JPS62147364A - Period variable circuit of sampling clock - Google Patents

Abstract

PURPOSE:To enable fine sampling of a required portion and effective use of memory, by sampling input data with a clock of different repeated period in response to the specified range. CONSTITUTION:A clock generating circuit 6 generates a plurality of clock, A, B of different repeated periods. Input data 1 are divided in the specified range and input to memory 4 and detecting circuit 5, the circuit 5 detects the specified range of the data 1 and compares a integrated pattern and the input data 1 and the compared output is transmitted to a clock selecting circuit 7. Clocks A, B have been supplied to the circuit 7 from the circuit 6 and the circuit 7 outputs one of the clocks A and B after selection. Consequently, one of the clocks A and B is to be supplied to a counter 3 and the memory 4 for effective use of the memory 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (a1 Technical Field of the Invention This invention provides a method for detecting
The present invention relates to a variable cycle circuit that can vary the cycle of a sampling clock of a logic analyzer.

(b) Conventional technology and problems The logic analyzer is a digital signal “0” and “1”
It is a logic behavior analyzer that displays data on multiple channels at once on a cathode ray tube by normalizing it using ``.

Next, FIG. 2 shows a block diagram of a sub/bling circuit of a logic analyzer according to the prior art.

In FIG. 2, 1 is input data, 2 is a clock generation circuit, 3 is a counter, and 4 is a memory.

The clock generating circuit 2 generates a sampling clock, and when adding this clock to the color/receiver 3, it also supplies it to the memory 4 as a write signal.

As a result, the input data 1 is written into the memory 4, and the address of the memory 4 is updated with the output of the counter 3.

The conventional technique shown in FIG. 2 cannot simultaneously satisfy the following requirements.

(a) Observe the rough movement of input data 1 for a long time.

(b) Look closely at a specific time relationship in input data 1.

In order to satisfy the requirement (i'), it is necessary to lengthen the sampling period, but if the sampling period is lengthened, the requirement (a) cannot be realized.

Furthermore, in order to satisfy the requirement (a), it is necessary to shorten the sampling period, but if the sampling period is shortened, the requirement (a) cannot be realized.

Generally, when observing data with a logic analyzer,
There are parts that should be observed, and parts that should be measured in detail.

However, with the conventional circuit shown in Figure 2, it is not possible to change the sampling period during observation, so it is possible to sample parts that are unnecessary or cannot be sampled as finely as necessary. 4 is required, and detailed time relationships cannot be observed.

(c) Purpose of the Invention The present invention provides the following features:
Logic that allows you to change the sampling period of the logic analyzer, allows you to perform long fi $1 even with a small capacity memory 4, and allows you to make detailed measurements of only a specific section. The purpose is to provide analyzers.

(d) Examples of the invention FIG. 1 shows a block diagram of an embodiment of the present invention.

The embodiment shown in FIG. 1 is an example in which the sampling period is changed depending on the pattern of input data 1.

In FIG. 1, 5 is a detection circuit, 6 is a clock generation circuit, and 7 is a clock selection circuit, and the other parts are the same as in FIG. That is, in FIG. 1, a detection circuit 5 and a clock selection circuit 7 are added to FIG. 2, and a clock generation circuit 6 is used in place of the clock generation circuit 2 in FIG.

The clock generation circuit 6 in FIG. 1 generates a plurality of clocks with different repetition periods. In FIG. 1, two clocks, clock A and clock B, are generated, but the number of clocks with different repetition periods may be increased. In FIG. 1, clock A has a longer repetition period than clock B.

Input data 1 in FIG. 1 is divided into multiple designated sections,
It is added to the memory 4 and the detection circuit 5.

The detection circuit 5 is for detecting a specified section of the input data 1, and in FIG. 1, it compares the built-in pattern with the input data 1, and transmits the comparison output to the clock selection circuit 7, as will be described in detail later. It looks like this.

The clock selection circuit 7 is supplied with the clock A and the clock B from the clock generation circuit 6, and based on the output of the detection circuit 5, the clock selection circuit 7 selects and outputs either the clock A or the clock B. Therefore, counter 3
Then, the memory 4 is supplied with either clock A or clock B.

Next, a waveform diagram of input data 1 is shown in FIG.

Figure 3 (a) is a waveform diagram of the first channel;
Figure (a) is a waveform diagram of the second channel.

In Figure 3 (7), there are designated sections of "1" and "0",
The specified interval of ``0'' is roughly <1dli911, and the specified interval of ``1'' is examined in detail! I shall do so.

FIG. 3(A) shows observed data, and in this embodiment, the pull/pull period is changed according to rlJ and rOJ in FIG. 3(A).

For example, when the first channel is "1", clock B
is the sampling clock, and the first channel is “0”.
”, clock A is used as the sampling clock.

As a result, the first
When the hand channel is "1", the data of the second channel can be observed in detail, and the first channel is "1".
0”, the data of the second channel is coarse <fi7!
vl can be done.

Next, a circuit diagram of an embodiment of the detection circuit 5 and the clock selection circuit 7 is shown in FIG.

“1” and “0” as shown in FIG. 3 (A) are supplied to the terminal 51 in FIG. 4 from the first channel of input data 1,
Data such as the third tooth (A) is supplied to the terminal 52 from the second channel of the input data 1.

Reference values for comparison are added to the terminals 53-56. Fourth
In the illustrated embodiment, "1" is supplied to terminal 53, and "1" is supplied to terminal 54.
"0" is supplied to 56.

Therefore, when the input to the terminal 51 is "1", the input to the terminal 57 is "1".
The output of the terminal 57 becomes "0", and when the input of the terminal 51 is "0", the output of the terminal 57 becomes "1".

A clock A is supplied to a terminal 72 in FIG. 4, and a clock B is supplied to a terminal 73.

Since the signal from terminal 57 is supplied to terminal 71,
When the input of terminal 71 is "1", the output of terminal 74 becomes clock A, and when the input of terminal 71 is "0", the output of terminal 74 becomes clock A.
The output of 4 becomes clock B.

From Figure 4, it can be seen that the period of the sapping clock can be changed to clock A or clock B, corresponding to "1" and "0" of the first channel, as indicated by the triangle marks in Figure 3. .

As means for detecting a plurality of specified sections of input data, in addition to pattern detection, it is possible to use trigger conditions such as enones, glitches, and time intervals of input data.

(e) Effects of the Invention According to the present invention, since the sampling period can be changed in accordance with the portion required for analysis, only the necessary portion can be sampled in detail.

Also, by changing the sampling period, memory 4
can be used effectively.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment according to the present invention, FIG. 2 is a block diagram of a conventional logic analyzer Su/Blinobu circuit, FIG. 3 is a waveform diagram of input data 1, and FIG. 4 is a block diagram of a detection circuit 5 and FIG. 7 is a circuit diagram of an embodiment of the clock selection circuit 7. FIG. 1...Input data, 2...Clock generation circuit, 3...Counter, 4...Memory, 5...Detection circuit, 6 ...Clock generation circuit, 7...Clock selection circuit, '51-
57...Terminal, 71-74...Terminal. Agent Patent Attorney Kinji Omata Figure 1 Figure 2 Input data memory

Claims (1)

[Scope of Claims] 1. A device comprising: a memory for inputting input data; a clock generation circuit for generating a sampling clock; and a counter for counting the clock; A sampling circuit that updates the address of the memory with a counter output, a detection circuit that divides the input data into a plurality of specified sections and detects the specified section, and a clock generation circuit that generates a plurality of clocks with different repetition periods. and a clock selection circuit that receives the plurality of clocks as input and selects one of the plurality of clocks based on the output of the detection circuit, and samples the input data with clocks having different repetition periods corresponding to the specified interval. A sampling clock cycle variable circuit characterized by: