JPS62146069A - Thermal line printer - Google Patents

Abstract

PURPOSE:To perform a data transfer with a simple circuit and at a high speed by sending the data of word parallel to be imaged to a parallel/series conversion circuit through a line buffer memory and a latch circuit, converting it to a serial data, and supplying it to a head block. CONSTITUTION:When a data is written on a line buffer memory 5, a CPU1 outputs a data request signal DRQ to a DMA controller 6. The data at the line buffer memory 5 is read out in order with a memory read signal MRD from the DMA controller 6. Next, the data at a latch circuit 21 is read out, and finally, the data at a latch circuit 2(n-1) is read out. A read out data is latched at latch circuits 20-2(n-1) with that timing. A timing signal generation circuit 7 supplies a load signal LD of row active, and the data latched at the latch circuits 20-2(n-1) are simultaneously loaded at shift registers 30-3(n-1), and are outputted bit by bit in serial with a shift clock SCLK following the load signal LD.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thermal line printer, and more specifically, proposes a data transfer circuit to its head.

[Prior art]

A thermal line printer is constructed in such a way that a plurality of head blocks each having a large number of dots are arranged in parallel in a direction perpendicular to the direction of paper movement, and are used to sequentially print a line-shaped dot pattern.

FIG. 5 is a block diagram schematically showing a circuit for transferring data to be printed.
, 513, 514, . . . are stored in word parallel memory.
1゜522, 523, 524... and converts it into serial data, and each serial data is sent to the line head 5.
3 each pronoc 531, 532, 533, 534...
I try to give it to

[Problem that the invention seeks to solve]

To perform such transfer at high speed, a complicated circuit is required, which hinders the miniaturization of printer circuits.

[Means for solving problems]

The present invention has been made to solve these problems, and uses DMA (Direct Memory Acc
An object of the present invention is to provide a thermal line printer that can perform high-speed data transfer with a simple circuit by using ess) transfer.

The thermal printer according to the present invention is equipped with a thermal line head made up of a plurality of head blocks arranged side by side in the line direction, and converts word-parallel data into serial data and provides it to each head block for printing. A thermal line printer includes a direct memory access controller having direct memory access channels equivalent to the number of head blocks, a line buffer memory storing word-parallel data to be printed, and a direct memory access controller having direct memory access channels equivalent to the number of head blocks. A latch circuit that temporarily stores the data accessed by the memory access controller and read from the line buffer memory in correspondence with the head block to which it should be given, and converts the data latched into the latch circuit into serial data. The direct memory access channel is characterized in that it includes a parallel/serial conversion circuit for supplying signals to each head block, and simultaneously activates the direct memory access channels in order of priority.

(Operation) Parallel word data to be printed is sent from the line buffer memory to the latch circuit, from where it is applied to the parallel/serial conversion circuit, converted into serial data, and applied to the head block. This makes it possible to provide printing data to the head block at high speed.

〔Example〕

The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram of main parts showing an embodiment of the present invention. The thermal line head 4 has n head blocks 40
．． 41...4(n-1) are arranged in parallel in the line direction, and shift registers 30, 31...3(n-1) convert m-bit parallel data into serial data.
1> are respectively inputted and printed.

The CPU is in charge of overall control of this printer, and is connected to the ROM2. RAM 3 for storing other data
The address bus B[IS and data bus D-BIIS are connected to a line buffer memory 5 and a DMΔ controller 6 that store data to be printed. Furthermore, the data bus D-BI
JS is connected to latch circuits 20, 21...2n.

A memory write signal MWT is applied to the line buffer memory 5 from the CPUI, and thereby the line buffer memory 5 becomes a writable state, and the address bus A-BII
Data input via the data bus o-Bus is written in accordance with the input address from S.

The memory read signal MRD is given from the DMA controller 6 and data is transferred to the data bus D-8 according to the manual address.
Read out to US.

The DMA controller 6 has n DMA channels, and when the I10 port 8 issues an IIRQ signal, it is sent to the terminals DRQO and DRQO provided corresponding to each channel.
Each channel is activated in response to DRQI-DRQ(n-1).

Each DMA channel has a data acknowledge signal output terminal D.
A(JO, DACKI = DACK(n-1), and each output signal is connected to n AND gates 10.11-Hn-
1), and these A
The 10g inclusive signal IOW of the DMA controller 6 is applied to the other input terminals of the ND gates 10.11...1 (n-1). Latch circuit 20.21...2(n-1
) are given the outputs of AND gates 10.11...1(n-1) to their respective latch command signal input terminals G.

For example, 8-bit data read from the line buffer memory 5 is applied to the input terminals of the latch circuits 20, 21, . . . 2 (n-1), and is latched at the timing when the terminal G becomes high level.

Output terminal 0 of latch circuit 20.21...2(n-1)
1JT is shift register 30.31...3(n-1)
is connected to the parallel input terminal IN.

Reference numeral 7 designates a timing signal generation circuit for the shift register, which generates a load signal LD after receiving the output from the AND gate 0n-1), and transmits the load signal LD to the shift registers 30, 31, . . .
・Give it to the terminal LD of 3(n-1) to load the input data.

After that, the timing signal generation circuit 7 generates a shift clock 5C.
LK is issued and shift registers 30, 31...3 (n-
1), and the parallel input is serially output one bit at a time from the terminal OUT to be applied to each of the head blocks 40, 41, . . . , 4 (n-1).

FIG. 2 is a time chart for explaining the operation of this circuit. When data is written to the line panzer memory 5, the CPt1l sets the DMA start address of each DMA channel and the number of bytes of data to be transferred to the DMA controller 6. and control bus C-Bu
s, outputs a data request/quest signal DRQ via I10 port 8. Terminal ORG of DMA controller 6
O, DRQ 1-DRQ(n-1) has a signal -
1) R (1 is given, but priority is given to the channel with the smaller number, and as shown in Fig. 2 fbl, the data acknowledge signal is DACK O, DACK 1...
- The level becomes high in the order of DACK(n-1). After a short delay, the DMA controller 6 sets the memory read signal MRD and the 0-write signal 0- to a high level (FIG. 2 (C1, (d)). Memory read signal MR
D causes the data in the line pan store memory 5 to be sequentially read out. In this order, data to be latched by the latch circuit 20 (that is, data to be printed by the head block 40) is given priority, then data from the latch circuit 21 (head block 41) is read out, and finally data to be latched by the latch circuit 20 is read out.
(n-1) (head block 4 (n-1)) data is read out [FIG. 2(e)]. When the signal IOW becomes high level, the output of the AND gates 10.11...Hn4) becomes high level, so the data read out as described above is transferred to the latch circuits 20.21...
・Latched at 2(n-1). On the other hand, AND gate 1 (
n-1) As the output becomes high level, the timing signal generation circuit 7 synchronizes with the system clock (given to the timing signal generation circuit 7 from a clock generation circuit not shown) shown in FIG. 2(a). Low active load signal Ll) (Emits the 211iJ(f)3).

As a result, the data latched in the latch circuits 20, 21...2 (n-1) are simultaneously transferred to the shift register 30.
．． 31...3(n-1), and the load signal L
The shift clock 5CLK (FIG. 2 (gl)) following D is serially output one bit at a time. This output data is Qm, Qm-t... in the case of m-bit data as shown in FIG. The order is Q 2 + Q l.The shift clock 5CLK needs to be fast enough to shift out m bits before the data of n3 is latched into the latch circuit.

FIG. 3 shows a block diagram of the main parts of the printer of the present invention when 8-bit parallel data (m=8) is written and printed on four bottom processors (n-4), and is similar to FIG. The same reference numerals are given to the parts. Further, FIG. 4 is a time chart showing the operation of this circuit, and its contents are the same as those in FIG. 2.

Now, in the circuit of FIG. 3, the configuration of the timing signal generation circuit 7 is illustrated in detail. In other words, this circuit 7 has three D
= Frisopfront 71, 72.74, a counter 78 with an output of "23", and two AND gates 73.7
6 and two inverters 75.77. The clock CLK generated by the DMA controller 6 is connected to the clock terminals CK and AN of the D-flip-flop 71.
It is applied to one terminal of D gate 73. Further, the output of the AND game H3 is given to the D terminal of the D-flip flop 71. The enable reset output of the D-flip-flop 77 is the load signal LD of the shift registers 30 to 33.
It becomes. This output page also shows the clock terminal C of the D-flip-flop 72 with the D terminal fixed at high level.
It is given to K. The set output Q of the D-flip-flop 72 is the other input of the AND gate 71. The output of AND gate 73 is D-flip-flop 74
is applied to the clock terminal CK of. The reset output of this D-flip-flop 74 is possible with shift clock 5C.
It is applied as LK to the shift registers 33 to 33 and also to its own D terminal. Further, the output Q thereof is inputted to the negative logic counting terminal of the counter 78.

When the count value reaches 23, the counter 78 generates a carry signal from its output, which is input to the inverter 17, and the output of the inverter 17 becomes one input of the AND gate 76.

The other input to the AND gate 76 is a signal HDWR which is kept at low level except when data is transferred from the line buffer memory 5 to the thermal line head 4. It serves as an input to the logic clear signal terminal CLR and impark 75. The output of the inverter 75 is then sent to the counter 78.
is applied to the clear signal terminal CLR of.

The operation of the above timing signal generation circuit 7 will be explained. While DACK3 is at a high level, as shown in FIG. 4 fd), when the signal 10W becomes a high level, the output of the AND gate 13 becomes a high level. Therefore, in the meantime, DMA
Since the D-flip-flop 71 is set at the timing when the clock CLK outputted by the controller 6 changes to high level, its reset output page, that is, as shown in FIG.
The load signal LD shown in ) changes to low level, and the shift registers 30 to 33 latch the output data of the latch circuits 20 to 23, respectively.

Since the signal ION then changes to a low level, the D-flip-flop 71 is reset at the next rising edge of the clock C1, and the output, that is, the load signal LD returns to a high level. Then D-flip-flop 72
is set and the Q output becomes high level, so the output of the AND gate 73 changes according to the input of the clock CLK, and therefore this is the page output of the D-flip-flop 74, that is, the fourth output.
It will be given to the shift registers 30 to 33 as the shift clock 5CLK shown in the figure (phantom).On the other hand, the Q output of the flip-flop 74 is input to the counter 78, so when it reaches 8, a carry signal is sent from its 23 terminal. This causes the output of the AND gate 76 to go low.This clears the flip-flops 72 and 74 and returns to the original state.

Note that when data is not being transferred, the signal +1 [IW
R becomes low level, D-flip-flop 72.7
4 is forcibly cleared, shift clock 5CLK is not output during this period.

〔effect〕

According to the present invention as described above, data transfer from the line buffer memory to the thermal line head can be performed quickly, and the circuit can be configured simply.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of the printer of the present invention, FIG. 2 is a time chart for explaining its operation, FIG. 3 is a block diagram showing the timing signal generation circuit in detail, and FIG.
The figure is an explanatory diagram of the operation, and FIG. 5 is a schematic block diagram of the data transfer system of the thermal line printer.

Claims (1)

[Claims] 1. A thermal line printer equipped with a thermal line head having a plurality of head blocks arranged side by side in the line direction, and configured to convert word-parallel data into serial data and provide it to each head block for printing. Direct memory access equivalent to the number of head blocks
A direct memory access controller with a channel, a line buffer memory storing word-parallel data to be printed, and data accessed by the direct memory access controller and read from the line buffer memory. a latch circuit that temporarily stores the data in correspondence with the head block to which it is to be applied, and a parallel/serial conversion circuit that converts the data latched in the latch circuit into serial data and provides it to each head block, A thermal line printer characterized in that the direct memory access channels are activated simultaneously in sequential order of priority.