JPS62145865A - Solid-stage image pickup device - Google Patents

Solid-stage image pickup device

Info

Publication number
JPS62145865A
JPS62145865A JP60287338A JP28733885A JPS62145865A JP S62145865 A JPS62145865 A JP S62145865A JP 60287338 A JP60287338 A JP 60287338A JP 28733885 A JP28733885 A JP 28733885A JP S62145865 A JPS62145865 A JP S62145865A
Authority
JP
Japan
Prior art keywords
type impurity
region
impurity region
well region
section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60287338A
Other languages
Japanese (ja)
Other versions
JPH06105782B2 (en
Inventor
Atsushi Honjo
本庄 敦
Tetsuo Yamada
哲生 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60287338A priority Critical patent/JPH06105782B2/en
Publication of JPS62145865A publication Critical patent/JPS62145865A/en
Publication of JPH06105782B2 publication Critical patent/JPH06105782B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14643Photodiode arrays; MOS imagers

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Abstract

PURPOSE:To eliminate an after-image of a signal charge when transferring an image from a photosensor to a transfer unit by forming the depths of junctions of a first conductivity type well region at the lower center and the lower end of the photosensor substantially the same and forming the depth of the junction of the photosensor deeper than that of the junction of the transfer unit. CONSTITUTION:The depth of the junction of a p-type well region 2 is, for example, 4mum, the depths of a shallow well region (the depth of the junction is, for example, 3mum) and a deep well region (the depth of the junction is, for example, 5mum) are provided in a conventional example. In comparison, uniform depths of junctions are provided. An n<+> type impurity region 3 is formed as a photosensor for storing a signal charge generated by an incident light on the surface of the region 3. The depth of the junction of the region 3 is, for example, 3mum which is to be deeper than the conventional example in which the depth of the junction has been, for example, 2mum.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は固体撮像装置に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a solid-state imaging device.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

従来の感光部と転送部とが別々になっている固体撮像装
置は、第4図に示されるように、半導体基板1表面にp
型ウェル領域22が形成されていて、このp型ウェル領
域22の接合の深さが例えば3μ肌と浅く、不純物積分
濃度が低いシA・ロー・ウェル(Shallow We
ll)領域表面に感光部としてn+型不純物領域23が
設けられ、またp型ウェル領域12の接合の深さが例え
ば5μmと深く、不純物積分濃度が高いディープ・ウェ
ル(DeepWell)領域表面に転送部としてのn+
型不純物領域25.26が設(プられている。そしてp
型ウェル領域22は接地され、半導体基板1には15V
の基板電圧が印加されている。
A conventional solid-state imaging device in which a photosensitive section and a transfer section are separate has a photosensitive layer on the surface of a semiconductor substrate 1, as shown in FIG.
A type well region 22 is formed, and the p-type well region 22 has a shallow junction depth of, for example, 3μ, and has a low integrated impurity concentration.
ll) An n+ type impurity region 23 is provided on the surface of the region as a photosensitive region, and a transfer region is provided on the surface of a deep well region where the junction depth of the p-type well region 12 is as deep as, for example, 5 μm, and the integrated impurity concentration is high. n+ as
Type impurity regions 25 and 26 are provided.
The mold well region 22 is grounded and the semiconductor substrate 1 has a voltage of 15V.
A substrate voltage of is applied.

これらは電荷がp型ウェル領域22を通って半導体基板
1に排出される機能を感光部においてのみ有するように
するだめの縦形オーバフロードレイン(Vertica
l Overflow Drain )構造を形成して
いる。
These are vertical overflow drains (Vertica
l Overflow Drain ) structure is formed.

すなわち感光部としてのn+型不純物領域23の接合の
深さが2μ兜とすやと、n+型不純物領域23下方のp
型ウェル領域22は厚さが1μmと薄(、不純物積分濃
度も低いため、信号電荷の多少にかかわらず、p型ウェ
ル領域22の上下2つの接合における空乏層が互に結合
して、ここにおけるp型ウェル領域22の電位はoVよ
り高くなり、n+型不純物領域23に発生した過剰電荷
は半導体基板1に排出される。そして転送部としてのn
 ・型不純物領域25下方のp型ウェル領域22は厚さ
が厚く、不純物積分濃度も高いために、n+型不純物領
域25の信号電荷が失われたり、半導体基板1からn+
型不純物領域25に電荷が注入されたりすることが防止
される。
That is, if the junction depth of the n+ type impurity region 23 as a photosensitive part is 2μ, the depth of the junction below the n+ type impurity region 23 is 2 μm.
Since the p-type well region 22 is as thin as 1 μm in thickness (and the integrated impurity concentration is low, the depletion layers at the upper and lower junctions of the p-type well region 22 are coupled to each other regardless of the amount of signal charge, and the The potential of the p-type well region 22 becomes higher than oV, and the excess charge generated in the n+ type impurity region 23 is discharged to the semiconductor substrate 1.
- Since the p-type well region 22 below the type impurity region 25 is thick and has a high integrated impurity concentration, the signal charge in the n+ type impurity region 25 may be lost or the n+
Charges are prevented from being injected into the type impurity region 25.

また第4図に示されるように、感光部としてのn+型不
純物領域23表面にp+型不純物領域24が設けられ、
B P D (Burried Photo Diod
e埋め込みホトダイオード)構造が形成されている。
Further, as shown in FIG. 4, a p+ type impurity region 24 is provided on the surface of an n+ type impurity region 23 serving as a photosensitive portion.
B P D (Burried Photo Diod)
e buried photodiode) structure is formed.

これは埋め込まれたn+型不純物領域23の蓄積容量を
大きくし、また完全空乏化を可能にするためである。さ
らにまた、p+型不純物領域24に蓄積された信号電荷
が読み出し時に完全に転送されずに残留することを防ぐ
ためである。この残留した信号電荷は、熱運動のエネル
ギにより、次の読み出し時に流出することによって残像
を起こす。
This is to increase the storage capacity of the buried n+ type impurity region 23 and to enable complete depletion. Furthermore, this is to prevent signal charges accumulated in the p+ type impurity region 24 from remaining without being completely transferred during reading. This residual signal charge flows out during the next readout due to the energy of thermal motion, thereby causing an afterimage.

従って、感光部としてのn+型不純物領域23に蓄積さ
れた信号電荷が読み出し時にできるだけ完全に読み出さ
れて、残像が起きないようにしている。
Therefore, the signal charge accumulated in the n+ type impurity region 23 as a photosensitive portion is read out as completely as possible during readout, thereby preventing an afterimage from occurring.

いま第5図に感光部の中央部におけるA−A’線断面の
深さ方向の完全空乏時のポテンシャル分布を示す。感光
部としてのn 型不純物領域23の完全空乏時の電位の
極大値は例えば7.5V程度に設計されているので、転
送部としてのn+型不純物領域25の電位が7.5V以
上になるように転送電極9に例えば8V〜10v程度の
読み出し電圧を印加すれば、感光部としてのn+型不純
物領域23に蓄積された信号電荷は読み出し時において
転送部としてのn+型不純物領域25に完全に読み出さ
れると考えられる。
FIG. 5 shows the potential distribution in the depth direction of a cross section taken along the line A-A' in the central part of the photosensitive area at the time of complete depletion. Since the maximum value of the potential of the n-type impurity region 23 as a photosensitive region when fully depleted is designed to be approximately 7.5V, for example, the potential of the n+-type impurity region 25 as a transfer region is set to be 7.5V or more. When a read voltage of, for example, about 8 V to 10 V is applied to the transfer electrode 9, the signal charge accumulated in the n+ type impurity region 23 as a photosensitive part is completely read out to the n+ type impurity region 25 as a transfer part at the time of reading. It is thought that

しかしながら、上記従来の固体撮像装置においては、第
4図に示されるように、感光部の端部下方におけるp型
ウェル領域22の接合の深さはn 型不純物領域23の
外周方向に向って徐々に深くなっている。また同−深さ
におけるp型不純物領域も同様な傾向で高くなっている
。これらはn 型不純物領域23の外周に隣接するp型
ウェル領域22のデープ・ウェル領域から感光部下方の
p型ウェル領域22のシャロー・ウェル領域に向って、
p型不純物が熱工程によって横方向に拡散されることか
ら生じる。
However, in the above-mentioned conventional solid-state imaging device, as shown in FIG. It's getting deeper. Furthermore, the p-type impurity region at the same depth also has a similar tendency to become high. These extend from the deep well region of the p-type well region 22 adjacent to the outer periphery of the n-type impurity region 23 toward the shallow well region of the p-type well region 22 below the photosensitive area.
This occurs because p-type impurities are laterally diffused by a thermal process.

いま第6図に感光部の端部におけるB−B’線断面の深
さ方向の完全空乏時のポテンシャル分布を示す。感光部
としてのn+型不純物領域23下方のp型ウェル領域2
2の不純物積分濃度が感光部の中央部下方におけるそれ
よりも高くなっているため、第6図に示されたn+型不
純物領域23の完全空乏時の電位の極大値は第5図に示
されたそれよりも低くなっている。
Now, FIG. 6 shows the potential distribution in the depth direction of a cross section taken along the line B-B' at the end of the photosensitive section in the case of complete depletion. P-type well region 2 below n+-type impurity region 23 as a photosensitive region
Since the integrated impurity concentration of 2 is higher than that below the center of the photosensitive area, the maximum value of the potential when the n+ type impurity region 23 shown in FIG. 6 is completely depleted is as shown in FIG. It is lower than that.

また第7図に、読み出し時の信号電荷の移動に添ったT
1−Ml−M2−T2−T3−T4線断面における例え
ば9Vの読み出し電圧を転送電極9に印加した完全空乏
時のポテンシャル分布を示す。第5図および第6図から
明らかなように、感÷ 先部としてのn 型不純物領域23の端部の点M2にお
ける電位は、中央部の点M1における電位よりも低い。
Figure 7 also shows the T
1-Ml-M2-T2-T3-T4 line cross section shows a potential distribution at the time of complete depletion when a read voltage of, for example, 9V is applied to the transfer electrode 9. As is clear from FIGS. 5 and 6, the potential at point M2 at the end of n-type impurity region 23 serving as the sensing tip is lower than the potential at point M1 at the center.

このため信号電荷が感光部としてのn+型不純物領域2
3から転送部としてのn+型不純物領域25に移動す際
、第7図に示されるように、n+型不純物領域23の端
部(点M2)に電位障壁が生じる。この電位障壁により
信号電荷の一部が01型不純物領域23に残留し、この
残留した信号電荷が熱運動のエネルギにより徐々に流出
して、残像を生じる大きな原因となる。このにうに上記
従来の固体撮像装置は残像を生じるという問題を有して
いた。
Therefore, the signal charge is transferred to the n+ type impurity region 2 as a photosensitive area.
3 to the n+ type impurity region 25 serving as the transfer section, a potential barrier is generated at the end (point M2) of the n+ type impurity region 23, as shown in FIG. A portion of the signal charge remains in the 01 type impurity region 23 due to this potential barrier, and this remaining signal charge gradually flows out due to the energy of thermal motion, which is a major cause of afterimages. However, the above-mentioned conventional solid-state imaging device has the problem of producing an afterimage.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、感光部から転送部に転送される際の信
号電荷の残像をなくし、残像の少ない固体撮像装置を提
供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate afterimages of signal charges when transferred from a photosensitive section to a transfer section, and to provide a solid-state imaging device with less afterimages.

〔発明の概要〕[Summary of the invention]

本発明は、半導体基板と、この半導体基板表面に形成さ
れた第1導電型ウェル領域と、この第1導電型ウェル領
域表面に第2導電型不純物を添加して形成され、入射光
により生成される信号電荷を蓄積する感光部と、第1導
電型ウェル領域表面に第2導電型不純物を添加して形成
され、信号電荷を転送する転送部と、この転送部と感光
部との間に設けられ、感光部に蓄積された信号電荷を転
送部に読み出す読み出し部とを有する固体撮像装置にお
いて、感光部の中央部下方および端部下方のそれぞれに
おける第1導電型ウェル領域の接合の深さがほぼ同一で
あり、感光部の接合の深さが転送部の接合の深さにり深
いことを特徴とする。
The present invention includes a semiconductor substrate, a first conductivity type well region formed on the surface of the semiconductor substrate, and a second conductivity type impurity formed by adding a second conductivity type impurity to the surface of the first conductivity type well region. a photosensitive section that accumulates signal charges, a transfer section that is formed by adding a second conductivity type impurity to the surface of the first conductivity type well region and transfers the signal charges, and a transfer section that is provided between the transfer section and the photosensitive section. In a solid-state imaging device having a readout section that reads out signal charges accumulated in the photosensitive section to a transfer section, the depth of the junction of the first conductivity type well region under the center and below the end of the photosensitive section is determined. They are almost the same, and are characterized in that the depth of the junction in the photosensitive part is deeper than the depth of junction in the transfer part.

これにJ−り感光部の端部に電位障壁が生じないように
して、残留電荷のない信号電荷の完全な読み出しが行な
われるようにすると共に、感光部下方における第1導電
型ウェル領域の厚さが薄くなり、勘号部の過剰電荷が半
導体基板に排出されるようにしたものである。
In addition, a potential barrier is not generated at the edge of the photosensitive area to ensure complete readout of signal charges without residual charges, and the thickness of the first conductivity type well region below the photosensitive area is The structure is made thinner, and the excess charge in the contact area is discharged to the semiconductor substrate.

〔発明の実施例〕[Embodiments of the invention]

本発明の一実施例による固体撮像装置の断面を第1図に
示す。例えばn型シリコン基板からなる半導体基板1表
面にp型ウェル領域2が形成されている。このp型ウェ
ル領域2の接合の深さは例えば4μmであり、従来例が
シャロー・ウェル領域く接合の深さは例えば3μ而であ
る)とディープφウェル領域(接合の深さは例えば5 
ilmである)とを有していたのに比べると、均一な接
合の深さを有している点に特徴がある。まtc p型ウ
ェル領域2の不純物a度分布においても、同一の深さで
は同一の不純物濃度を有している。
FIG. 1 shows a cross section of a solid-state imaging device according to an embodiment of the present invention. A p-type well region 2 is formed on the surface of a semiconductor substrate 1 made of, for example, an n-type silicon substrate. The junction depth of this p-type well region 2 is, for example, 4 μm, and the conventional example is a shallow well region (the junction depth is, for example, 3 μm) and the deep φ well region (the junction depth is, for example, 5 μm).
It is characterized in that it has a uniform bonding depth, compared to the conventional method (Ilm). Also, in the impurity degree distribution of the tc p-type well region 2, the impurity concentration is the same at the same depth.

p型ウェル領域2表面には、入射光ににり生成される信
号電荷を蓄積する感光部としてのn゛型不純物領域3が
形成されている。このn4型不純物領域3の接合の深さ
は例えば3μmであり、従来例の接合の深さが例えば2
μmであったのに比べると、接合の深さが深くなってい
る点に特徴がある。
On the surface of the p-type well region 2, an n-type impurity region 3 is formed as a photosensitive portion for accumulating signal charges generated by incident light. The depth of the junction of this n4 type impurity region 3 is, for example, 3 μm, and the depth of the junction of the conventional example is, for example, 2 μm.
The feature is that the depth of the bond is deeper than that of μm.

感光部としてのn+型不縄物領域3表面にp+型不純物
領域4が設けられ、BPD構造が形成されている。これ
により、埋め込まれたn+型不純物領域3は蓄積容量が
大きくなり、また完全空乏化が可能となる。
A p+ type impurity region 4 is provided on the surface of an n+ type impurity region 3 serving as a photosensitive portion, forming a BPD structure. As a result, the buried n+ type impurity region 3 has a large storage capacity and can be completely depleted.

またp型ウェル領域2表面には、信号電荷を転送する転
送部としてのn+型不純物領域5,6が形成されている
。そして感光部としてのn4型不純物領域3と転送部と
してのn+型不純物領域5との間には、n1型不純物領
域3に蓄積された信号電荷をn+型不純物領域5に読み
出す読み出し部が設けられている。ざらにn+型不純物
領域3と隣接する画素の転送部としてのn+型不純物領
域6との間に、p+型不純物が添加されたヂトンネル・
ストッパ7が形成されている。
Further, on the surface of the p-type well region 2, n+-type impurity regions 5 and 6 are formed as transfer portions for transferring signal charges. A readout section is provided between the n4 type impurity region 3 as a photosensitive section and the n+ type impurity region 5 as a transfer section, for reading out the signal charges accumulated in the n1 type impurity region 3 to the n+ type impurity region 5. ing. Roughly speaking, there is a di-tunnel layer doped with p+ type impurities between the n+ type impurity region 3 and the n+ type impurity region 6 serving as a transfer portion of an adjacent pixel.
A stopper 7 is formed.

また転送部どしてのn+型不純物領域5,6および読み
出し部の上方には、絶縁膜8を介して転=  8 − 送電極9が形成されている。そしてAl−8iからなる
光遮蔽膜(図示せず)が感光部を除いて全面を覆ってい
る。さらに仝而を表面保護膜(図示せず)が覆っている
。さらにまたp型ウェル領域2は接地され、半導体基板
1には15Vの基板電圧が印加されている。
Further, a transfer electrode 9 is formed above the n+ type impurity regions 5 and 6 serving as the transfer section and the readout section with an insulating film 8 interposed therebetween. A light shielding film (not shown) made of Al-8i covers the entire surface except for the photosensitive area. Furthermore, it is covered with a surface protective film (not shown). Furthermore, the p-type well region 2 is grounded, and a substrate voltage of 15V is applied to the semiconductor substrate 1.

次に本実施例による固体撮像装置の製造工程を説明する
。まずn型シリコン基板からなる半導体基板1表面を酸
化して絶縁膜8を形成する。イして全面に硼素Bをイオ
ン注入し、アニール処理を行なってp型つIル領域2を
形成する。このp型ウェル領域2表面に燐Pをイオン注
入し、アニール処理を行なって感光部としてのn”型不
純物領域3を形成する。
Next, the manufacturing process of the solid-state imaging device according to this embodiment will be explained. First, an insulating film 8 is formed by oxidizing the surface of a semiconductor substrate 1 made of an n-type silicon substrate. Then, boron B is ion-implanted over the entire surface, and annealing is performed to form a p-type trench region 2. Phosphorus P is ion-implanted into the surface of this p-type well region 2, and annealing is performed to form an n''-type impurity region 3 as a photosensitive portion.

また、p型ウェル領域2表面に転送部としてのn+型不
純物領域5.6を形成するための砒素A3をイオン注入
し、次にヂVンネル・ストッパ7を形成するための硼素
Bをイオン注入し、さらに転送部および読み出し部の上
方に絶縁膜8を介してvAPがドープされたポリシリコ
ンからなる転送電極9を形成し、さらにまた感光部とし
てのn+型不純物領域3表面にp+型不純物領域4を形
成するための硼素Bをイオン注入した後、アニール処理
を行なう。
Furthermore, arsenic A3 is ion-implanted to form an n+-type impurity region 5.6 as a transfer region on the surface of the p-type well region 2, and then boron B is ion-implanted to form a di-V channel stopper 7. Further, a transfer electrode 9 made of polysilicon doped with vAP is formed above the transfer section and the readout section via an insulating film 8, and a p+ type impurity region is further formed on the surface of the n+ type impurity region 3 serving as a photosensitive section. After ion implantation of boron B to form 4, an annealing process is performed.

さらに全面にAl−8iからなる光遮蔽膜を形成した後
、感光部に対応する部分を開口し、シンタリング(5i
nterino )を行なう。最後に全面に表面保護膜
を形成する。
Furthermore, after forming a light shielding film made of Al-8i on the entire surface, the portion corresponding to the photosensitive area is opened and sintered (5i
terino). Finally, a surface protective film is formed on the entire surface.

次に本実施例による固体撮像装置の読み出し時の信号電
荷に移動に添ったT1−Ml−M2−T  −T  −
T4線断面における完全空乏時のボテンシャル分布を第
3図に示す。点M1および点M2はそれぞれ感光部とし
てのn+型不純物領域3の中央部および端部におけるポ
テンシャル極大点であり、n+型不純物領域3の厚さの
中程に位置している。点T1はn 型不純物領域3とチ
ャンネル・ストッパ7との境界にあって、点M1と同じ
深さに位置している。点T2はn+型不純物領域3と読
み出し部との境界にあって、点M2と同じ深さに位置し
ている。点T4は転送部としてのn+型不純物領域5に
お【プるポテンシャル極大点であり、n+型不純物領域
5の厚さの中程に位置している。点T3はn+型不耗物
領域5と読み出し部との境界にあって、点T4と同じ深
さに位置している。
Next, T1-Ml-M2-T-T-
FIG. 3 shows the potential distribution at the time of complete depletion in the T4 line cross section. Point M1 and point M2 are maximum potential points at the center and end portions of n+ type impurity region 3 as a photosensitive portion, respectively, and are located in the middle of the thickness of n+ type impurity region 3. Point T1 is located at the boundary between n-type impurity region 3 and channel stopper 7, and at the same depth as point M1. Point T2 is located at the boundary between n+ type impurity region 3 and the readout section and at the same depth as point M2. The point T4 is the maximum potential point applied to the n+ type impurity region 5 as a transfer portion, and is located in the middle of the thickness of the n+ type impurity region 5. The point T3 is located at the boundary between the n+ type consumable area 5 and the reading section, and is located at the same depth as the point T4.

いま感光部としてのn+型不純物領域3の完全空乏時の
電位の極大値は例えば8■に設計されているので、転送
部としてのn+型不純物領域5の電位が8■以上になる
ように転送電極9に例えば10V程度の読み出し電圧を
印加すると、感光部としてのn+型不純物領域3に蓄積
された信号電荷は読み出し時において転送部としてのn
+型不純物領域5に読み出される。このとき感光部とし
てのn4型不純物領域3の中央部下方および端部下方の
それぞれにお【ノるp型ウェル領域2は、接合の深さに
おいても、深さ方向の不純物濃度の分布においても差が
ないため、第3図に示されるように、完全空乏時におけ
る電位の極大値はn+梨型−11− 不純物領域3の中央部(点M )と端部点(−2)とで
差がな〈従来例のようなn+型不純物領域3の端部(点
M2)に信号電荷の移動を妨げる電位障壁が生じること
はない。′このため信号電荷はn+型不純物領域3に残
留することなく、完全に読み出される。このようにして
、本実施例によれば、感光部に残留電荷を生じさせるこ
となく、残像の発生を防ぐことができる。
The maximum value of the potential when fully depleted of the n+ type impurity region 3 as a photosensitive area is designed to be, for example, 8■, so the transfer is performed so that the potential of the n+ type impurity region 5 as a transfer area is 8■ or more. When a read voltage of, for example, about 10 V is applied to the electrode 9, the signal charges accumulated in the n+ type impurity region 3 as a photosensitive part are transferred to the n+ type impurity region 3 as a transfer part during reading.
The signal is read out to the + type impurity region 5. At this time, the p-type well region 2 is formed under the center and under the end of the n4-type impurity region 3 as a photosensitive region, both in the junction depth and in the impurity concentration distribution in the depth direction. Since there is no difference, as shown in Fig. 3, the maximum value of the potential at the time of complete depletion is different between the center (point M) and the end point (-2) of the n+ pear-shaped -11- impurity region 3. However, unlike the conventional example, no potential barrier is generated at the end (point M2) of the n+ type impurity region 3 that hinders the movement of signal charges. 'Therefore, the signal charge does not remain in the n+ type impurity region 3 and is completely read out. In this way, according to this embodiment, it is possible to prevent the occurrence of afterimages without generating residual charges in the photosensitive portion.

また、接合の深さ4μmg)p型ウェル領域2表面に3
μmという接合の深さの深い感光部としてのn+型不純
物領域3が形成されているため、このn+型不純物領域
3下方のp型ウェル領域2の厚さは縦形オーバフロード
レイン構造を有する従来例と同じ1μmと薄くなってい
る。このため信号電荷の多少にかかわらず、n+型不純
物領域3とp型ウェル領域2の接合およびp型ウェル領
域2と半導体基板1との接合のそれぞれにおける空乏層
が互に結合して、ここにおけるp型ウェル領域2の電位
はOvより高くなり、n+型不純物領域3に発生した過
剰電荷は半導体基板1に排出される。このようにして本
実施例によれば縦形オーバフロードレイン構造を有する
場合と同様に、感光部に発生した過剰電荷を半導体基板
1に排出する機能を有し、スミア・ブルーミング現象を
防止することことができる。
In addition, the junction depth is 4 μmg) 3 μm on the surface of the p-type well region 2.
Since the n+ type impurity region 3 is formed as a photosensitive region with a deep junction depth of μm, the thickness of the p type well region 2 below the n+ type impurity region 3 is smaller than that of the conventional example having a vertical overflow drain structure. It is also thinner at 1 μm. Therefore, regardless of the amount of signal charge, the depletion layers at the junction between the n+ type impurity region 3 and the p-type well region 2 and the junction between the p-type well region 2 and the semiconductor substrate 1 are combined with each other, The potential of p-type well region 2 becomes higher than Ov, and excess charges generated in n+-type impurity region 3 are discharged to semiconductor substrate 1. In this way, this embodiment has the function of discharging excess charge generated in the photosensitive area to the semiconductor substrate 1, as in the case of having a vertical overflow drain structure, and can prevent the smear blooming phenomenon. can.

また転送部としてのn+型不純物領域5は、感光部とし
てのn+型不純物領域3と比べて相対的に接合の深さが
浅くなっているため、n+型不純物領域5下方のp型ウ
ェル領域2は厚さが厚く、不純物積分濃度も高くなって
いる。このためn+型不純物領域5の信号電荷が失われ
たり、n+型不純物領域5に半導体基板1から電荷が注
入されたりすることを防止することができる。
Furthermore, since the n+ type impurity region 5 serving as a transfer portion has a relatively shallow junction depth compared to the n+ type impurity region 3 serving as a photosensitive portion, the p type well region 2 below the n+ type impurity region 5 is thicker and has a higher integrated impurity concentration. Therefore, loss of signal charges in n+ type impurity region 5 and injection of charges from semiconductor substrate 1 into n+ type impurity region 5 can be prevented.

なお上記実施例におけるBPD構造を形成しているp+
型不純物領域4は、読み出し部側において感光部として
のnF型不純物領域3より小さいものであってもよい。
Note that p+ forming the BPD structure in the above example
The type impurity region 4 may be smaller than the nF type impurity region 3 serving as a photosensitive portion on the reading section side.

この場合の固体撮像装置の断面を第2図に示す。また製
造上の誤差により逆にp型ウェル領域4がn+型不耗物
領域より大ぎいものであってもよい。
A cross section of the solid-state imaging device in this case is shown in FIG. Furthermore, due to manufacturing errors, the p-type well region 4 may be larger than the n+-type consumable region.

また上記実施例において、転送部はn+型不純物領域5
からなる埋め込み転送チャンネル構造となっているが、
n+型不純物領域5がないm造でもよい。p+型不純物
領域からなるチャンネル・ストッパ7の接合の深さは、
第1図ないし第2図に示された深さに限定される必要は
なく、あるいはまたチャンネル・ストッパ7そのものも
なくてもよい。また半導体基板1に印加される基板電圧
は、上記実施例の15Vに限定される必要もない。
Further, in the above embodiment, the transfer portion is the n+ type impurity region 5.
It has an embedded transfer channel structure consisting of
An m structure without the n+ type impurity region 5 may be used. The depth of the junction of the channel stopper 7 made of the p+ type impurity region is
There is no need to be limited to the depth shown in FIGS. 1-2, or alternatively there may be no channel stopper 7 itself. Further, the substrate voltage applied to the semiconductor substrate 1 does not need to be limited to 15V as in the above embodiment.

また上記実施例において、転送電極および光遮蔽膜はそ
れぞれポリシリ■]ンおよびAl−8iからなっている
が、これど異なる伯の素材を用いてもよい。
Further, in the above embodiment, the transfer electrode and the light shielding film are made of polysilicon and Al-8i, respectively, but they may be made of different materials.

また」−記実施例は信号電荷として電子を用いる固体撮
像装置であるが、この装置を構成する全ての領域のn型
導電型とn型導電型とを入れかえて、正孔を信号電荷と
する固体搬像装置であってもよい。この場合、半導体基
8[1や転送電極9等に印加される電圧の正負tよ逆に
される。
In addition, although the embodiment described above is a solid-state imaging device that uses electrons as signal charges, the n-type conductivity type and the n-type conductivity type of all the regions constituting this device are switched, and holes are used as signal charges. It may also be a solid-state image carrier. In this case, the polarity t of the voltage applied to the semiconductor substrate 8[1, the transfer electrode 9, etc.] is reversed.

〔発明の効果〕〔Effect of the invention〕

以上の通り、本発明によれば、感光部から転送部への信
号電荷の転送において、信号電荷の残留がなくなり、残
像が生じないようにすることができる。
As described above, according to the present invention, no signal charges remain in the transfer of signal charges from the photosensitive section to the transfer section, and it is possible to prevent afterimages from occurring.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による固体撮像装置を示す断
面図、第2図は本発明の他の実施例による固体撮像装置
を示す断面図、第3図は本発明の一実施例による固体撮
像装置の特性を示すポテンシャル分布図、第4図は従来
の固体撮像装置を示す断面図、第5図ないし第7図は従
来の固体撮像装置の特性を示すポテンシャル分布図であ
る。 1・・・半導体基板、2,22・・・p型ウェル領域、
3.5.6.23.25.26・・・n+型不純物領域
、4.14.24・・・p+型不純物領域、7・・・チ
ャンネル・ストッパ、8・・・絶縁膜、9・・・転送電
極。 第3図 Poterttル酩 P1叫QIOd 〉 [F]     9!!2 PotentwL
FIG. 1 is a sectional view showing a solid-state imaging device according to an embodiment of the present invention, FIG. 2 is a sectional view showing a solid-state imaging device according to another embodiment of the invention, and FIG. 3 is a sectional view showing a solid-state imaging device according to another embodiment of the invention. 4 is a sectional view showing a conventional solid-state imaging device, and FIGS. 5 to 7 are potential distribution diagrams showing characteristics of a conventional solid-state imaging device. 1... Semiconductor substrate, 2, 22... P-type well region,
3.5.6.23.25.26...n+ type impurity region, 4.14.24...p+ type impurity region, 7...channel stopper, 8...insulating film, 9...・Transfer electrode. Fig. 3 P1 shout QIOd 〉 [F] 9! ! 2 PotentwL

Claims (1)

【特許請求の範囲】 半導体基板と、 この半導体基板表面に形成された第1導電型ウェル領域
と、この第1導電型ウェル領域表面に第2導電型不純物
を添加して形成され、入射光により生成される信号電荷
を蓄積する感光部と、前記第1導電型ウェル領域表面に
第2導電型不純物を添加して形成され、信号電荷を転送
する転送部と、この転送部と前記感光部との間に設けら
れ、前記感光部に蓄積された信号電荷を前記転送部に読
み出す読み出し部とを備えた固体撮像装置において、前
記感光部の中央部下方および端部下方のそれぞれにおけ
る前記第1導電型ウェル領域の接合の深さがほぼ同一で
あり、前記感光部の接合の深さが前記転送部の接合の深
さより深いことを特徴とする固体撮像装置。
[Claims] A semiconductor substrate, a first conductivity type well region formed on the surface of the semiconductor substrate, and a second conductivity type well region formed by adding a second conductivity type impurity to the surface of the first conductivity type well region, a photosensitive section that accumulates generated signal charges; a transfer section that is formed by adding a second conductivity type impurity to the surface of the first conductivity type well region and transfers the signal charges; and the transfer section and the photosensitive section. In the solid-state imaging device, the solid-state imaging device includes a readout section that is provided between the photosensitive section and reads out the signal charges accumulated in the photosensitive section to the transfer section, wherein the first conductive conductor is located below the center and below the end of the photosensitive section. A solid-state imaging device characterized in that the junction depths of the mold well regions are substantially the same, and the junction depth of the photosensitive section is deeper than the junction depth of the transfer section.
JP60287338A 1985-12-20 1985-12-20 Solid-state imaging device Expired - Lifetime JPH06105782B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60287338A JPH06105782B2 (en) 1985-12-20 1985-12-20 Solid-state imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60287338A JPH06105782B2 (en) 1985-12-20 1985-12-20 Solid-state imaging device

Publications (2)

Publication Number Publication Date
JPS62145865A true JPS62145865A (en) 1987-06-29
JPH06105782B2 JPH06105782B2 (en) 1994-12-21

Family

ID=17716075

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60287338A Expired - Lifetime JPH06105782B2 (en) 1985-12-20 1985-12-20 Solid-state imaging device

Country Status (1)

Country Link
JP (1) JPH06105782B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7388611B2 (en) 2003-12-02 2008-06-17 Matsushita Electric Industrial Co., Ltd. Solid-state image-taking apparatus, solid-state image-taking system, and apparatus and method for driving the solid-state image-taking apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5762557A (en) * 1980-10-02 1982-04-15 Nec Corp Solid state image pickup device and driving method therefor
JPS57173274A (en) * 1981-04-17 1982-10-25 Nec Corp Solid-state image pickup device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5762557A (en) * 1980-10-02 1982-04-15 Nec Corp Solid state image pickup device and driving method therefor
JPS57173274A (en) * 1981-04-17 1982-10-25 Nec Corp Solid-state image pickup device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7388611B2 (en) 2003-12-02 2008-06-17 Matsushita Electric Industrial Co., Ltd. Solid-state image-taking apparatus, solid-state image-taking system, and apparatus and method for driving the solid-state image-taking apparatus

Also Published As

Publication number Publication date
JPH06105782B2 (en) 1994-12-21

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