JPS62143507A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To secure the stability of a semiconductor integrated circuit at the time of negative feedback, by providing a serial circuit of a capacity and resistance in parallel with an earthing point at the signal point between the next- stage amplifier having a high-output resistance and an output buffer having a high-input impedance. CONSTITUTION:A serial circuit of a capacity 4 for phase compensation and resistance 5 for phase compensation is connected in parallel between the signal point 9 between the next stage amplifier 2 and output buffer 3 and earthing point 10. From the pole of a transfer function which is determined by the time constant between the capacity and resistance shunted from the high-output resistance of the amplifier 12, a gain damping characteristic of -6dB/Oct and phase delaying characteristic are obtained. In addition, a phase advancing characteristic is obtained at the zero point on the left-half plane of the transfer function determined by the time constant between the shunted capacity and resistance and the phase delaying quantity in the vicinity of a unit gain frequency is extremely improved. Therefore, high stability can be maintained even when the negative feedback quantity to be added to an operational amplifier is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit of an operational amplifier for high frequency analog signal processing.

Conventional technology In recent years, in addition to conventional video signals, analog signal processing has rapidly expanded the frequency band that can be handled due to the development of optical fiber communication systems, and it is desirable to realize operational amplifiers that can handle such high frequencies. ing. Generally, operational amplifiers have a built-in phase compensation circuit to prevent the amplifier from oscillating even if negative feedback is applied until the gain reaches unity. In the high frequency operational amplifier 2t\-/', the stability during negative feedback is determined by this phase compensation circuit, so its design is very important.

An example of the phase compensation circuit of the conventional semiconductor integrated circuit described above will be explained. Conventionally, in operational amplifier integrated circuits using silicon bipolar transistors, a phase compensation capacitor is inserted between the pace and collector in the common emitter circuit of the second amplification stage, and the Miller effect is used to lower the high-frequency gain.
Improved phase characteristics. ! f, silicon MO8FE
In the operational amplifier using T, a series circuit of a phase compensation capacitor and a buffer amplifier is inserted between the gate and drain in the common source circuit of the second amplification stage to perform phase compensation. The buffer amplifier is used to suppress the effect of yield forward, which occurs because the qm of a MOSFET is much smaller than that of a bipolar transistor.

Problems to be Solved by the Invention However, in the configuration of the phase compensation circuit as described above, the G
Good phase compensation cannot be achieved for operational amplifiers designed to operate at high frequencies using high-speed basic devices such as aAs (gallium arsenide) FETs. This is because as the frequency increases, in addition to the phase change in the first-stage amplifier, which has a large gain, the phase change in the next-stage amplifier itself, which uses the Miller effect, also increases, making it impossible to perform phase compensation correctly. .

1. In the buffer near-phase compensation circuit described above, a zero point on the left half plane occurs in the inverse transfer function due to the output resistance of the buffer in the high frequency region. As a result, sufficient gain attenuation characteristics cannot be obtained in the high frequency range, and reliable phase compensation cannot be achieved. As a result,
High frequency operational amplifiers have had a major problem in that they oscillate when the amount of negative feedback is increased.

In view of the above problems, the present invention provides a phase compensation circuit that guarantees stability during negative feedback of a high frequency operational amplifier.

Means for Solving the Problems In order to solve the above problems, the semiconductor integrated circuit of the present invention includes a second amplification stage having a high output resistance in an operational amplifier;
A series circuit consisting of a capacitor and a resistor is inserted between the signal point and the ground between the output cover which has high input impedance, and phase compensation is applied to the overall gain of the first-stage amplifier and the second-stage amplifier. It is.

Operation of the present invention: With the configuration described above, the entire gain through the first-stage amplifier and the next-stage amplifier is shunted by a series circuit of capacitors and resistors. Gain attenuation characteristics and phase lag characteristics of -6 dB10 at can be obtained with the ball of the transfer function, which is determined by the time constant of .

Furthermore, a phase progression characteristic is obtained at the zero point on the left half plane of the transfer function determined by the time constant of the shunt capacitance and resistance, and the amount of phase delay near the unit gain frequency is significantly improved. As a result, high stability can be maintained even if the amount of negative feedback applied to the operational amplifier is increased.

Embodiment Hereinafter, a semiconductor integrated circuit according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a circuit diagram of an operational amplifier with phase compensation in an embodiment of the present invention on page 6. In Figure 1, 1 is the first stage amplifier, 2
is a next-stage booster with high output resistance, 3 is an output sofa with high input impedance, 4 is a phase compensation capacitor, and 5 is a capacitor for phase compensation.
is a phase compensation resistor.

6 and 7 are positive phase and negative phase input terminals, respectively, and 8 is an output terminal. Series circuit of phase compensation capacitor 4 and phase compensation resistor 5 #
5 is a signal point 9 between the next stage amplifier 2 and the output buffer 73
and the ground point 1o. The characteristics of the semiconductor integrated circuit configured as above are shown below using FIGS. 1 and 2, and the broken line shows the characteristics when there is no shunt circuit N for phase compensation. In the broken line, due to the balls of the three transfer functions generated by the first stage amplifier 1 and the second stage amplifier 2, the phase delay at the unit gain frequency is -180
If the temperature exceeds 100° and negative feedback is applied, it will oscillate.

Assuming that the value of the capacitance 46 of the shunt circuit added for phase compensation is C, the value of the resistor 6 is R1, and the output resistance of the next stage amplifier 2 is R8, the transfer function of the operational amplifier is as follows. Here, A1(S), A2(S), and A3(S) are transfer functions of the first stage amplifier, the next stage amplifier, and the output Banoff 7, respectively. The output bacher has a gain of almost 1 up to the high frequency range, and the phase change is also very small. As a result, the frequency characteristics of gain and phase for the transfer function expressed by equation (1) are illustrated as shown by the solid line in FIG. 2.

In FIG. 2, the first ball frequency fP1 is the ball of equation (1), and the second ball frequency fP2 is generated from the transfer function A1(S) of the first stage multiplier 1. Furthermore, the frequency f of the zero point. becomes (1) from 2, and this f. In the second case, there is a phase advance, which cancels out the phase delay caused by the 37th Be/' pole. Therefore, in the higher range than near fo, the change in phase becomes small as shown by the solid line in FIG. Since the phase delay at unity gain does not exceed -180', the operational amplifier will not oscillate even if the negative feedback is increased. If the output resistance of the next-stage amplifier 2 is increased to 6 to 50 Ω, the value of the capacitance 4 of the phase compensation circuit will be about 1 to 10 pF, and the value of the resistor 6 will be about 20 to 200 Ω, making the phase compensation circuit monolithic. is easy. The larger the output resistance of the next-stage amplifier 2, the smaller the size of the capacitor 4, which is advantageous for monolithic implementation. In addition, if the output vanofer 3 after the phase compensation circuit is selected to have high input impedance and a wide band gain frequency characteristic, the transfer function of the operational amplifier will be the transfer function A1 of the first and next stage amplifiers.
(S), A2(S), and the values of the capacitance and resistance of the phase compensation circuit. Therefore, designing phase compensation becomes very easy.

As described above, according to this embodiment, a series circuit of a capacitor and a resistor is inserted in parallel to the ground point at the signal point between the next-stage amplifier having a high output resistance and the output vanifer having a high input impedance. As a result, sufficient gain attenuation characteristics and phase delay improvement can be obtained, and an operational amplifier that does not oscillate even when negative feedback is applied can be realized.

In addition, for the next stage amplifier 2 having a high output resistance, for example, a differential amplifier using two dual gate type FETs can be used.
Further, a source follower circuit can be used for the output vanofer 3 having a high input impedance.

Effects of the Invention As described above, the present invention provides a next-stage amplifier having a high output resistance in an operational amplifier, an output cover having a high input impedance,
By inserting a series circuit of a capacitor and a resistor in parallel with the ground point at the signal point between 7A and 7A, it is possible to sufficiently attenuate the gain and reduce the amount of phase delay in the high frequency range. Therefore, according to the present invention, it is possible to ensure stability during negative feedback of a high frequency operational amplifier using a high speed device such as a G a A 5FET.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a 9-page path of a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a characteristic diagram showing frequency characteristics of gain and phase of the semiconductor integrated circuit according to an embodiment of the present invention. 1...First stage amplifier, 2-...Next stage amplifier, 3...
... Output vanofer, 4 ... Phase compensation capacitor,
5...Resistance for phase compensation. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
--Sugar I width winding 7--Reverse phase input sieve hand 8-- and basket parking 9--Signal point Iθ-Grounding point

Claims (1)

[Claims] between the signal point between the amplifier with high output resistance and the buffer amplifier with high input impedance and the ground point.
A semiconductor integrated circuit characterized by inserting a series circuit of capacitance and resistance.