JPH0380706A - Operational amplifier - Google Patents

Operational amplifier

Info

Publication number
JPH0380706A
JPH0380706A JP21895989A JP21895989A JPH0380706A JP H0380706 A JPH0380706 A JP H0380706A JP 21895989 A JP21895989 A JP 21895989A JP 21895989 A JP21895989 A JP 21895989A JP H0380706 A JPH0380706 A JP H0380706A
Authority
JP
Japan
Prior art keywords
circuit
output
input
source follower
phase compensation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21895989A
Other languages
Japanese (ja)
Inventor
Tomoaki Masuda
増田 智章
Yutaka Takahashi
豊 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21895989A priority Critical patent/JPH0380706A/en
Publication of JPH0380706A publication Critical patent/JPH0380706A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To obtain a stable phase compensation characteristic which is not influenced by a load on an output side and an input/output frequency, etc., by connecting a phase compensating circuit to which a prescribed source follower circuit and a capacity are connected in series, between an input and an output of a gain circuit. CONSTITUTION:The operational amplifier is constituted by providing a differential amplifying circuit 1, a gain circuit 2, an output circuit 3, a source follower circuit 7 containing an NMOS transistor 5 and a resistance 6, and a phase compensating circuit 8 containing a capacity 4 and the source follower circuit 7. Since the source follower circuit exists in the phase compensating circuit for forming a feedback circuit, a stable phase compensation characteristic which is not influenced by a load on an output side and an input/output frequency, etc., is realized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は演算増幅器に関し、特にMO3型半導体集積回
路に適合する位相補償回路を備える演算増幅器に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an operational amplifier, and more particularly to an operational amplifier equipped with a phase compensation circuit suitable for an MO3 type semiconductor integrated circuit.

〔従来の技術〕[Conventional technology]

従来の演算増幅器は、第3図に一例が示されるように、
差動増幅回路17の出力側に接続される出力回路18と
、出力回路18の入出力間に接続される容量19および
抵抗20の直列接続回路から戒る位相補償回路21と、
を備えて構成されている。
A conventional operational amplifier, as shown in FIG.
an output circuit 18 connected to the output side of the differential amplifier circuit 17; a phase compensation circuit 21 connected between the input and output of the output circuit 18 from a series connection circuit of a capacitor 19 and a resistor 20;
It is configured with.

第3図において、信号入力端子59および60から入力
される信号は、差動増幅回路17の正相および逆相の入
力端子に入力され、入出力間に容量19および抵抗20
からなる位相補償回路21が接続される利得回路18を
経由して位相補償され、信号出力端子61から出力され
る。
In FIG. 3, signals inputted from signal input terminals 59 and 60 are inputted to positive-phase and negative-phase input terminals of a differential amplifier circuit 17, and a capacitor 19 and a resistor 20 are connected between the input and output terminals.
The signal is phase compensated via the gain circuit 18 to which the phase compensation circuit 21 consisting of the following is connected, and is output from the signal output terminal 61.

今、第3図における差動増幅回路17の相互コンダクタ
ンスをg、1.出力抵抗をR1、出力端子61にかかわ
る負荷容量をCLとし、更に、位相補償回路21に含ま
れる抵抗20の抵抗値をR1、容量19の容量値をCF
とすると、第4図のような等価回路が得られ、上記の抵
抗値Rfおよび容量値C,を適当に選定することにより
、位相補償された入出力信号特性が得られる。
Now, the mutual conductance of the differential amplifier circuit 17 in FIG. 3 is expressed as g, 1. The output resistance is R1, the load capacitance related to the output terminal 61 is CL, the resistance value of the resistor 20 included in the phase compensation circuit 21 is R1, and the capacitance value of the capacitor 19 is CF.
Then, an equivalent circuit as shown in FIG. 4 is obtained, and by appropriately selecting the above-mentioned resistance value Rf and capacitance value C, phase-compensated input/output signal characteristics can be obtained.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の演算増幅器においては、出力端子から直
接に位相補償回路を介して出力回路の入力側に帰還をか
けているために、位相補償機能が負荷の影響を受けると
いう欠点とともに、帰還回路が抵抗と容量とによって構
成されているため、入力信号の周波数が高くなるとフィ
ードフォーワードになり、余分の零点が生じて十分な位
相補償が為されないという欠点がある。
In the conventional operational amplifier described above, since feedback is applied directly from the output terminal to the input side of the output circuit via the phase compensation circuit, the phase compensation function is affected by the load, and the feedback circuit is Since it is composed of a resistor and a capacitor, it has the disadvantage that when the frequency of the input signal becomes high, it becomes a feed forward, and an extra zero point is generated, making it impossible to perform sufficient phase compensation.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の演算増幅器は、第1および第2の信号入力に対
応する差動増幅回路に対して、それぞれ順次に縦続接続
される利得回路および出力回路を備え、前記利得回路の
入出力間に接続される帰還回路として、所定の容量とソ
ースフォロア回路とを含む位相補償回路を備えて構成さ
れる。
The operational amplifier of the present invention includes a gain circuit and an output circuit that are sequentially connected in cascade to differential amplifier circuits corresponding to first and second signal inputs, and that are connected between the input and output of the gain circuit. The feedback circuit is configured to include a phase compensation circuit including a predetermined capacitance and a source follower circuit.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。第1図
(&)および(b)は、それぞれ本発明の第1および第
2の実施例を示す回路図、第2図は、前記第1および第
2の実施例の等価回路図である。
Next, the present invention will be explained with reference to the drawings. FIGS. 1(&) and (b) are circuit diagrams showing the first and second embodiments of the present invention, respectively, and FIG. 2 is an equivalent circuit diagram of the first and second embodiments.

第1図(a)に示されるように、第1の実施例は、差動
増幅回路1と、利得回路2と、出力回路3と、NMO3
)−ラジスタ5および抵抗6を含むソースフォロア回路
7と、容量4およびソースフォロア回路7を含む位相補
償回路8と、を備えて構成される。
As shown in FIG. 1(a), the first embodiment includes a differential amplifier circuit 1, a gain circuit 2, an output circuit 3, and an NMO3.
) - a source follower circuit 7 including a radiator 5 and a resistor 6; and a phase compensation circuit 8 including a capacitor 4 and the source follower circuit 7.

第1図(a)において、信号入力端子51および52か
ら入力される信号は、差動増幅回路1の正相および逆相
の入力端子に入力され、入出力間に容量4およびソース
フォロア回路7を含む位相補償回路8が接続されている
利得回路2を経由して、出力回路3を介して信号出力端
子54から出力される。
In FIG. 1(a), signals inputted from signal input terminals 51 and 52 are inputted to the positive phase and negative phase input terminals of the differential amplifier circuit 1, and a capacitor 4 and a source follower circuit 7 are connected between the input and output. The signal is outputted from the signal output terminal 54 via the output circuit 3 via the gain circuit 2 to which the phase compensation circuit 8 including the phase compensation circuit 8 is connected.

前記従来例の場合と同様に、差動増幅回路1の相互コン
ダクタンスをg、1、出力抵抗をR5、出力側の寄生容
量をC!とし、更に、位相補償回路8におけるソースフ
ォロア回路7の相互コンダクタンスをg、。、出力抵抗
をR8として、容量4の容量値をCeとすると、第2図
に示されるような等価回路が得られる。この等価回路は
、第4図に示されている従来例の等価回路における抵抗
20の抵抗値R1を、ソースフォロア回路7の相互コン
ダクタンスg0および出力抵抗R8によって置換した形
となっている。従って、本演算増幅器の入出力特性とし
ては、所定の位相補償された特性が得られることは明ら
かである。しかも、本発明特有の作用として、帰還回路
を形成する位相補償回路にソースフォロア回路が介在し
ているため、出力側の負荷ならびに入出力周波数等に影
響されない安定した位相補償特性が実現される。
As in the case of the conventional example, the mutual conductance of the differential amplifier circuit 1 is g, 1, the output resistance is R5, and the parasitic capacitance on the output side is C! Furthermore, the mutual conductance of the source follower circuit 7 in the phase compensation circuit 8 is g. , when the output resistance is R8 and the capacitance value of the capacitor 4 is Ce, an equivalent circuit as shown in FIG. 2 is obtained. This equivalent circuit has a form in which the resistance value R1 of the resistor 20 in the conventional equivalent circuit shown in FIG. 4 is replaced by the mutual conductance g0 of the source follower circuit 7 and the output resistance R8. Therefore, it is clear that a predetermined phase compensated characteristic can be obtained as the input/output characteristics of the present operational amplifier. Furthermore, as a unique feature of the present invention, since a source follower circuit is interposed in the phase compensation circuit forming the feedback circuit, stable phase compensation characteristics that are not affected by the load on the output side, the input/output frequency, etc. can be realized.

次に、本発明の第2の実施例について説明する。第1図
(b)に示されるように、本実施例は、差動増幅回路9
と、利得回路10と、出力回路11と、PMO3)ラン
ジスタ13および抵抗14を含むソースフォロア回路1
5と、容量12と、容量12およびソース7オロア回路
15を含む位相補償回路16と、を備えて構成される。
Next, a second embodiment of the present invention will be described. As shown in FIG. 1(b), in this embodiment, the differential amplifier circuit 9
, a gain circuit 10 , an output circuit 11 , a PMO 3) a source follower circuit 1 including a transistor 13 and a resistor 14
5, a capacitor 12, and a phase compensation circuit 16 including the capacitor 12 and a source 7-oror circuit 15.

本実施例は、第1図(a)に示される第1の実施例にお
いて、NMOSトランジスタ5を用いて構成されていた
ソースフォロア回路7を、PMOSトランジスタ13を
用いてソース7オロア回路15として構成した例であり
、その等価回路は、第2図に示されるように、第1の実
施例の場合と同様である。従って、第1の実施例の場合
と同様に、演算増幅器の入出力特性としては、出力側の
負荷ならびに入出力周波数等に影響されない安定した位
相補償特性が実現される。
In this embodiment, the source follower circuit 7 configured using the NMOS transistor 5 in the first embodiment shown in FIG. This is an example in which the equivalent circuit is the same as that in the first embodiment, as shown in FIG. Therefore, as in the case of the first embodiment, stable phase compensation characteristics that are not affected by the load on the output side, the input/output frequency, etc. are realized as the input/output characteristics of the operational amplifier.

〔発明の効果〕〔Effect of the invention〕

以上、詳細に説明したように、本発明は、差動増幅回路
、利得回路および出力回路を含む演算増幅器において、
所定のソースフォロア回路と容量とを直列接続した位相
補償回路を、前記利得回路の入出力間に接続することに
より、出力側の負荷ならびに入出力周波数等に影響され
ない安定した位相補償特性が得られるという効果がある
As described above in detail, the present invention provides an operational amplifier including a differential amplifier circuit, a gain circuit, and an output circuit.
By connecting a phase compensation circuit in which a predetermined source follower circuit and a capacitor are connected in series between the input and output of the gain circuit, stable phase compensation characteristics that are not affected by the load on the output side and the input/output frequency can be obtained. There is an effect.

【図面の簡単な説明】 第1図(a)および(b)は、それぞれ本発明の第1お
よび第2の実施例の回路図、第2図は前記第工および第
2の実施例の等価回路図、第3図は、従来例の回路図、
第4図は前記従来例の等価回路図である。 図において、1.9.17・・・・・・差動増幅回路、
2、lO・・・・・・利得回路、3.11.18・・・
・・・出力回路、4、12.19・・・・・・容量、5
・・・・・・NMOSトランジスタ、6,14.20・
・・・・−抵抗、7,15・・・・・・ソースフォロア
回路、8.16.21・・・・・・位相補償回路。
[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1(a) and (b) are circuit diagrams of the first and second embodiments of the present invention, respectively, and FIG. 2 is an equivalent circuit diagram of the first and second embodiments of the present invention. Circuit diagram, Figure 3 is a circuit diagram of a conventional example,
FIG. 4 is an equivalent circuit diagram of the conventional example. In the figure, 1.9.17...differential amplifier circuit,
2, lO...gain circuit, 3.11.18...
...Output circuit, 4, 12.19... Capacity, 5
・・・・・・NMOS transistor, 6,14.20・
......-Resistor, 7,15... Source follower circuit, 8.16.21... Phase compensation circuit.

Claims (1)

【特許請求の範囲】[Claims] 第1および第2の信号入力に対応する差動増幅回路に対
して、それぞれ順次に縦続接続される利得回路および出
力回路を備え、前記利得回路の入出力間に接続される帰
還回路として、所定の容量とソースフォロア回路とを含
む位相補償回路を備えることを特徴とする演算増幅器。
A gain circuit and an output circuit are sequentially connected to the differential amplifier circuit corresponding to the first and second signal inputs, and a predetermined feedback circuit is connected between the input and output of the gain circuit. An operational amplifier comprising a phase compensation circuit including a capacitance of 1 and a source follower circuit.
JP21895989A 1989-08-24 1989-08-24 Operational amplifier Pending JPH0380706A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21895989A JPH0380706A (en) 1989-08-24 1989-08-24 Operational amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21895989A JPH0380706A (en) 1989-08-24 1989-08-24 Operational amplifier

Publications (1)

Publication Number Publication Date
JPH0380706A true JPH0380706A (en) 1991-04-05

Family

ID=16728029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21895989A Pending JPH0380706A (en) 1989-08-24 1989-08-24 Operational amplifier

Country Status (1)

Country Link
JP (1) JPH0380706A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023195A (en) * 1997-09-01 2000-02-08 Nec Corporation On-chip source follower amplifier
US6316998B1 (en) 1997-11-12 2001-11-13 Nec Corporation Differential amplifier and a method of compensation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60239109A (en) * 1984-05-14 1985-11-28 Nec Corp Operational amplifier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60239109A (en) * 1984-05-14 1985-11-28 Nec Corp Operational amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6023195A (en) * 1997-09-01 2000-02-08 Nec Corporation On-chip source follower amplifier
US6316998B1 (en) 1997-11-12 2001-11-13 Nec Corporation Differential amplifier and a method of compensation

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