JPS62139478A - Horizontal phase locked loop circuit for composite synchronizing signal - Google Patents

Abstract

PURPOSE:To prevent a VCO from unnecessary variation of output frequency by sample-holding the output of a phase comparator at the leading edge or trailing edge of a vertically synchronizing pulse of a composite synchronizing signal and inputting the sample-holding value to the VCO as a control signal. CONSTITUTION:A vertical synchronization separating circuit 7 separates a vertically synchronizing signal from a composite cynchronizing signal inputted from an input terminal 1 and sends the separated signal to a synchronizing width extending circuit 8. The circuit 8 extends the pulse width of the vertically synchronizing signal and sends the extended signal to a sample holding circuit 4. The circuit 4 samples the output of an amplifier 3 at the trailing edge of the extended synchronizing pulse, holds the sampled voltage up to the leading edge of the pulse and outputs the held voltage to the VCO 5. When there is no extended synchronizing pulse, the signal inputted from the amplifier 3 is outputted to the VCO 5 as it is. Consequently, the VCO can be prevented from the influence of the output variation of a phase comparator 2 upon its output frequency.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention relates to horizontal phase synchronization of a composite synchronization signal of an address generator that accesses a memory having an address corresponding to a scanning line, such as an image memory of a rask scan type display. Regarding circuits.

[Conventional technology]

Recently, with the rapid progress of LSI technology and image signal processing technology, there has been an increasing demand for image memories with even higher bulk quality.

When recording images, when displaying video signals sent from the shooting side by scanning with an electron beam, it is impossible to assemble the image on the receiving side unless you know where the horizontal scanning starts and where the vertical scanning starts, and the timing. Can not. Therefore, it is common practice to insert a narrow pulse as a synchronization signal between video signals to match the timing of horizontal scanning and vertical scanning. If the waveform of this synchronization signal is inaccurate or the phase interval varies, distortion will occur in the image reproduced on the screen. Therefore, the phase interval is fixed by the PLL circuit.

FIG. 3 is a block diagram of a conventional example of a horizontal phase synchronization circuit for a composite synchronization signal, and FIG. 4 is an example of a waveform diagram of a composite synchronization signal.

The block diagram shown in FIG. 8 is a normal PLL circuit. The phase comparator 2 compares the composite synchronization signal input via the input terminal l with the output of the 2nVCO5 fed back via the (1/2 n) counter 6, and the output is sent to the 2nVCO5 via the amplifier 3. is input. FIG. 4 is a waveform diagram of the composite synchronization signal. The horizontal synchronization signal for matching the timing of horizontal scanning and the vertical synchronization signal for matching the timing of field scanning have the same amplitude but different pulse widths, making it easy to separate the horizontal and vertical synchronization signals. ing.

[Problems to be Solved by the Invention] The above-mentioned conventional horizontal phase synchronization circuit inputs a composite synchronization signal in which a horizontal synchronization pulse is included in a vertical synchronization pulse, as shown in FIG. Then, while the vertical synchronization signal is being input, phase lock is no longer possible and the oscillation frequency is significantly shifted, and after the vertical synchronization ends, synchronization pull-in is performed again and the phase is locked. Although the oscillation frequency shift at this time depends on the loop gain of the PLL circuit, the image memory is affected by the time until this synchronization pull-in is performed again.

If the loop gain of the PLL circuit is lowered, the deviation in oscillation frequency can be reduced, but in the case of a multi-scan display in which the horizontal scanning frequency changes, for example, it takes time to acquire synchronization. Therefore, disturbances in horizontal synchronization during input of vertical synchronization signals cannot be avoided by lowering the loop gain of the PLL circuit.

[Means for solving problems]

The horizontal phase synchronization circuit for composite synchronization signals of the present invention includes a vertical synchronization separation circuit that inputs a composite synchronization signal and separates a vertical synchronization signal from the composite synchronization signal, and a vertical synchronization signal output from the vertical synchronization separation circuit. A synchronization width extension circuit that extends the pulse width of the vertical synchronization pulse and an amplifier that amplifies the output of the phase comparator circuit of the PLL circuit are input. The output of the amplifier is sampled at the time of rising, and the sampled voltage is held and output to the VCO until the extended synchronization pulse rises or falls.When the extended synchronization pulse is not present, the signal input from the amplifier is output to the VCO. It is characterized by having a sample and hold circuit.

In this way, the sample and hold circuit samples the phase comparator output at the falling or rising edge of the vertical synchronization pulse,
By holding the output of the phase comparator that has changed due to the input of the vertical synchronization signal until it recovers to the voltage value immediately before sampling, and outputting the held voltage as the control voltage of the VCO, the vertical synchronization signal can be changed. It is possible to prevent fluctuations in the output frequency of the VCO due to fluctuations in the output of the phase comparator caused by the input of , and to prevent disturbances in horizontal synchronization.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a horizontal phase synchronization circuit for composite synchronization signals according to the present invention.

This embodiment is a vertical synchronization separation circuit in addition to the conventional horizontal phase synchronization circuit for composite synchronization signals shown in FIG. , synchronous width expansion circuit 8. A sample and hold circuit 4 is added.

The vertical synchronization separation circuit 7 separates the vertical synchronization signal from the composite synchronization signal input via the input terminal 1.

The synchronization width extension circuit 8 extends the pulse width of the vertical synchronization signal output from the vertical synchronization separation circuit 7. The sample hold circuit 4 inputs the output of the phase comparator 2 via the amplifier 3,
The output of the amplifier 8 is sampled at the falling edge of the extended synchronization pulse output by the synchronization width expansion circuit 7, and the sampled voltage is held until the extended synchronization pulse rises, and the voltage is converted to VC.
When there is no expansion synchronization pulse, the signal input from the amplifier 3 is output as is to \CO.

Next, the operation of this embodiment will be explained with reference to FIG.

FIG. 2 is a waveform diagram showing the operation of this embodiment.

FIG. 2 fal is a diagram showing a composite synchronization signal waveform at point A in FIG. 1. Since the synchronization signal is input in the negative direction to the blanking portion of the video signal, it is shown as a downward pulse in the figure, which is exactly the same as in FIG. 3. The composite synchronization signal input from the input terminal 1 is input to the phase comparator 2 and also to the vertical synchronization separation circuit 7, where the narrow pulse width horizontal synchronization signal is removed and the vertical synchronization signal output from the vertical synchronization separation circuit 7. The pulse width of the signal is expanded by a synchronization width expansion circuit 8. Figure 2 (bl is a diagram showing the expanded synchronization signal waveform at point B in Figure 1, falling at time t1 and rising at time t2. Sample and hold circuit 4 samples the output voltage of amplifier 3 at time t□. and holds it until time t2, and outputs it to vCo5. Therefore, from time t to time t2, the output frequency of vCo5 is
It is controlled by the output voltage of the amplifier 3 at time t□, and is not affected by changes in the output of the amplifier 3 between time t□ and time t2. After time t2, until time t3 when the expansion synchronization signal next falls, the sample and hold circuit inputs the output of the amplifier 3 and outputs it to the VCO 5 as it is. Therefore, the output frequency of vCo5 is controlled by the output of the -phase comparator 2 during the period from time t2 to t3.

Fig. 2 (cl is a diagram showing the voltage waveform at point C in Fig. 1. The output of the amplifier 3 is from the input terminal 1 to the horizontal synchronous The signal decreases because it is not input to phase comparator 2, and the time t when the horizontal synchronization signal is input to phase comparator 2 from input terminal 1.
4 and onward, and at time t2, it recovers to the voltage value at time t1. The reason why the vertical synchronization signal is extended to time t2 by the synchronization width extension circuit 8 is to control vCo5 with the sample and hold voltage from time t□ to t2, when the output of the phase comparator 2 changes. Figure 2 (dl is the first
It is a figure which shows the VC05 input terminal waveform at the D point of a figure. It is shown that the vertical synchronization signal remains constant even during input. In this way, fluctuations in the output frequency of vCo5 can be prevented, thereby locking the phase of the horizontal synchronization signal.

〔Effect of the invention〕

As explained above, the horizontal phase synchronization circuit for the composite synchronization signal of the present invention samples and holds the output of the phase comparator at the falling or rising edge of the vertical synchronization pulse of the composite synchronization signal, and inputs it to vCo as a control signal. By this, the output fluctuation of the phase comparator caused by the input of the vertical synchronization signal is reduced to vCo.
In addition, by being used in the address generation circuit of the video memory, disturbances in the addresses at the top of the screen are reduced, and distortion at the top of the image is eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the horizontal phase synchronization circuit for composite synchronization signals of the present invention, FIG. 2 (section) is a diagram showing the composite synchronization signal waveform at point A in FIG. A diagram showing the expanded synchronization signal waveform at point B in Figure 1, Figure 2(c)
is a diagram showing the phase comparator output waveform at point C in FIG. 1,
Figure 2 (dl is a diagram of the VCO input voltage waveform at point D in Figure 1, Figure 8 is a block diagram of a conventional example of a horizontal phase synchronization circuit for a composite synchronization signal, and Figure 4 is a diagram of a conventional example of a horizontal phase synchronization circuit for a composite synchronization signal. It is a waveform diagram. 1... Input terminal. 2... Phase comparator. 3... Amplifier. 4... Sample hold circuit. 5-2nVC0. 6... l/2n counter/re. 7 ... Vertical sync separation circuit. 8... Synchronization width expansion circuit.

Claims (1)

[Claims] A horizontal phase synchronization circuit for a composite synchronization signal including a PLL circuit for phase locking a horizontal synchronization signal, comprising a vertical synchronization separation circuit for inputting the composite synchronization signal and separating a vertical synchronization signal from the composite synchronization signal. , a synchronization width expansion circuit that inputs the vertical synchronization signal output from the vertical synchronization separation circuit and expands the pulse width of the vertical synchronization pulse, and inputs the output of an amplifier that amplifies the output of the phase comparator of the PLL circuit, The output of the amplifier is sampled at the falling or rising edge of the expanded synchronizing pulse output by the synchronizing width expanding circuit, and the sampled voltage is held and output to the VCO until the expanded synchronizing pulse rises or falls. . A horizontal phase synchronization circuit for a composite synchronization signal, comprising a sample and hold circuit that outputs a signal input from the amplifier to a VCO when the expanded synchronization pulse is not present.