JPH0514765A - Display device - Google Patents

Abstract

PURPOSE:To operate a stable clock operation by selectively generating a reference pulse and a pedestal clamp pulse which can be selectively adapted to a display, even when a video signal having a different horizontal synchronizing frequency is inputted. CONSTITUTION:A synchronizing timing detecting circuit 3 generates an inside synchronizing signal ISYNC having the necessitated minimum pulse width as a synchronizing signal. When the horizontal synchronizing frequency fH of an input video signal SIN is high, a rise timing is earlier than the synchronizing signal ISYNC, and the short pulse width is obtained. Therefore, the time of a back porch following the signal ISYNC is lengthened. As the result, the reference pulse generated by a monostable multivibrator 7 for shaping a waveform with an output pulse signal S3 as a reference timing, and the pedestal clamp pulse generated by a monostable multivibrator 8 with the reference pulse as the reference, are stored in a back porch timing. Thus, a stable clamp operation can be operated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a multi-scan display device capable of selecting and displaying one of a plurality of types of video signals.

[0002]

2. Description of the Related Art For example, in a display device for a computer, one of a plurality of types of analog video signals is used.
2. Description of the Related Art A multi-scan type display device is known in which a seed is selected and displayed on one type of display, for example, a CRT display.
One example of the waveform of such an analog input video signal is shown in FIG.
It shows in (A). This input video signal SIN is a synchronization signal SY.
The signal structure has a front porch FP in front of the NC, a back porch BP in the rear, and a video signal component, for example, a luminance signal component Y. In this type of display device, in order to display a plurality of video signals on one type of CRT display, the back porch BP after the synchronization signal SYNC has a height corresponding to the level for detecting the video signal level. It has a reference pulse REF and a pedestal clamp pulse CLAMP for pedestal clamp.

In the current multi-scan type display device, it is possible to display only two or three types of input video signals, even if it is a plurality of video signals.
As shown in (B) and (C), after detecting the synchronization signal SYNC, the reference pulse REF is generated at a fixed timing in common to these video signals, and then the pedestal clamp pulse CLAMP is also generated at a fixed timing. I am letting you.

[0004]

When the horizontal synchronization (deflection) frequency f _H becomes higher, the time of the back porch BP becomes shorter accordingly, but as described above, the reference pulse REF and the pedestal clamp pulse CLAMP are fixed in timing. , A high horizontal sync frequency f
_In the case of the _H video signal, as shown in FIG. 5C, the pedestal clamp pulse CLAMP does not fit in the timing area of the back porch BP and enters the area of the luminance signal component Y, so that the pedestal clamp cannot be performed. Come across. The problem is that the number of multi-scans increases and the range of the horizontal synchronization frequency f _H becomes, for example,
Oyobi the 31KH _Z ~70KH _Z, multiscan number 1
When the number of types is 0 or more, a large number of video signals having a high horizontal synchronizing frequency f _H will be present, which is particularly remarkable. As one method for solving such a problem, a method of shortening the width of the reference pulse REF and the width of the pedestal clamp pulse CLAMP can be considered, but if these pulse widths are shortened to a predetermined limit pulse width or less, the original purpose is reduced. Operation cannot be secured. Therefore, it is an object of the present invention to provide a display device capable of stably displaying a large number of video signals with a relatively simple circuit configuration.

[0005]

In order to solve the above problems, a video signal in which a back porch and a video signal component are input after a synchronization signal is input, and a video signal level detection reference pulse and a pedestal clamp In the display device of the present invention for generating a pedestal clamp pulse and outputting a video signal to a display device, a circuit for generating the reference pulse and the pedestal clamp pulse at the timing corresponding to the frequency of the input video signal within the timing of the back porch. Is provided. The circuit configuration is as follows: (1) The sync signal and the back porch of the input video signal are left unchanged, and the sync pulse and the pedestal clamp pulse are set within the back porch timing so that the sync pulse and A circuit configuration that changes the reference pulse generation timing and the pedestal clamp pulse generation timing. (2) When the frequency of the input video signal is high, the synchronization signal included in the input video signal is within the time required for the display. The internal sync signal for the display is switched so that it is shortened as much as possible, and the back porch is substantially lengthened by generating an internal sync signal for the display, which is substantially fixed within the extended back porch timing. To generate a reference pulse and a pedestal clamp pulse at the same timing (3) and a method of mixing circuit configuration and the circuit configuration of (2) above (1).

[0006]

In any of the above circuit configurations, the reference pulse and the pedestal clamp pulse are generated within the timing of the back porch at the timing corresponding to the frequency of the input video signal. More specifically, the above (1)
In the case of the circuit configuration of, the reference pulse and the pedestal clamp pulse are generated immediately after the sync signal in the originally short back porch in the case of the input video signal having the high horizontal sync frequency, while having the low horizontal sync frequency. In the case of the input video signal, the reference pulse and the pedestal clamp pulse are generated in the originally long back porch with a timing margin. In the case of the circuit configuration of the above (2), the synchronizing signal having the minimum pulse width necessary for the display is internally generated, and the rising timing of the internal synchronizing signal is earlier than the rising timing of the synchronizing signal of the input video signal. Then, the back porch time that follows is substantially extended. The reference pulse and the pedestal clamp pulse are contained within this extended back porch timing.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a signal processing circuit in a display device in the case of internally generating a synchronizing signal as one embodiment of a multi-scan display device of the present invention. Figure 1 (A)
Shows the entire configuration of the signal processing circuit, and FIG. 1B shows a detailed circuit of the synchronization timing detection circuit 3 of FIG. One input video signal SIN among the video signals having various horizontal synchronizing frequencies f _H is input to a signal processing circuit, and this signal processing circuit sends a horizontal synchronizing frequency f _H to a CRT display (not shown). The output video signal SOUT having the reference pulse and the pedestal clamp pulse whose generation timing is adjusted according to the above is output. In the first embodiment, the generation timing of the reference pulse and the pedestal clamp pulse is adjusted by changing the width of the internal synchronizing signal according to the horizontal synchronizing frequency f _H of the input video signal SIN.

The signal processing circuit shown in FIG. 1A has a sync separation circuit 1, a sync timing detection circuit 3, a waveform shaping mono multivibrator 5, a mono multivibrator 7 and a deflection system 20. Further, this signal processing circuit has an internal synchronizing signal generation circuit 10, an amplification circuit 12, a signal addition circuit 14, a signal addition circuit 16 and an amplification circuit 18, and the amplification circuits 12 to 18 form a negative feedback loop. is doing. Figure 2 shows the waveform of the input video signal SIN
(A) shows. This signal waveform itself is the same as the waveform of FIG. 5 (A), and the front porch FP, the horizontal synchronizing signal SYNC
(Or HD), a back porch BP, and a video signal component, for example, a luminance signal component Y.

Also in this signal processing circuit, as shown in FIG.
As shown in (B) and (C), a reference pulse REF having a height corresponding to the video signal level is generated in the waveform shaping mono multivibrator 5 and is superimposed on the signal from the amplifier circuit 12 in the signal addition circuit 14. And
Further, in the mono-multi vibrator 7, a pedestal clamp pulse CL having a height according to the pedestal level
AMP is generated and superposed on the signal S14 from the signal addition circuit 14 in the signal addition circuit 16. The reference pulse REF is generated a predetermined time t1 after the fall of the synchronizing signal SYNC, and the pedestal clamp pulse CLAMP is generated a predetermined time t2 after the rise of the reference pulse REF. The generation time t1 of the reference pulse REF is, as described later,
It is determined by the horizontal synchronizing frequency f _H of the input video signal SIN. The time t2 between the reference pulse REF and the pedestal clamp pulse CLAMP is constant in this embodiment, and the widths of the reference pulse REF and the pedestal clamp pulse CLAMP are also constant.

The sync separation circuit 1 detects the sync signal SYNC included in the input video signal SIN, separates the sync signal SYNC, and outputs the separated sync signal SYNC, in this example, the horizontal sync signal HD to the sync timing detection circuit 3. To do. Further, the signal S1B from which the component of the horizontal synchronizing signal HD is removed is applied to the deflection system 20, and the deflection system 20 deflects the CRT display as in the conventional case.

As shown in FIG. 1B, the synchronization timing detection circuit 3 includes a mono multivibrator 31 and a capacitance C.
_X of the capacitor 32, the resistance value R _X of the resistor 33 and 34,
It is composed of an integration comparison circuit 36 and resistors 36 and 37. The resistors 36 and 37 are the reference voltage V _ref H of the integrating comparator 36.
(See FIGS. 3 and 4). FIG. 3 shows a signal waveform in the synchronization timing detection circuit 3. 3A is an enlarged waveform of the horizontal synchronizing signal HD, and FIG. 3B is a resistor 33.
3C shows the differential signal waveform of the capacitor 32, and FIG. 3C shows the output pulse signal S3 of the synchronization timing detection circuit 3. The synchronization timing detection circuit 3 integrates the horizontal synchronization signal HD and uses this integrated voltage as the pull-up voltage of the resistor 33 that sets the time constant of the mono-multivibrator 31. Therefore, when the horizontal sync frequency f _H of the input video signal SIN is high, a large number of horizontal sync signals HD are input within a predetermined time, so that a high integrated voltage is obtained and the time constant of the mono-multivibrator 31 becomes short. Sync timing detection circuit 3
The pulse width of the output signal S3 becomes narrower. On the contrary, in the case of the input video signal SIN having a low horizontal synchronizing frequency f _H , the pulse width of the output pulse signal S3 becomes long.

Details of such operation will be described with reference to FIG. When the horizontal synchronizing frequency f _H is high, the high pull-up voltage shown by the broken line in FIG. 4 is obtained, and when the horizontal synchronizing frequency f _H is low, the low pull-up voltage shown by the solid line is obtained. When the pull-up voltage is high, the output pulse signal S having the pulse width of the short time τ1 is output from the synchronization timing detection circuit 3.
3 is output, and when the pull-up voltage is low, a long time τ
An output pulse signal S3 having a pulse width of 1 is output.

The output pulse signal S3 from the synchronization timing detection circuit 3 is applied to the internal synchronization signal generation circuit 10.
The internal sync signal generation circuit 10 corrects the rising timing of the sync signal SYNC included in the input video signal SIN according to the pulse width of the output pulse signal S3 from the sync timing detection circuit 3 so that the back porch BP interval becomes substantially equal. Internal sync signal ISYNC with a short pulse width that is relatively long
The sync signal SYNC included in the input video signal SIN is replaced with the input signal. The synchronization signal SYNC of this input video signal SIN
1A is indicated by a broken line.

That is, the internal sync signal generation circuit 10 generates an internal sync signal ISYNC having a minimum required pulse width as a sync signal for a CRT display (not shown) of this display device. This internal synchronization signal ISYN
C is based on the synchronization signal SYNC of the input video signal SIN, and its falling timing is the input video signal SI.
The sync signal SYNC included in N has the same timing, but when the horizontal sync frequency f _H of the input video signal SIN is high, its rising timing becomes earlier than the sync signal SYNC as shown in FIG. Sync signal SYN
The pulse width is shorter than the pulse width of C. Therefore,
The time of the back porch following the internal synchronizing signal ISYNC is substantially lengthened. As a result, even if the input video signal SIN having a high horizontal synchronizing frequency f _H , the output pulse signal S
The back porch BP timing in which the reference pulse REF generated by the waveform shaping mono multivibrator 5 with 3 as the reference timing and the pedestal clamp pulse CLAMP generated by the mono multivibrator 7 with the reference pulse REF as the reference are substantially extended. Will be housed inside.

A second embodiment of the present invention will be described. The second embodiment is an example of adopting the circuit configuration of (1) described in the above-mentioned "Means for solving the problem". In the above-described first embodiment, an example in which the sync signal SYNC in the input video signal SIN is replaced according to the horizontal sync frequency f _H to substantially extend the back porch BP period has been described. Does not change the sync signal SYNC of the input video signal SIN and the back porch BP itself. Even if the back porch BP has a short horizontal porch BP when the horizontal sync frequency f _H is high, the back porch BP is responsive to the horizontal sync frequency f _H. The reference pulse REF is generated by advancing the generation timing of the reference pulse REF, and the pedestal clamp pulse CLAMP is also generated so as to fit within the back porch BP.

In the second embodiment, the reference pulse REF is generated at a timing corresponding to the horizontal synchronizing frequency f _H with reference to the rising time of the synchronizing signal SYNC. The pedestal clamp pulse CLAMP is generated at a fixed time t2 after the reference pulse REF is generated. That is, the reference pulse REF generated at the predetermined time t1a from the rising of the synchronization signal SYNC.
Is generated according to the horizontal synchronizing frequency f _H.

In the second embodiment, the generation timing of the pedestal clamp pulse CLAMP generated after the reference pulse REF may be changed according to the horizontal synchronizing frequency f _H.

The implementation of the display device of the present invention, in particular, the implementation circuit of the signal processing circuit is not limited to the circuit configuration described above, and various other circuit configurations can be adopted. For example, the signal processing circuit may have a circuit configuration in which the above-described first embodiment and second embodiment are combined. That is, the internal synchronizing signal is generated according to the horizontal synchronizing frequency f _H of the input video signal SIN, and further the reference pulse REF and the pedestal clamp pulse C are generated according to the horizontal synchronizing frequency f _H.
Adjust the generation timing of LAMP. Also in the third embodiment, since the reference pulse REF and the pedestal clamp pulse CLAMP are within the back porch BP, the clamp operation is accurately performed and stable display is possible.

The display applied to the display device of the present invention is not limited to the CRT display described above, and may be a display of another system. Further, the video signal applied to the display device of the present invention may have a ternary sync signal or the like.

[0020]

As described above, according to the display device of the present invention, the reference pulse and the pedestal clamp pulse that can be selectively applied to the display even when the video signals having various horizontal synchronizing frequencies are input. Can be generated, stable reference operation and stable clamp operation can be performed, and the video signal can be displayed stably.

[Brief description of drawings]

FIG. 1 is a signal processing circuit diagram of a display device according to an exemplary embodiment of the present invention.

FIG. 2 is an overall signal processing waveform diagram by the signal processing circuit shown in FIG.

FIG. 3 is a partial signal processing waveform diagram in the signal processing circuit shown in FIG.

FIG. 4 is a partial signal processing waveform diagram in the signal processing circuit shown in FIG.

FIG. 5 is a signal processing waveform diagram in a conventional display device.

[Explanation of symbols]

1 ... Synchronous separation circuit, 3 ... Synchronous timing detection circuit,
5 ··· Waveform shaping mono multivibrator, 7 · · Mono multivibrator, 10 · · Internal synchronization signal generation circuit,
12 ... Amplifying circuit, 14, 16 ... Signal adding circuit, 18
..Amplification circuit, 20..Deflection system, SIN..input video signal, SOUT..output video signal

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[Procedure amendment]

[Submission date] December 27, 1991

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Full text

[Correction method] Change

[Correction content]

[Document name] Statement

Title of display device

[Claims]

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a multi-scan display device capable of selecting and displaying one of a plurality of types of video signals.

[0002]

2. Description of the Related Art For example, in a display device for a computer, one of a plurality of types of analog video signals is used.
2. Description of the Related Art A multi-scan display device is known in which a seed is selected and displayed on one type of display device, for example, a CRT display device.
One example of the waveform of such an analog input video signal is shown in FIG.
It shows in (A). This input video signal SIN is a synchronization signal SY.
The signal structure has a front porch FP in front of the NC, a back porch BP in the rear, and a video signal component, for example, a luminance signal component Y. Although the video signal does not include a synchronization signal, the same configuration as the former configuration is applied even in the case of a signal configuration having an external synchronization signal at the same position in terms of timing. In this type of display device, a plurality of video signals
Synchronous signal SYN for displaying on the CRT display of the kind
The back porch BP after C has a reference pulse REF having a height corresponding to the level for detecting the video signal level and a pedestal clamp pulse CLAMP for the pedestal clamp.

In the current multi-scan type display device, it is possible to display only two or three types of input video signals, even if it is a plurality of video signals.
As shown in (B) and (C), after detecting the synchronization signal SYNC, the reference pulse REF is generated at a fixed timing in common to these video signals, and then the pedestal clamp pulse CLAMP is also generated at a fixed timing. I am letting you.

[0004]

When the horizontal synchronization (deflection) frequency f _H becomes higher, the time of the back porch BP becomes shorter accordingly, but as described above, the reference pulse REF and the pedestal clamp pulse CLAMP are fixed in timing. , A high horizontal sync frequency f
_In the case of the _H video signal, as shown in FIG. 5C, the pedestal clamp pulse CLAMP does not fit in the timing region of the back porch BP and enters the region of the luminance signal component Y, so that the pedestal clamp cannot be performed. Come across. The problem is that the number of multi-scans increases and the range of the horizontal synchronization frequency f _H becomes, for example,
Oyobi the 31KH _z ~70KH _z, multiscan number 1
When the number of types is 0 or more, a large number of video signals having a high horizontal synchronizing frequency f _H will be present, which is particularly remarkable. As one method for solving such a problem, a method of shortening the width of the reference pulse REF and the width of the pedestal clamp pulse CLAMP can be considered, but if these pulse widths are shortened to a predetermined limit pulse width or less, the original purpose is reduced. Operation cannot be secured. Therefore, it is an object of the present invention to provide a display device capable of stably displaying a large number of video signals with a relatively simple circuit configuration.

[0005]

In order to solve the above problems, a video signal in which a back porch and a video signal component are input after a synchronizing signal is input, and a reference pulse for video signal level detection and a pedestal clamp for back porch timing are input. In the display device of the present invention which generates the pedestal clamp pulse of and outputs the video signal to the display,
A circuit is provided for generating the reference pulse and the pedestal clamp pulse within the timing of the back porch at a timing corresponding to the frequency of the input video signal. The circuit configuration is as follows: (1) The sync signal and the back porch of the input video signal are left unchanged, and the sync pulse and the pedestal clamp pulse are set within the back porch timing so that the sync pulse and A circuit configuration that changes the reference pulse generation timing and the pedestal clamp pulse generation timing. (2) When the frequency of the input video signal is high, the synchronization signal included in the input video signal is within the time required for the display. The internal sync signal for the display is switched so that it is shortened as much as possible, and the back porch is substantially lengthened by generating an internal sync signal for the display, which is substantially fixed within the extended back porch timing. To generate a reference pulse and a pedestal clamp pulse at the same timing (3) and a method of mixing circuit configuration and the circuit configuration of (2) above (1).

[0006]

In any of the above circuit configurations, the reference pulse and the pedestal clamp pulse are generated within the timing of the back porch at the timing corresponding to the frequency of the input video signal. More specifically, the above (1)
In the case of the circuit configuration of, the reference pulse and the pedestal clamp pulse are generated immediately after the sync signal in the originally short back porch in the case of the input video signal having the high horizontal sync frequency, while having the low horizontal sync frequency. In the case of the input video signal, the reference pulse and the pedestal clamp pulse are generated in the originally long back porch with a timing margin. In the case of the circuit configuration of the above (2), the synchronizing signal having the minimum pulse width necessary for the display is internally generated, and the rising timing of the internal synchronizing signal is earlier than the rising timing of the synchronizing signal of the input video signal. Then, the back porch time that follows is substantially extended. A reference pulse and a pedestal clamp pulse are stored within this extended back porch timing.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a signal processing circuit in a display device in the case of internally generating a synchronizing signal as one embodiment of a multi-scan display device of the present invention. Figure 1 (A)
Shows the entire configuration of the signal processing circuit, and FIG. 1B shows a detailed circuit of the synchronization timing detection circuit 3 of FIG. An input video signal SIN, which is one of the video signals having various horizontal synchronizing frequencies f _H , is input to a signal processing circuit, and the signal processing circuit sends a horizontal synchronizing frequency f _H to a CRT display (not shown). The output video signal SOUT having the reference pulse and the pedestal clamp pulse whose generation timings are adjusted in accordance with the above in the back porch timing is output. In the first embodiment, the generation timing of the reference pulse and the pedestal clamp pulse is adjusted by changing the width of the internal synchronizing signal according to the horizontal synchronizing frequency f _H of the input video signal SIN.

The signal processing circuit shown in FIG. 1A comprises a sync separation circuit 1, an internal SYNC / external SYNC, a discrimination circuit 2,
It has a pulse generation circuit 4, a synchronous timing detection circuit 3, a signal selection circuit 5, 6, a mono-multi-vibrator 7, 8 and a deflection system 20. Furthermore, this signal processing circuit
The amplifier circuit 12, the signal addition circuit 14, and the amplifier circuit 18 are included, and the amplifier circuit 12 to the amplifier circuit 18 configure a negative feedback loop. Figure 2 shows the waveform of the input video signal SIN
(A) shows. This signal waveform itself is the same as the waveform of FIG. 5 (A), and the front porch FP, the horizontal synchronizing signal SYNC
(Or HD), a back porch BP, and a video signal component, for example, a luminance signal component Y. In the case of the present embodiment, the signal is input from SIN in the case of the video signal including the sync SYNC, and the video signal is SIN in the case of the external sync signal.
Also, the synchronization signal is PIN or RI if necessary.
Input from N.

Also in this signal processing circuit, as shown in FIG.
As shown in (B) and (C), a reference pulse REF having a height corresponding to the video signal level is generated in the waveform shaping mono multivibrator 7 and is superimposed on the signal from the amplifier circuit 12 in the signal addition circuit 14. And
Further, in the mono-multi vibrator 8, a pedestal clamp pulse CL having a height according to the pedestal level
AMP is generated and pedestal clamped in the amplifier circuit 18. The reference pulse REF is generated a predetermined time t1 after the fall of the synchronizing signal SYNC, and the pedestal clamp pulse CLAMP is generated a predetermined time t2 after the rise of the reference pulse REF. The generation time t1 of the reference pulse REF is determined by the horizontal synchronizing frequency f _H of the input video signal SIN, as described later. The time t2 between the reference pulse REF and the pedestal clamp pulse CLAMP is constant in this embodiment, and the reference pulse REF and the pedestal clamp pulse CLAMP are constant.
The width of each is also constant.

The sync separation circuit 1 detects the sync signal SYNC included in the input video signal SIN or the external sync SYNC input from PIN, RIN to detect the sync signal SYNC.
And the separated sync signal SYNC, in this example the horizontal sync signal HD, is output to the sync timing detection circuit 3.
Further, in the case of the present embodiment, since the deflection circuit requires the horizontal synchronizing signal HD having a constant pulse width, the pulse generated by the pulse generation circuit 4 is applied to the deflection system 20 and CR is applied.
Deflection of the T indicator.

As shown in FIG. 1B, the synchronization timing detection circuit 3 includes a mono multivibrator 31 and a capacitance C.
_x of the capacitor 32, the resistance value _{R x} of the resistor 33 and 34,
It is composed of an integration comparison circuit 36 and resistors 36 and 37. The resistors 36 and 37 are the reference voltage V _ref H of the integration comparator 36.
(See FIGS. 3 and 4). FIG. 3 shows a signal waveform in the synchronization timing detection circuit 3. 3A is an enlarged waveform of the horizontal synchronizing signal HD, and FIG. 3B is a resistor 33.
3C shows the differential signal waveform of the capacitor 32, and FIG. 3C shows the output pulse signal S3 of the synchronization timing detection circuit 3. The synchronization timing detection circuit 3 integrates the horizontal synchronization signal HD and uses this integrated voltage as the pull-up voltage of the resistor 33 that sets the time constant of the mono-multivibrator 31. Therefore, when the horizontal synchronizing frequency f _H of the input video signal SIN is high, a large number of horizontal synchronizing signals HD are input within a predetermined time, so that a high integrated voltage is obtained and the time constant of the mono-multivibrator 31 becomes short. Sync timing detection circuit 3
The pulse width of the output signal S3 becomes narrower. On the contrary, in the case of low input video signal SIN of the horizontal synchronizing frequency f _H pulse width of the output pulse signal S3 becomes longer.

Details of such operation will be described with reference to FIG. When the horizontal synchronizing frequency f _H is high, the high pull-up voltage shown by the broken line in FIG. 4 is obtained, and when the horizontal synchronizing frequency f _H is low, the low pull-up voltage shown by the solid line is obtained. When the pull-up voltage is high, the output pulse signal S having the pulse width of the short time τ1 is output from the synchronization timing detection circuit 3.
3 is output, and when the pull-up voltage is low, a long time τ
An output pulse signal S3 having a pulse width of 1 is output.

In the case of the present embodiment, when the external SYNC is input, the output pulse signal S3 that has been reshaped short is output to the signal selection circuit 6 as the ISYNC used inside the apparatus by the INT / EXT discrimination circuit 2 and the signal selection circuits 5 and 6. Output to the multi-multi 7, and the synchronization signal S of the input video signal SIN
Replace YNC. When the sync signal is included in the video signal, the sync signal S of the input video signal SIN is passed even if it passes through the INT / EXT discrimination circuit 2 and the signal selection circuits 5 and 6.
YNC is output the same as when it is input. The intended operation of this display device is the former case, and ISYN
The position of C is shown by a broken line in FIG.

That is, the synchronization timing detection circuit 3 generates an internal synchronization signal ISYNC having a minimum required pulse width as a synchronization signal for a CRT display (not shown) of this display device. This internal synchronization signal ISYN
C is based on the synchronization signal SYNC of the input video signal SIN, and its falling timing is the input video signal SI.
The sync signal SYNC included in N has the same timing, but when the horizontal sync frequency f _H of the input video signal SIN is high, its rising timing is earlier than that of the sync signal SYNC as shown in FIG. Sync signal SYN
The pulse width is shorter than the pulse width of C. Therefore,
The time of the back porch following the internal synchronizing signal ISYNC is substantially lengthened. As a result, even if the input video signal SIN having a high horizontal synchronizing frequency f _H , the output pulse signal S
The back porch BP timing in which the reference pulse REF generated by the waveform shaping mono-multivibrator 7 with 3 as the reference timing and the pedestal clamp pulse CLAMP generated by the mono-multivibrator 8 with the reference pulse REF as the reference are substantially extended. Will be housed inside.

A second embodiment of the present invention will be described. The second embodiment is an example of adopting the circuit configuration of (1) described in the above-mentioned "Means for solving the problem". In the first embodiment described above, an example in which the sync signal SYNC in the input video signal SIN is replaced according to the horizontal sync frequency f _H to substantially extend the back porch BP period has been described. Does not change the sync signal SYNC of the input video signal SIN and the back porch BP itself. Even if the back porch BP has a short horizontal porch BP when the horizontal sync frequency f _H is high, the back porch BP can be adjusted according to the horizontal sync frequency f _H. The reference pulse REF is generated by advancing the generation timing of the reference pulse REF, and the pedestal clamp pulse CLAMP is also generated so as to fit within the back porch BP.

In the second embodiment, the reference pulse REF is generated at a timing corresponding to the horizontal synchronizing frequency f _H with reference to the rising time of the synchronizing signal SYNC. The pedestal clamp pulse CLAMP is generated at a fixed time t2 after the reference pulse REF is generated. That is, the reference pulse REF generated at the predetermined time t1a from the rising of the synchronization signal SYNC.
Is generated according to the horizontal synchronization frequency f _H.

[0017] In this second embodiment, it may be a generation timing of the pedestal clamp pulse CLAMP generated after the reference pulse REF is varied in response to the horizontal synchronizing frequency f _H.

The implementation of the display device of the present invention, in particular, the implementation circuit of the signal processing circuit is not limited to the circuit configuration described above, and various other circuit configurations can be adopted. For example, the signal processing circuit may have a circuit configuration in which the above-described first embodiment and second embodiment are combined. That is, the internal synchronizing signal is generated according to the horizontal synchronizing frequency f _H of the input video signal SIN, and further the reference pulse REF and the pedestal clamp pulse C are generated according to the horizontal synchronizing frequency f _H.
Adjust the generation timing of LAMP. Also in the third embodiment, since the reference pulse REF and the pedestal clamp pulse CLAMP are within the back porch BP, the clamp operation is accurately performed and stable display is possible.

The display applied to the display device of the present invention is not limited to the CRT display described above, and may be a display of another system. Further, the video signal applied to the display device of the present invention may have a ternary sync signal or the like.

[0020]

As described above, according to the display device of the present invention, the reference pulse and the pedestal clamp pulse that can be selectively applied to the display even when the video signals having various horizontal synchronizing frequencies are input. Can be generated, stable reference operation and stable clamp operation can be performed, and the video signal can be displayed stably.

[Brief description of drawings]

FIG. 1 is a signal processing circuit diagram of a display device according to an exemplary embodiment of the present invention.

FIG. 2 is an overall signal processing waveform diagram by the signal processing circuit shown in FIG.

FIG. 3 is a partial signal processing waveform diagram in the signal processing circuit shown in FIG.

FIG. 4 is a partial signal processing waveform diagram in the signal processing circuit shown in FIG.

FIG. 5 is a signal processing waveform diagram in a conventional display device.

[Explanation of Codes] 1 ... Sync Separation Circuit, 2 ... INT / EXT Discrimination Circuit,
3 ・ ・ Synchronous timing detection circuit, 4 ・ ・ Pulse generation circuit, 5, 6 ・ ・ Signal selection circuit, 7, 8 ・ ・ Mono multivibrator, 12 ・ ・ Amplification circuit, 14 ・ ・ Signal addition circuit, 18 ・ ・ Amplification circuit Circuit, 20 ... Deflection system, SIN ... Input video signal, SOUT ... Output video signal, PIN ... Input sync signal (horizontal, vertical, composite sync signal or horizontal sync signal), RIN ... Vertical sync signal.

[Procedure 3]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 1

[Correction method] Change

[Correction content]

[Figure 1]

Claims (1)

Claim: What is claimed is: 1. A video signal in which a back porch and a video signal component follow after a synchronizing signal is input, and a reference pulse for detecting a video signal level and a pedestal clamp pulse for a pedestal clamp are generated in the back porch. A display device for outputting a video signal to a display device by using a circuit for generating the reference pulse and the pedestal clamp pulse within the timing of the back porch at a timing according to the frequency of the input video signal. apparatus.