JPS62139058A - Memory controller - Google Patents

Abstract

PURPOSE:To execute primary processing at a high speed by providing a normal logic area of a memory area and an excessive logic area of the memory area where excessive physical memories are is allocated and decreasing the deciding frequency for presence or absence of allocation of the physical memory. CONSTITUTION:An area 25a set at the bottom side of a stack 25 serves as a normal logic area and a register SP12 which indicates the highest part of the stack 25 indicates a certain area in the area 25a. While an excessive logic area 25b is set immediately after the area 25a and along the extending direction of the stack 25. Thus the dynamic allocation of the physical memory is carried out by recognizing access given to the area 25b. However, a fact that access is secured within the area 25b is stored together with a fact that access is given to the area 25b. Therefore, it is enough to decide access given to the area 25b just in a single time after all accesses are through in terms of the consumption of the continuous logic memory spaces within an amount less than the size of the area 25b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control device for a digital computer.

[Prior Art] Conventionally, in a memory device having a large-capacity logical storage space and a small-capacity physical storage space compared to this logical storage space, allocation of a physical storage area corresponding to a specific logical storage area has been carried out. , is a configuration diagram showing one entry of the address translation table if physical storage is allocated when the logical storage area is accessed. The memory control device shown in FIG.
This is used when performing dynamic allocation, and here,
To simplify the explanation, the logical address is 24 bits,
The physical address is 20 bits, and the physical memory allocation unit is 1.
Although it is assumed that the conversion from 0.024 word and logical address to physical address is performed by one stage table search, these numerical values and the method such as the number of stages of table search are not essential at all.

In FIG. 7, a logical address is supplied by an arithmetic processing unit (not shown) or the like via a signal line 1, and is supplied to a logical address register LAR2. LAR2
The upper 22 bits, ie, bits 23 to 10, are supplied via signal line 3 to ATT4, which is an address translation table. ATT4 is a table having 16,384 entries, and each entry has a configuration as shown in FIG. That is, bit 10, 4a, which is the most significant bit, indicates whether physical storage is allocated or not, and is transmitted to an arithmetic processing unit (not shown) or the like via the signal line 5 shown in FIG.

The lower 10 bits of each entry of ATT4, that is, bits 9 to 0, 4b, are flags that are information indicating which physical storage unit is allocated, and are connected to signal line 6 shown in FIG.
is supplied to the upper 10 bits, bits 19-10, of the physical address register PAR7.

The lower 10 bits of LAR2, that is, bits 9 to O, are
It is directly supplied to the lower 10 bits of PAR7, ie, bits 9 to O, via signal line 8. The physical address, which is the content of PAR 7, is transmitted via signal line 9 to a memory element (not shown) constituting physical storage.

FIG. 4 is a block diagram showing a part of the arithmetic processing unit of the computer that implements the dynamic allocation method of physical storage, and FIG.
FIG. 4 is a block diagram showing part of the microinstructions in the computer, FIG. 6 is a flowchart showing a microprogram that performs stack processing in the computer in FIG. 4, and FIG. A method for dynamically allocating physical memory using a conventional memory control device will be explained using a microblock controlled computer with a stack as an example. A part of the processing unit of such a computer is It is assumed that the configuration shown in Fig. 4 is as shown in Fig. 4.
In the configuration shown in the figure, the same components as in FIG. 7 are given the same numbers. Reference numeral 10 shown in FIG. 4 is a register D for data transfer between the memory device, the arithmetic processing device, and the arithmetic processing device. Data written to the memory device and data read from the memory device are transferred via a signal line 11. It is transmitted by A register SP 12 indicates the next address at the top of the stack, and has the function of increasing or decreasing by "1". A register C 13 is a counter used for loop control, and has a function of decrementing by "1" and a function of determining whether the contents are "0" or not. 1
4 is a data bus, each signal line 15a, 15b, 1
5c or 15d, register D10. register 5
P12. Either register C13 or constant "0" is output to data bus 14. In addition, each signal line 1.
15a, 15b or 15c3.

Next, it is assumed that a part of the microinstructions that control the arithmetic processing unit and the memory device have a configuration as shown in FIG. 16a shown in FIG. 5 controls the memory device and specifies read (Read), write (Write), or no operation (Nop). 16b data bus 14
Register DIO, register 5P12. Register C13 or constant r□.

Specify. 16c are logical address registers LAR2, registers D10 . Specifies that the data is not stored in either register 5P12 or register C13 (Nop). 16d increases register 5P12 by "1" (SP++)
, r 1 , specifies a decrease (sp--) or no action (Nop). 16e sets register C13 to “1”.
” (C-1) or no action (Nop). 16f is a branch condition that the content of register C13 is rQ (C=O), that the content of register C13 is not "0" (C≠0), and that the most significant bit of the output of ATT4, which is an address conversion table, is After “1” (N
op). 16g specifies a branch (Jump) to the address specified by 16h or a branch (Eop) to an address determined for each instruction code of the microinstruction. Note that when the branch condition is not satisfied, the immediately following microinstruction is executed. Further, when determining the contents of the register C13, if the same microinstruction specifies an update of the register C13, the value before the update is used. Furthermore, when the same instruction specifies an update of the logical address register LAR2, the address used for accessing the memory device uses the value before the update. Further, the output of the register 5P12 to the data bus 14 uses the value before the update when the same instruction specifies an update of the register 5P12. Furthermore, it is assumed that the determination of the most significant bit of the output of the address translation table ATT4 is valid only for the microinstruction immediately after accessing the memory device.

FIG. 9 shows a flowchart of a microprogram for executing the macro instruction PUSH2n in the above computer. This is the part that reads the macro instruction and decodes the instruction code, and branches to the microprogram routine 18 that processes the macro instruction PUSH2, and stores the operand "n" of the macro instruction PUSH2 in the register DIO. do. The microprogram routine 18 is composed of microinstructions 18a, 18b, and 18c.

Consisting of 18d, 18e and 18f. 18a each.

18b and 18c are preprocessing, and each register 013 and D
Initializes the IO and logical address register LAR2. Each of 18d and 18e constitutes a loop, and each execution pushes one "0" onto the stack. The main processing of this loop is performed by 18d, but 18e is required to know whether physical storage is allocated or not. 1
8f performs post-processing to correct the value of register 5P12 which has increased by 1 too much. 19 is a part that performs physical storage allocation processing. In step 19a, it is determined whether the allocation process can be processed by a microprogram. For example, if it is possible because there is no unused physical memory, then in step 19b, the unused physical memory is acquired and an address conversion table is created. The acquired physical memory address is written in the corresponding entry of ATT4, and the most significant bit of the entry is set to "1". After that, it returns to 18d.

If the microprogram cannot process the process, 19
Perform with c. At that time, after executing the predetermined processing routine, in order to continue processing the macro instruction PUSH2 from the point where it was interrupted, each register DIO, C13 and the logical address register LAR2 are saved, and the micro instruction to be continued is 18d. It is necessary to remember that.

[Problems to be Solved by the Invention] In a method for dynamically allocating physical storage using the conventional memory control device as described above, the macro instruction PUSH
Regarding process 2, there are three problems. The first reason is that the determination of the presence or absence of physical memory allocation performed in 18e shown in FIG. 9 is necessary in addition to the main processing performed in 18d of the same figure, so it also appears in the macro instruction 41. The problem is that it is difficult to standardize the physical pre-memory allocation process. If commonization is forced, it will be necessary to save the internal state of registers and the like in order to return to the processing continuation point for each macro instruction, which will increase the processing time for physical memory allocation processing. Third, in the indexing process performed at 19c shown in FIG. 9, in order to return to the processing continuation point that exists in the middle of macro instruction processing, each register DIO , C13 and the logical address register LAR2, which complicates the mechanism for realizing general indexing and interrupts and increases processing time. Such a problem is that whenever access is made to a logical space for which it is unknown whether or not physical storage has been allocated, as in 18d shown in FIG. 9, a determination like 18e in the figure is always required. It is the cause.

This invention was made to solve these problems, and reduces the frequency of determining whether or not physical memory is to be allocated, making it possible to execute main processing at high speed, and making it possible to standardize the process of allocating physical memory. In order to obtain a memory control device that can be simplified, in addition to the normal logical area to which physical storage is normally allocated to the storage area, extra physical storage is allocated to the storage area. This system adds one dimension to the excess logical area, guarantees the result of access to this excess logical area, and at the same time includes a mechanism for storing the fact that an access to the excess logical area has occurred.

[Operation] In the memory control device of the present invention, dynamic allocation of physical storage is performed by recognizing access to the excess logical area. Since it is remembered that an access to a logical area has occurred, the determination of an access to an excess logical area is It is sufficient to do this only once after the access has ended.

[Embodiment] FIG. 1 is a block diagram showing a memory control device according to an embodiment of the present invention, and FIG. 2 is a construction diagram showing one entry of an address translation table in the memory control device shown in FIG. be. In order to simplify the explanation, an assumption similar to the example of the conventional memory control device shown in FIG. Needless to say, this is not something that can be done.

Further, since the same reference numerals as in the conventional memory control device shown in FIG. 7 represent the same constituent elements, a detailed explanation thereof will be omitted. 20 shown in FIG. 1 is the ATT4 shown in FIG.
Similarly, the address translation table ATT is composed of two parts, each entry of which is composed of two parts as shown in FIG. The flags 20b and 20c shown in FIG. 2 correspond to the flags 20b and 20c shown in FIG. They correspond to the lugs 4a and 4b, respectively, and their meaning and relationship with the constituent elements of the pond are the same as in FIG. 20a shown in FIG. 2 is a 1-bit flag indicating whether or not the area is an excess logical area, and if the value is "0", it indicates that the area is a normal logical area.

If so, it indicates that it is an excess logical area.

Note that this flag 20a is significant only when the flag 20b is "1", that is, when physical storage is allocated. The flag 20a is also transmitted to the terminal S to the flip-flop 22 via the signal line 21. The flip-flop 22 is an SR flip-flop or has a similar function, and holds the state if both the S and R terminals are "0", and retains the state if the S terminal is "1". If the R terminal is “1”, the state is “1”.
0” respectively. Flip flop 22 R
A reset signal is supplied to the terminal from an arithmetic processing unit (not shown) or the like via a signal line 23, and the state of the flip-flop 22 is transmitted from the Q terminal to the arithmetic processing unit or the like via a signal line 24.

Next, a method for dynamically allocating physical storage using the memory control device according to the present invention will be explained using a microprogram-controlled computer having a stack as in the conventional example described above. In this example, the logical storage area corresponding to the stack has the configuration shown in FIG. That is,
The leftmost end of the stack 25 shown in FIG. 3 corresponds to the stack bottom, and the stack 25 is expanded from left to right.

Note that the addresses increase from left to right.

An area 25a on the bottom side of the stack 25 is a normal logical area, and a register 5P1 indicating the top of the stack 25
2 indicates somewhere within the normal logical area 25a.

The excess logical area 25b is placed immediately after the normal logical area 25a in the direction in which the stack 25 extends. Such a configuration makes consecutive entries in the address translation table ATT20 in the memory control device according to the present invention, that is, the ATT20 shown in FIG. 1, correspond to the logical storage area of the stack 25, and
This can be realized by setting the most significant bit of one or more entries, that is, the flag 20a shown in FIG. 2, to "l".

Next, a part of the arithmetic processing unit and microinstructions in the computer of this example are shown in FIG. 11 and FIG. 5, respectively, as in the above-mentioned conventional example. However, 16f in Figure 5
AIIocateJ and Not^11oeat in
In the conventional example, ed was based on the value of the signal line 5 shown in FIG. 7, but in this example, if the signal line 24 in FIG. 1 is "O", A11ocated, '
If it is IJ, it is determined as Not AIIorateJ. Note that the arithmetic processing unit and microinstructions are not directly related to the present invention, and the application of the present invention is not limited by this example.

Next, FIG. 6 shows a microprogram flow number 1 for executing the above-mentioned macro instruction PUSH2. The portion 26 shown in FIG. 6 is similar to the portion 17 shown in FIG. 9 above, but when branching due to the instruction code of a macro instruction, it determines whether or not the excess logical area 25b is accessed and stores the access event. Only when the instruction code is not executed, a branch is made to the microprogram routine 27 corresponding to the instruction code. This microprogram routine 27 processes the macro instruction PUSH2, and is similar to the microprogram routine 18 shown in FIG. 9 with 18e removed, that is, 27a and 27a shown in FIG.
7b, 27c, 27d and 27e are 18 shown in FIG.
Similar to a, 18b, 18C, 18d and 18f.

Excess logical area 25 occurred during processing of macro instruction PtJSH2.
When access is made to 25b, when the next macro instruction is decoded at 26 after processing is completed, it is recognized that an access has occurred to the excess logical area 25b, and the section 28 performs physical memory allocation processing. Branch to. In addition,
In this case, stack 2 in macro instruction PUSH2
The expansion of 5 is 1023 words or less, and the excess logical area 2
Since 5b has a capacity of 1024 words or an integral multiple thereof, the processing result of macro instruction PUSH2 is completely guaranteed.

The judgment conditions for 28a shown in FIG. 6 are as follows for 19a shown in FIG.
It is similar to Further, in 28b shown in FIG. 6, unused physical memory is acquired in units of 1024 words or in units of one or more units. There are two methods for allocating this acquired physical storage area to the logical storage area corresponding to the stack. The first method is to change only the most significant bit of the entry of the ATT20 which is the address translation table corresponding to the excess logical area 25b, that is, the flag 20a in FIG. 2, to "r□",
Each bit 11, 10 and 9 to 0 of one or more subsequent entries, that is, each flag 20a, 20 shown in FIG.
b and 20c 'IJ, 'IJ.

and a method of changing the address to the acquired physical memory address. The second method is to copy the contents of the physical memory corresponding to the excess logical area 25b to the acquired physical memory, and bits 11 and 9 to 9 of the entry of the ATT20 which is the address translation table corresponding to the excess logical area 25b. 0, that is, each flag 20a and 20c shown in FIG.
”, and change to the acquired physical memory address, bits 11, 10 and 9 to 0 of the following one or more entries.
, that is, each flag 20a shown in FIG.

20b and 20c as rl'', rl4. and the physical storage address corresponding to the excess logical area 25b. Any method is applicable to this invention. After allocating physical memory,
The clip-flop 22 shown in FIG. 1 is reset and instruction fetch and decoding are performed again. In 28c shown in FIG. 6, only the information to be transmitted between multiple macro instructions, such as the address of the instruction to be executed next to the macro instruction PtJSH2, is stored and indexed to a predetermined processing routine. Flip-flop 22 shown in the figure
Reset.

As described above, in this example, compared to the conventional example, the loop in the processing routine of the macro instruction PtJSH2 is composed of a single microinstruction, so that the processing time is reduced. In addition, since physical memory allocation is performed after execution of macro instruction processing, common processing routines can be easily shared, and even in indexing processing, only the same information as general indexing and interrupts needs to be saved. .

In the above embodiment, the bush 3 of multiple words is added to the stack 25, but it is clear that the processing time can be shortened by removing the stain judgment 3 even in the bush of a single word. .

Furthermore, although the above embodiment has been explained using the stack 25 as an example, it is obvious that it can also be applied to a storage area that consumes logical storage space in a continuous and sequential manner, such as a heap, in the same way as the stack 25. be.

Furthermore, in the above embodiment, the presence or absence of access to the excess logical area 25b is determined after the execution of one macro instruction is completed, but for some reason, the existence of a macro instruction that performs this determination during the processing is denied. It is not something to do,
Furthermore, it goes without saying that the present invention can be applied even to a computer that does not have the concept of a macro instruction by appropriately inserting a determination as to whether or not to access the excess logic area 25b.

[Effects of the Invention] As explained above, in a memory control device, the excess logical area is added to (4, Since the configuration is configured to guarantee access to the area and to remember whether or not there is an access to the excess logical area, it is possible to reduce the frequency of determining whether or not to allocate physical memory and increase the processing time of the main process. This has the profound effect of making it possible to quickly and easily implement dynamic physical memory allocation processing.

[Brief explanation of drawings]

1 [21 is a block configuration diagram showing a memory control device which is an embodiment of the present invention, FIG. 2 is a configuration diagram showing one entry of the address translation table in the memory control device of FIG. 1, and FIG. 1 is a block diagram showing a logical storage area corresponding to the stack in the memory control device of FIG. 1, FIG. Figure 5 is a block diagram showing part of the microinstructions in the computer shown in Figure 4, Figure 6 is a flowchart showing a microprogram that performs stack processing in the computer shown in Figure 4, and Figure 7 is a conventional memory control system. FIG. 8 is a block diagram showing one entry of the address translation table in the memory control device shown in FIG. 7; FIG. 9 is a block diagram showing the conventional memory control device shown in FIG. 7; A flowchart showing a microprogram for performing stack processing in the rt11 equipped with the arithmetic processing unit and microinstructions shown in FIGS. 4 and 5.
6ru. In the figure, l, 3.5.6, 8.9, 11°15a
~15d, 21.23.24 -- Signal line, 2 -- Logical address register (LAR), 7 -- Physical address register, (PAR), 10 -- Register (D
), 12...Register (SP), 13...Register C
C>, 20...address translation table, (ATT),
20a, 20b, 20cm - flag, 22... flip-flop, 25... stack, 25a... normal logic area, 25b... excess logic area, 27... microprogram routine. In each figure, the same reference numerals indicate the same or equivalent parts. Applicant Todoroki Director, Agency of Industrial Science and Technology Predicate Figure 1 1.3, 5, 6, 8, 9, 21, 23, 24'a
Kame procedural amendment (In button, July 73, 1947)

Claims (1)

[Claims] In a memory device having one or more stack-like storage areas that sequentially consume continuous logical storage space, each of the storage areas has a method of allocating physical storage corresponding to the storage area as necessary. has a normal logical area of the storage area to which physical storage is normally allocated and an excess logical area of the storage area to which extra physical storage is allocated, and this excess logical area is used to consume the logical storage space. The storage device is arranged immediately after the normal logical area according to the direction, and has a mechanism capable of determining access to the normal logical area and the excess logical area, and storing the event regarding access to the excess logical area. A memory control device characterized by: