JPH0255813B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory control device for a digital computer.

[Prior Art] Conventionally, in a memory device having a large-capacity logical storage space and a small-capacity physical storage space compared to this logical storage space, allocation of a physical storage area corresponding to a specific logical storage area is A dynamic allocation method is often used in which physical storage is allocated if it is not allocated when the logical storage area is accessed.

FIG. 7 is a block diagram showing a conventional memory control device, and FIG. 8 is a diagram showing one entry of an address translation table in the memory control device shown in FIG. The memory control device shown in FIG. 7 is used when performing dynamic allocation, and here,
To simplify the explanation, we assume that the logical address is 24 bits, the physical address is 20 bits, the physical memory allocation unit is 1024 words, and the conversion from logical address to physical address is performed by a one-step table lookup. However, these numerical values and the method such as the number of stages of table search are not essential at all.

In FIG. 7, a logical address is supplied by an arithmetic processing unit (not shown) or the like via a signal line 1, and is supplied to a logical address register LAR2. The upper 14 bits of LAR2, ie, bits 23 to 10, are supplied via signal line 3 to ATT4, which is an address translation table. ATT4 is
This table has 16,384 entries, and each entry has a structure as shown in FIG. In other words, the most significant bit, bit 10,
4a is a 1-bit flag that indicates whether physical memory is allocated or not. If the value is "0", it indicates that physical memory is not allocated.
If so, this indicates that physical storage has been allocated, and is transmitted to an arithmetic processing unit (not shown) or the like via the signal line 5 shown in FIG. ATT
The lower 10 bits of each entry of 4, that is, bits 9 to 0, 4b, is a field that holds information indicating which physical storage unit is allocated. It is supplied to the upper 10 bits of register PAR7, ie, bits 19-10. The lower 10 bits of LAR2, bits 9 to 0, are directly connected to the lower 10 bits of PAR7, bits 9 through signal line 8.
~0 is supplied. The physical address, which is the content of PAR7, is transmitted via signal line 9 to a memory element (not shown) that constitutes physical storage.

FIG. 4 is a block diagram showing a part of the arithmetic processing unit of the computer that implements the dynamic allocation method of physical memory. 9 is equipped with the conventional memory control device shown in FIG.
2 is a flowchart showing a microprogram that performs stack processing in a computer equipped with the arithmetic processing unit and microinstructions shown in the figure.

Next, a method for dynamically allocating physical storage using the conventional memory control device described above will be explained using a microprogram-controlled computer having a stack as an example. It is assumed that a part of the arithmetic processing unit of such a computer has a configuration as shown in FIG. In the configuration shown in FIG. 4, the same components as in FIG. 7 are given the same numbers. Fourth
10 shown in the figure is a register D for data transfer between the memory device, the arithmetic processing device, and the arithmetic processing device, and data written to the memory device and data read from the memory device are transmitted via a signal line 11. be done. A register SP 12 indicates the next address at the top of the stack, and has the function of increasing or decreasing by "1". A register C 13 is a counter used for loop control, and has a function of decrementing by "1" and a function of determining whether the contents are "0" or not. 14 is data
The register D10, the register
Any one of SP12, register C13, or constant "0" is output to data bus 14. Also, the value of the data bus 14 is transferred to the logical address register LAR2, register D10, register SP1 via each signal line 1, 15a, 15b or 15c.
2 or register C13.

Next, it is assumed that part of the microinstructions that control the arithmetic processing unit and the memory device have a configuration as shown in FIG. 16a shown in FIG. 5 controls the memory device and specifies read, write, or no operation (Nop). 1
6b is a register D1 that outputs to the data bus 14.
0, register SP12, register C13, or constant "0". 16c is a logical address register LAR2 that stores the value of the data bus 14;
Specifies that the data is not stored in register D10, register SP12, or register C13 (Nop). 16d specifies that the register SP12 should be increased by 1 (SP++), decreased by 1 (SP--), or not operated (Nop).
16e specifies that the register C13 is to be decremented by "1" (C--) or to have no operation (Nop). 16
f is a branch condition that the content of register C13 is "0" (C=0), that the content of register C13 is not "0" (C≠0), and the most significant bit of the output of ATT4, which is an address conversion table. is "1" (Allocated), the most significant bit of the output of the address translation table ATT4 is "0" (Not Allocated), or an unconditional branch is to be performed (Nop). 16g is 1
Specifies a branch (Jump) to the address specified by 6h or a branch (Eop) to an address determined for each instruction code of the microinstruction. Note that when the branch condition is not satisfied, the immediately following microinstruction is executed. Furthermore, when determining the contents of the register C13, if an update instruction for the register C13 is given in the same microinstruction, the value before the update is used. In addition, the address used to access the memory device can be set to a logical address register in the same instruction.
If an update of LAR2 is specified, the value before update shall be used. Furthermore, when the register SP12 is specified to be updated by the same instruction, the output of the register SP12 to the data bus 14 uses the value before the update. Furthermore, it is assumed that the determination of the most significant bit of the output of the address translation table ATT4 is valid only for the microinstruction immediately after accessing the memory device.

FIG. 9 shows a flowchart of a microprogram for executing the macro instruction PUSHZ n in the above computer. Note that the above microinstruction adds the constant "0" to "n" in the stack.
For the sake of simplicity, it is assumed that "n" is a positive integer not exceeding 1023. Reference numeral 17 shown in FIG. 9 is a part that reads macro instructions and decodes instruction codes, and branches to a microprogram routine 18 that processes the macro instruction PUSHZ, and stores the macro instruction in register D10.
Stores the operand "n" of PUSHZ. The microprogram routine 18 consists of microinstructions 18a, 18b, 18c, and 18.
d, 18e and 18f. Each 18a, 18
b, 18c are preprocessing, and each register C13,
Initialize D10 and logical address register LAR2. Each of 18d and 18e constitutes a loop, and each execution pushes one "0" onto the stack. The main processing of this loop is performed by 18d, but 18e is required to know whether physical storage is allocated or not. 18f performs post-processing to correct the value of register SP12 which has increased by one too much. 19 is a part that performs physical storage allocation processing. 19a determines whether the allocation process can be handled by a microprogram. For example, if there is no unused physical memory and it is necessary to retrieve unnecessary physical memory or swap out to auxiliary memory, the microprogram The program determines that it cannot be processed. If it can be processed by the microprogram, an unused physical memory is acquired in 19b, the address of the acquired physical memory is written in the corresponding entry of the address translation table ATT4, and the most significant bit of the entry is written as " 1”. After that, it returns to 18d.
If the microprogram is unable to process the process, 19c performs processing to index the process to a predetermined processing routine configured by macro instructions. At that time, after executing the predetermined processing routine, each register D10, C13 and the logical address register
There is only one microinstruction to save and continue LAR2.
It is necessary to remember that it is 8d.

[Problems to be solved by the invention] Using the conventional memory control device as described above,
In the method of dynamically allocating physical storage, there are three problems with the processing of the macro instruction PUSHZ. The first is that the determination of the presence or absence of physical storage allocation performed at 18e shown in FIG.
This is an increase in processing time due to the fact that the loop is composed of two microinstructions, which are required in addition to the main processing performed in the microinstruction. Second, after the physical memory allocation process performed at 19b shown in FIG. 9 is completed, it is necessary to return to 18d in the same figure, so the physical memory allocation process will appear in many macro instructions. It is difficult to standardize the information. If commonization is forced, it will be necessary to save the internal state of registers and the like in order to return to the processing connection point for each microinstruction, which will increase the processing time for physical memory allocation processing. Thirdly, in the indexing process performed at 19c shown in FIG. 9, each register D10, which is originally a working register during macro instruction processing, is used to return to the processing continuation point that exists in the middle of macro instruction processing. ，
It is necessary to save C13 and the logical address register LAR2, which complicates the mechanism for realizing general indexing and interrupts and increases processing time. This kind of problem occurs whenever access is made to a logical space for which it is unclear whether or not physical storage has been allocated, such as 18d shown in Figure 9.
This is due to the need for a judgment like 8e.

This invention was made to solve these problems, and reduces the frequency of determining whether or not physical memory is to be allocated, making it possible to execute main processing at high speed, and making it possible to standardize the process of allocating physical memory. The object is to obtain a memory control device that can be simplified.

[Means for Solving the Problems] The memory control device according to the present invention is capable of correctly allocating physical storage to a storage area that sequentially consumes continuous logical storage space, such as a stack. In addition to the normal logical area that is
An excess logical area to which extra physical storage is allocated is added, and a mechanism is provided to guarantee the result of access to this excess logical area and at the same time to store the fact that an access to the excess logical area has occurred.

[Operation] In the memory control device of the present invention, dynamic allocation of physical storage is performed by recognizing access to the excess logical area. Since the access to the logical area is remembered,
For consumption of contiguous logical storage space in an amount that does not exceed the size of the excess logical area, it is sufficient to determine access to the excess logical area only once after all accesses have been completed.

[Embodiment] FIG. 1 is a block configuration diagram showing a memory control device according to an embodiment of the present invention, and FIG. 2 is a configuration diagram showing one entry of an address translation table in the memory control device shown in FIG. be. In order to simplify the explanation, an assumption similar to the example of the conventional memory control device shown in FIG. 7 above is used, and this assumption is not essential in any way. Needless to say, it is not intended to limit. Also, since the same reference numerals as in the conventional memory control device shown in FIG. 7 are the same components,
A detailed explanation thereof will be omitted. 20 shown in Figure 1
is an ATT of the address translation table like ATT4 shown in FIG. 7, but each entry thereof is composed of three parts as shown in FIG. Each flag 20b and field 20c shown in FIG. 2 correspond to the flag 4a and field 4b shown in FIG. 8, respectively, and their meanings and relationships with other components are the same as in FIG. 8. 20a shown in Fig. 2 is a 1-bit flag indicating whether or not the area is an excess logical area. , respectively. Note that this flag 20a is significant only when the flag 20b is "1", that is, when physical storage is allocated. The flag 20a is also transmitted to the terminal S to the flip-flop 22 via the signal line 21. Flip-flop 22 is an SR flip-flop.
It is a flop or something with a similar function, and if the S and R terminals are both "0", it holds the state, and if the S terminal is "1", the state is set to "1", and the R terminal changes the state to "1". If it is “1”, the status is “0”
Change each to A reset signal is supplied to the R terminal of the flip-flop 22 from an arithmetic processing unit (not shown) via a signal line 23, and the state of the flip-flop 22 is supplied to the R terminal of the flip-flop 22 via a signal line 24 from an arithmetic processing unit, etc. transmitted to.

Next, a method for dynamically allocating physical storage using the memory control device according to the present invention will be explained using a microprogram-controlled computer having a stack as in the prior art example. In this example, the logical storage area corresponding to the stack has the configuration shown in FIG. That is, the leftmost end of the stack 25 shown in FIG. 3 corresponds to the stack bottom, and the stack 25 is expanded from left to right.
Note that the addresses increase from left to right. The area 25a on the bottom side of the stack 25 is a normal logic area, and the register SP12 pointing to the top of the stack 25 points to one of the areas within the normal logic area 25a. The excess logical area 25b is
According to the direction in which the stack 25 extends, it is usually placed immediately after the logical area 25a. Such a configuration makes consecutive entries in the address translation table ATT20 in the memory control device according to the present invention, that is, the ATT20 shown in FIG. 1, correspond to the logical storage area of the stack 25,
This can be realized by setting the most significant bit of one or more entries at the end, that is, the flag 20a shown in FIG. 2, to "1".

Next, a part of the arithmetic processing unit and microinstructions in the computer of this example are stored in the fourth
These are shown in FIG. 5 and FIG. 5, respectively. However, Allocated and Not in 16f of Figure 5
In the conventional example, Allocated was determined by the value of the signal line 5 shown in FIG. 7, but in this example, if the signal line 24 in FIG.
Allocated, and if it is "1", it is defined as Not Allocated. Note that the arithmetic processing unit and microinstructions are not directly related to the present invention, and the application of the present invention is not limited to this example.

Next, the flowchart of the microprogram for executing the macro instruction PUSHZ mentioned above is shown in the sixth section.
Shown in the figure. The portion 26 shown in FIG. 6 is similar to the portion 17 shown in FIG.
5b is accessed, and only when the access event is not stored, branches to the microprogram routine 27 corresponding to the instruction code. This microprogram routine 27 processes the macro instruction PUSHZ, and the microprogram routines 18 to 18 shown in FIG.
This is the same as with e removed. That is, 27a, 27b, 27c, 27d and 27e shown in FIG. 6 are the same as 18a, 18b, 18 shown in FIG.
c, 18d and 18f. macro instructions
If the excess logical area 25b is accessed during PUSHZ processing, when the next macro instruction is decoded in 26 after the processing is completed, the occurrence of the access to the excess logical area 25b is recognized and the physical The process branches to a part 28 that performs storage allocation processing. In this case, the macro instruction
The expansion of the stack 25 in PUSHZ is 1023 words or less, and the excess logical area 25b has a capacity of 1024 words or an integral multiple thereof, so the macro instruction
PUSHZ processing results are completely guaranteed. The judgment conditions for 28a shown in FIG. 6 are as follows for 19a shown in FIG.
It is similar to Further, in 28b shown in FIG. 6, unused physical memory is acquired in units of one or more units of 1024 words. There are two methods of allocating this acquired physical storage area to the logical storage area corresponding to the stack. The first method is to
ATT, which is the address translation table corresponding to b
The most significant bit of the 20 entries, i.e. the second
Only the flag 20a in the figure is changed to "0", and each bit 11, 10, and 9 to 1 of the following one or more entries is changed to "0".
0, that is, the flags 20a, 20 shown in FIG.
This is a method of changing the fields 20c and 20c to "1", "1", and the acquired physical storage address, respectively. The second method is to copy the contents of the physical memory corresponding to the excess logical area 25b to the acquired physical memory, and copy each bit 11 and 9 to 9 of the entry of the ATT20 which is the address translation table corresponding to the excess logical area 25b. 0, that is, change the flag 20a and field 20c shown in FIG. 2 to "0" and the acquired physical memory address, and then
or bits 11, 10, and 9 of multiple entries
0, that is, the flags 20a, 20 shown in FIG.
In this method, the fields 20c and 20c are respectively changed to "1", "1", and the physical storage address corresponding to the excess logical area 25b. Any method is applicable to this invention. After the physical memory allocation is completed, the flip-flop 22 shown in FIG. 1 is reset, and instruction fetching and decoding are executed again. 2 shown in Figure 6
In step 8c, only information transmitted between a plurality of macro instructions, such as the address of the instruction to be executed next to the macro instruction PUSHZ, is saved and indexed to a predetermined processing routine. At this time, the flip-flop 22 shown in FIG. 1 is reset.

As described above, in this example, compared to the conventional example, the loop in the processing routine of the macro instruction PUSHZ is composed of a single microinstruction, so that the processing time is reduced. In addition, since physical memory allocation is performed after execution of macro instruction processing, it is easy to standardize processing routines, and even in indexing processing, only the same information as in general indexing and interrupts needs to be saved.

In the above embodiment, the pushing of a plurality of words onto the stack 25 has been described, but it is clear that the processing time can be shortened by eliminating conditional determination even when pushing a single word.

Further, although the above embodiment has been explained using the stack 25 as an example, it is obvious that the application can also be applied to a storage area that consumes logical storage space in a continuous and sequential manner, such as a heap, in the same way as the stack 25. be.

Furthermore, in the above embodiment, the presence or absence of access to the excess logical area 25b is determined after the execution of one macro instruction is completed, but for some reason, the existence of a macro instruction that performs this determination during the processing is denied. It's not something you do. Furthermore, it goes without saying that the present invention can be applied even to a computer that does not have the concept of a macro instruction by appropriately inserting a determination as to whether or not to access the excess logic area 25b.

[Effects of the Invention] As explained above, in a memory control device, the present invention adds an excess logical area to a storage area such as a stack that sequentially consumes logical storage space, and stores data within this excess logical area. Since the configuration is configured to guarantee access to the area and to remember whether or not there is an access to the excess logical area, the frequency of determining whether or not physical storage is allocated can be reduced, and the processing time of the main process can be reduced without increasing the processing time. This provides an excellent effect in that dynamic physical storage allocation processing can be realized quickly and easily.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing a memory control device as an embodiment of the present invention, FIG. 2 is a configuration diagram showing one entry of an address translation table in the memory control device of FIG. 1, and FIG. , FIG. 4 is a block diagram showing a part of the arithmetic processing unit of a computer that implements the dynamic allocation method of physical storage, and FIG. 5 is a block diagram showing part of the microinstructions in the computer shown in FIG. 4, FIG. 6 is a flowchart showing a microprogram for performing stack processing in the computer shown in FIG. 4, and FIG.
8 is a block configuration diagram showing a conventional memory control device, FIG. 8 is a configuration diagram showing one entry of the address translation table in the memory control device shown in FIG. 7, and FIG. 9 is a block diagram showing a conventional memory control device shown in FIG. 6 is a flowchart showing a microprogram for performing stack processing in a computer equipped with a memory control device and equipped with the arithmetic processing unit and microinstructions shown in FIGS. 4 and 5. FIG. In the figure, 1, 3, 5, 6, 8, 9, 11,
15a to 15d, 21, 23, 24...signal lines,
2...Logical address register (LAR), 7...
Physical address register (PAR), 10...Register (D), 12...Register SP, 13...Register (C), 20...Address translation table (ATT),
20a, 20b...Flag, 20c...Field, 22...Flip-flop, 25...Stack, 25a...Normal logic area, 25b...Excess logic area, 27...Microprogram routine. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A memory device having one or more stack-like storage areas that sequentially consume continuous logical storage space, and having a method of allocating physical storage corresponding to the storage areas as necessary,
Each of the storage areas has a normal logical area of the storage area to which physical storage is normally allocated, and an excess logical area of the storage area to which extra physical storage is allocated, and this excess logical area is a discrimination mechanism disposed immediately after the normal logical area according to the consumption direction of logical storage space, and for discriminating access to the normal logical area and the excess logical area during execution of a machine instruction, and the excess logic; A storage mechanism capable of storing the occurrence of an access to the area is provided, and the execution of the instruction is not interrupted even when an access to the excess logical area occurs, and the memory is stored in the storage mechanism after the execution of the machine instruction is completed. A memory control device characterized by performing physical storage allocation processing after determining that an access to an excess logical area has occurred.