JPS62137908A - Signal delay circuit - Google Patents

Abstract

PURPOSE:To simplify remarkably the titled circuit and to reduce the cost considerably by converting an analog signal into a PWM wave, converting the wave into a 1-bit data string by means of sampling and applying digital processing to the data string. CONSTITUTION:The analog input signal is converted into a PWM wave by a PWM modulation circuit 2 and sampled at a sampling circuit 3 by using a high frequency clock B. The sampling data is written in a prescribed address of a 1-bit memory 5 and read in a buffer 6. The data read in the buffer 6 is adjusted into a prescribed amplitude by a waveform shaping circuit 7 and outputted from an output terminal 9 via an PF 8 as a delay analog signal. Through the constitution above, since the data is all 1-bit data from the output of the circuit 2 till the LPF 8, a 1-bit memory is enough for the memory and no A/D converter nor D/A converter is required, the circuit is simplified remarkably and the cost is reduced remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to analog signal delay circuits, particularly reverberation adding devices for audio equipment and the like.

[Conventional technology]

Conventionally, the delay circuit described above uses an analog signal as it is,
There are two types: one in which the signal is delayed using a delay line or a BBD (Bucket Bridge Device), and the other type in which the signal is first A/D converted, delayed by a multi-focus memory, and then D/A converted.

[Problem that the invention seeks to solve]

Digital delay circuits are particularly promising because they can provide a variety of delay characteristics, but they require expensive components such as A/D converters, D/A converters, and large-capacity memory (multiple vias), resulting in high costs. It had the disadvantage of being expensive.

In view of the above circumstances, an object of the present invention is to convert analog signals into
Analog signals that can be converted to WM (pulse width modulation) waves and processed, eliminating the need for A/D converters and D/A converters, and can be used as memory with 1-bit memory, which can significantly reduce costs. The purpose of this invention is to provide a delay circuit.

[Means for solving problems]

The present invention inputs an analog signal, converts it into a PWM wave, samples it with a high frequency clock, writes the sampled data to a series of addresses in a memory sequentially at the clock cycle, and starts from an address having a certain offset to the address. The previously written data is successively written at the clock cycle,
By passing it through a low-pass filter, an analog signal having a predetermined amount of delay is obtained for the input (No. 3).

[Effect]

Converts the analog signal into a PWM wave, samples it with a high frequency clock, and converts it into 1-bit digital data.
Delayed data is obtained using 1-bit memory. A/
Since a D converter is not used, there is no need to worry about conversion speed, so sampling can be performed at a high frequency.

Therefore, the low-pass filter for converting into an analog signal may be extremely simple.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. Figure 1 shows the overall configuration block diagram, and Figure 2 shows the P
A WM modulation circuit is shown.

The analog input signal is converted into a PWM wave by the PWM modulation circuit 2. Frequency f of clock A of PWM modulation circuit 2. For example, take the number 11) to K IIZ and l OOKtlz. The PWM wave output 2a is 1. At tombling rotation 3, the frequency f1. For example, the black of l Q M tlz is sampled by [3]. This sampling data is written to a predetermined consecutive address of the 1-bit memory 5, and
S is sold to buffer 6. The address signal is generated temporally by inputting the clock B to the address clock generation circuit 4, but the address read to the buffer 6 is an address that has a certain offset from the address to be written at that time. shall be.

The data read into the buffer 6 is adjusted to have a constant amplitude by a waveform shaping circuit 7, and then outputted from an output terminal 9 via a low-pass filter 8 as a delayed analog signal. As explained above, all data from the output of the PWM modulation circuit 2 to the low-pass filter 8 is 1-bit data.

Next, the operation of the PWM modulation circuit 2 will be explained with reference to FIG. The capacitor C is charged by the constant current source 23,
The voltage increases linearly and the switch 25 closes to generate a sawtooth voltage. It is now assumed that the switch 25 is turned off when the Q point of the flip-flop 22 is "■4".

The rise of the sawtooth wave starts when the flip-flop 22 is periodically clocked by the clock A (negative pulse) as shown in FIG. 3, and the Q point becomes "H". When the sawtooth wave voltage applied to the negative phase terminal becomes equal to and exceeds the input analog signal applied to the positive phase terminal of the comparison circuit 21, the signal 21a becomes negative and the flip-flop 2
2, and set the P point to "■1" and the Q point to "■7".

Since the Q point becomes "L", the switch 25 is closed, the sawtooth voltage becomes zero, and the output signal 21a of the comparator circuit 21 becomes "
Since this change is fast, the signal 21.a eventually appears as a pulse.The voltage at point P of the flip-flop 22 is guided to the next stage as a PWM wave output. However, for convenience of explanation, the DC bias voltage is set to zero.

Note that since the PWM wave is extracted from point P, the phase of the PWM wave is reversed with respect to the input signal, but this does not pose a particular problem as a delay circuit for audio equipment. If this becomes a problem, the signal can be extracted from the Q point or the phase can be inverted in a subsequent stage.

Fourth application of the signal delay circuit of the present invention to audio equipment
5 will be explained. In both cases, the remaining addition device is used to create a delayed signal having a component equivalent to reverberation to be added to the original signal, and the single delay circuit 10 in FIG.
As a result, the delay can easily range from 10m5 to 1s. This circuit is constructed in a circular manner via a coefficient circuit 11. However, with this configuration, the reverberation effect is monotonous. On the other hand, in FIG. 5, by providing a plurality of delay circuits 12A to 12N and varying the delay time of each, various effects can be obtained. To create a circuit configuration as shown in Figure 5,
The present invention is particularly advantageous in that each delay circuit 12A-12N can be constructed in a simple manner.

〔Effect of the invention〕

As described above in detail, the present invention converts an analog signal into a digital signal and performs the 414 delay using a memory, which is similar to the delay circuit used in a conventional digital residual stone adding device. After converting into a wave, it is converted into a 1-bit data string by zumbling and digital processing is performed. Therefore, an A/D converter and a D/A converter are not required, and the circuit can be greatly simplified. Furthermore, since the memory is I-pinotomesori, an inexpensive memory may be used, especially as a large-capacity memory.

Furthermore, by setting the thumbling frequency to a sufficiently high value, a simple low-pass filter can be used to restore the analog signal, which is a great advantage.

As mentioned above, since the configuration of the signal delay circuit is simple,
With the reverberation addition device, a configuration as shown in FIG. 5 is possible to obtain a complex reverberation effect.

[Brief explanation of drawings]

Fig. 1 is a circuit block diagram of an embodiment of the present invention, Fig. 2 is a wiring diagram of a PWM modulation circuit in the embodiment, Fig. 3 is a time chart thereof, and Figs. 4 and 5 are application examples. . 2-PWM modulation circuit, 3-・sampling circuit, 4
-Address clock generation circuit, 5 memory, 6 buffer, 7 waveform shaping circuit, total low-pass filter.

Claims (1)

[Claims] After inputting an analog signal and converting it into a PWM wave, sampling it with a high frequency clock and sequentially writing the sampled data to a series of addresses in the memory at the clock cycle,
Data written first from an address having a certain offset to the address is read out sequentially at the clock cycle, and is passed through a low-pass filter to obtain an analog signal having a predetermined amount of delay with respect to the input signal. signal delay circuit.