JPH04138724A - D/a converter - Google Patents

Abstract

PURPOSE:To reduce noise by controlling a current summation type A/D converter with a gradient linear data obtained at a differential arithmetic circuit and interpolating data between adjacent sampling points corresponding to the gradient data. CONSTITUTION:When a differential arithmetic circuit 3 fetches a data (b) at a sampling point t2 from a demodulation circuit 1, the circuit 3 fetches a data (a) at a sampling point t1 at a just preceding time from a tentative hold circuit 2 simultaneously to calculate a gradient [(b-a)/(t2-t1)] and the polarity of the gradient based on a difference (b-a) of both the data. Then a digital data of each point on a straight line l1 from the data (a) to the data (b) based on the calculation. Then the current summation type A/D converter 4 controls a sum current in response to the consecutive data change to apply A/D conversion to the data.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a D/A converter that converts a digital numerical data string into an analog signal.

[Conventional technology]

A D/A converter is used to reproduce digitized audio data, for example, to reproduce compact discs, digital audio chips, and PCM audio in satellite broadcasting. At this time, in order to reduce quantization noise caused by the square wave included in the reproduced waveform, oversampling processing is conventionally performed in which sampling processing is performed at a frequency four times or eight times the sampling frequency. For example, Fig. 8 shows the original signal waveform A and the waveform B after D/A conversion when the oversampling ratio is 1, and Fig. 9 shows the original signal waveform A and D/D when the oversampling ratio is 4.
It is a figure which shows the waveform B after A conversion. Furthermore, FIG. 10 is an explanatory diagram of the D/A conversion method,
The curve a-b-c shows the original signal waveform to be reproduced. For example, the amplitude a at sampling time t1 is held at a constant value until the next sampling time t2, so the output waveform is a collection of rectangular waves. Become something. In other words, if the sampling points are increased, preferably infinite, the waveform will match the original waveform. Based on this principle, conventional methods use high-order oversampling to shorten the apparent data sampling interval, make the square wave component finer, and move the quantization noise component to a higher frequency band. This makes it easy to remove noise.

[Problem to be solved by the invention]

However, increasing the level of oversampling requires increasing the operating speed of the circuit. For example, doubling the oversampling requires doubling the circuit speed. However, this generates internal noise in the circuit, creating a trade-off relationship with quantization noise reduction. The present invention solves these problems and provides a D/R with reduced quantization noise without increasing the oversampling rate.
The purpose of the present invention is to provide an A converter.

[Means to solve the problem]

To this end, the present invention provides a difference calculation circuit that calculates the difference between digital data of a certain sampling point and digital data of the next sampling point and calculates slope data between both sampling points, and The present invention is configured to include a current addition type D/A conversion circuit whose addition current value is controlled by digital data.

[Effect]

Since the current addition type D/A conversion circuit is controlled by the slope linear data obtained in the difference calculation circuit, the data between adjacent sampling points is linearly interpolated according to the slope data, and the data is not a rectangular wave but a linear wave. This allows you to obtain a more accurate waveform and reduce noise.

【Example】

Examples of the present invention will be described below. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. 1 is a data demodulation circuit that edits digital data in different data formats depending on sources such as satellite broadcasting and CDs into common digital data of specific bits; 2 is a data demodulation circuit 1 obtained by the demodulation circuit 1;
3 is a temporary holding circuit that temporarily holds digital data of A difference calculation circuit that outputs continuously changing slope digital data and also outputs sign data indicating the direction of the slope; 4 is a current addition type D that changes the added current value according to the slope digital data output from the difference calculation circuit 3; The /A conversion circuit 5 is an LPF that removes high frequency components from the signal output from the current addition type D/A conversion circuit 4. As a result, in this example, as shown in FIG. 2, for example,
If the data (amplitude) at a certain sampling point t1 is a and the data at the next sampling point t2 is b, in the difference calculation circuit 3, when taking in the data b at the sampling point t2 from the data demodulation circuit 1, The data a at the sampling point t1 is simultaneously taken in from the temporary holding circuit 2, and the slope [(b
-a)/(t2-tl)] and the sign (upward or downward direction) of its slope is calculated. Based on this calculation, digital data (gradient digital data) of each point on the straight line 11 from data a to data b is obtained. The resolution of the data at each point increases as the number of divisions between sampling points t1 and t2 increases. In reality, data on the straight line Ill is created almost continuously and output continuously. As a result, the obtained straight line l
The slope of the data may change each time the sampling point changes, but the data changes continuously between adjacent sampling points. Then, according to this continuous data change, the current adding type D
The addition current is controlled by the /A conversion circuit 4 and D/A conversion is performed. FIG. 3 is a diagram showing a specific circuit of this current addition type D/A conversion circuit 4. In FIG. Here, an example of 8° bits is shown. 11 to 18 are digital data input terminals. On the positive side (left side), the gates are input to Nantes gates 19 to 26 whose gates are controlled by a sine signal, and on the negative side (right side), a signal obtained by inverting the sine signal with an inverter 27 is input. The signals are input via inverters 36 to 43 to NOR gates 28 to 35 whose gates are controlled. 44 to 51 are PMO8Ts (P-channel MO8FETs) whose sources are commonly connected to the power supply VA+, and whose drains are commonly connected to the output terminal 52. Also, 53 to 60 are NMO8T (N channel MO8F
ET), whose sources are commonly connected to the power supply VA-, and whose drains are commonly connected to the output terminal 52. 61 is a capacitor, 62 is a resistor, and constitutes an output circuit. And PMOS T44-51 are PMOS T4
4 to PMO8T51, its conduction resistance is PMO
If 8T44 is R, PMO8T45 is (-(7)R
/2, PMO8T46 is R/4, PMO5T47 is R/
8. PMO8T48 is R/16, PMO8T49 is R/
32, PMOS T 50ka R/64, PMO8T51
becomes R/128. In other words, the current value is 1x, 2x, 4
The weights are set to be 1x, 8x, 16x, 32x, 64x, and 128x. This is the other NMO3T
The same applies to 53-60. In this D/A conversion circuit 4, when positive digital data is input to the input terminals 11 to 18, the sine signal is at level H.
Then, Nantes gates 19 to 26 open and input terminal 1
The output of the gate corresponding to level H of the digital data manually input to 1 to 18 becomes level L, and PMO3T44
The corresponding one of ~51 becomes conductive, and then the power supply VA+
The currents discharged from the PMO 8T via the conductive PMO 8T are added, converted into a voltage signal by a capacitor 61 and a resistor 62, and outputted to an output terminal 52 as a positive voltage of a predetermined value. When negative digital data is input to the input terminals 11 to 18, the sine signal becomes level L, and the NOR gates 28 to 3
5 is opened, and the output of the gate corresponding to level L of the digital data input to input terminals 11 to 18 becomes level H.
Then, the corresponding ones of NMOS T53 to T60 conduct, and the current sucked through NMO8T, which is conductive to the power supply VA- at that time, is added, and the capacitor 61
, is converted into a voltage signal by the resistor 62, and taken out as a negative voltage of a predetermined value at the output terminal 52. From the above, from point a to point b in FIG. It is obtained by continuously changing the digital data DO to D7. 4 to 7 are diagrams showing waveforms of experimental results of this embodiment and the conventional example. FIG. 4 shows the original waveform, and based on the digital data obtained by A/D converting this, the D/A converted waveforms are shown in FIGS. 5 to 7. First, FIG. 5 is a diagram showing the results of this example, (a)
is a waveform diagram of the D/A conversion, and (b) is a waveform diagram showing noise components. On the other hand, FIG. 6 is a diagram showing a conventional example in which the oversampling link ratio is 1, in which (a) is a D/A conversion waveform diagram, and (b) is a waveform diagram showing noise components. Here, the level of the noise component has increased. FIG. 7 is a diagram showing a conventional case where the oversampling ratio is 4 times, in which (a) is a D/A conversion waveform diagram, and (b) is a waveform diagram showing its noise component. In this example as well, the level of the noise component is high. As described above, it can be seen that the D/A conversion of this embodiment significantly reduces the noise component level. In the above-described embodiment, a case has been described in which only data of one sampling point is held in the temporary holding circuit 2, but it is also possible to hold data of two or more adjacent sampling points. In this case, data interpolation between the current sampling point and the sampling point immediately before it can be predicted from the data of multiple past sampling points and can be performed using a curve instead of a straight line, making it possible to approximate the waveform of the original signal. can. In addition, in the above embodiment, a case was explained in which a signal that changes in the positive direction and a negative direction is handled, but in the case of a signal that changes only on the -blade side, PMO8T44~51 or NMO3T53~
60 (gates 19 to 26, 28 to 35, inverters 27, 36 to 43, etc. are not required.) [Effects of the Invention] As described above, according to the present invention, the sampling date - dusk can be made linear. Since interpolation is performed, there is an advantage that sufficient noise reduction can be achieved without increasing the oversampling ratio.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a D/A converter according to an embodiment of the present invention, Fig. 2 is an explanatory diagram of the D/A conversion function of the present invention, and Fig. 3 is a circuit diagram of a current addition type D/A converter circuit. Figure 4 is a waveform diagram of the original signal before A/D conversion, Figure 5 (Jl) is a waveform diagram after A/D conversion of the original signal in Figure 4, and (b
) is the noise waveform diagram at that time, Figure 6(a) is the waveform diagram obtained by A/D converting the original signal in Figure 4 using the conventional method with an oversampling ratio of 1, and -) is the waveform diagram obtained by A/D converting the original signal in Figure 4. The noise waveform diagram at that time, Figure 7 (Jl), is the original signal of Figure 4, which is A/D.
The converted waveform is D/A converted using the conventional method with an oversampling ratio of 4. (b) is a noise waveform diagram at that time. Fig. 8 is an explanatory diagram of conventional D/A conversion. Fig. 9 and 10th
The figure is an explanatory diagram of D/A conversion using conventional oversampling. Agent Patent Attorney Tsunema Nagao Figure 1 Figure 2! ime Figure 3 ttme Figure 4 Figure (a) f 2f 3f 14f. Sfo6f. Figure 6 (a) ime (b) fo2fo3foshunfo5fo6[. Figure 7 (a) -t i me 11fll

Claims (1)

[Claims] (1), D/ that converts digital data to analog signals
In the A converter, there is a difference calculation circuit that calculates the difference between the digital data of a certain sampling point and the digital data of the next sampling point and calculates the slope data between both sampling points, and the digital data obtained by the calculation circuit. A D/A converter comprising: a current addition type D/A conversion circuit in which an addition current value is controlled by.