JPS62137871A - Manufacture of compound semiconductor device - Google Patents

Manufacture of compound semiconductor device

Info

Publication number
JPS62137871A
JPS62137871A JP27961985A JP27961985A JPS62137871A JP S62137871 A JPS62137871 A JP S62137871A JP 27961985 A JP27961985 A JP 27961985A JP 27961985 A JP27961985 A JP 27961985A JP S62137871 A JPS62137871 A JP S62137871A
Authority
JP
Japan
Prior art keywords
crystal
substrate
excimer laser
compound semiconductor
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27961985A
Other languages
Japanese (ja)
Inventor
Hiroshi Komatsu
博志 小松
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP27961985A priority Critical patent/JPS62137871A/en
Publication of JPS62137871A publication Critical patent/JPS62137871A/en
Pending legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To uniformly manufacture a field effect transistor (FET) having the desired characteristics and the degree of integration with excellent productivity by a method wherein an excimer laser beam is made to irradiate on the surface of a substrate while an epitaxial process is being performed on GaAs crystal. CONSTITUTION:A completely cleaned semiinsulative GaAs substrate 301 is prepared and it is set in a metal oxide chemical vapor deposition (MOCVD) device. The set substrate is heated up and, at the same time, AsH3 gas is allowed to flow. Then, an excimer laser 303, which is patternized by a metal mask 303 and the like in advance, is made to irradiate on the surface of the substrate, and the growth of crystal is started immediately after said irradiation by passing TMG into the MOCVD device. After lapse of the desired time, first, the flow of TMG is stopped, and then the irradiation of the excimer laser is stopped. After the temperature of the substrate has been dropped completely, the substrate is picked out from the MOCVD device, an etching is performed, an ohmic electrode 309 is formed, and Schottky electrode 310 is formed. This invention can be applied not only to the GaAs crystal but also to InP, InGaAs and the like. Also, this invention can be used not only for the manufacture of III-V compound semiconductor but also for the growth of crystal such as a II-VI group, a IV-VI group, a IV-IV group, chalcopyrite and the like.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、例えばひ化ガリウム結晶(以下GaAθ結晶
という)から成る金属−半導体電界効果型トランジスタ
(以下MES?FXTという)のしきい値電圧や伝導型
等の特性を、GaA3結晶薄膜の成長中に結晶面内で制
御できることを特徴とする化合物半導体装置の製造方法
に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the threshold voltage of a metal-semiconductor field effect transistor (hereinafter referred to as MES?FXT) made of, for example, a gallium arsenide crystal (hereinafter referred to as GaAθ crystal). The present invention relates to a method for manufacturing a compound semiconductor device, which is characterized in that characteristics such as conductivity and conduction type can be controlled within the crystal plane during growth of a GaA3 crystal thin film.

〔発明の概要〕[Summary of the invention]

本発明は、化合物半導体結晶から成るMISFET等の
化合物半導体装置の製造方法において、おもにPETの
チャネルに用いる結晶薄膜のエピタキシャル成長工程中
に紫外光を照射することにより、基板表面上の紫外光に
よる光化学反応によって結晶薄膜中のキャリア濃度や伝
導型を制御し、基板面内にエンハンスメント型およびデ
ィプレッション型などのMESFETを高密度に製造で
きることを可能にしたものである。
In the method of manufacturing a compound semiconductor device such as a MISFET made of a compound semiconductor crystal, the present invention mainly involves irradiating ultraviolet light during the epitaxial growth process of a crystal thin film used for a PET channel, thereby producing a photochemical reaction caused by the ultraviolet light on the substrate surface. By controlling the carrier concentration and conductivity type in the crystal thin film, it has become possible to manufacture enhancement type and depletion type MESFETs at high density within the substrate surface.

〔従来の技術〕[Conventional technology]

高速デバイスとして注目されるGaAsMKSFITは
シリコンLSIで培った集積技術を駆使して16にビッ
ト以上の工O化が進められている、GaAsFETには
シリコンFITに用いられているような良質のゲート絶
縁膜が得られないため、金属−半導体のショットキー接
触を利用したMis型のものが用いられている。MES
型FETの場合、ショットキ障壁は高々数エレクトロン
ボルトのため、ゲート電極には数ボルト以上の電圧を印
加することはできず、したがって集積回路内で特性の均
一な1!’ETを作製する場合には、FITのしきい値
電圧〜を均一性良く制御しなければならない。また論理
回路を組むには、ディプレッleaン型とエンハンスメ
ント型の二種類のしきい値電圧を持つPETが必要とな
る。さらに高集積化した場合でも熱の発生を防ぐために
、FICTのチャネルの伝導型がP型のものと2型のも
のを用い相補型としなければならない。
GaAsMKSFIT, which is attracting attention as a high-speed device, is being developed to 16 bits or more by making full use of the integration technology cultivated in silicon LSI.GaAsFET uses high-quality gate insulating films like those used in silicon FIT Since this cannot be obtained, a Mis type that utilizes a metal-semiconductor Schottky contact is used. MES
In the case of type FETs, the Schottky barrier is at most a few electron volts, so a voltage of more than a few volts cannot be applied to the gate electrode, and therefore the characteristics are uniform within the integrated circuit. 'When manufacturing an ET, the threshold voltage ~ of the FIT must be controlled with good uniformity. Furthermore, in order to assemble a logic circuit, PETs having two types of threshold voltages, a depletion type and an enhancement type, are required. Furthermore, in order to prevent heat generation even in the case of high integration, the conductivity types of the FICT channels must be P-type and 2-type to be complementary.

従来は、このようf:rG a A s F E Tの
しきい値7u圧や伝導型の制御にイオン注入法という技
術を用いPETのチャネル部およびその周辺部にドナや
アクセプタとなり得る元素を打ち込み、各1i’ETの
チャネルの特性を制御していた。
Conventionally, to control the threshold 7u pressure and conduction type of f:rGaAs FET, a technique called ion implantation was used to implant elements that could become donors or acceptors into the PET channel region and its surroundings. , controlled the channel characteristics of each 1i'ET.

〔発明が解決しようとする問題点及び目的〕ところが、
このイオン注入法は、注入した原子が結晶内部に欠陥を
発生させることや、注入した原子の深さ方向の分布にば
らつきがあることから、結晶性や均一性に問題点がある
。またイオン注入した原子の活性化のために、ある程度
長い時間の熱処理工程が必要であることや、各FET間
にしきい値電圧の差を持たせるのに別々にイオン注入す
ることや、装置の取り扱いに時間がかかることから、生
産性が非常に悪くなるという問題点があった。さらに、
化合物半導体薄膜をエピタキシャル成長した後に、いっ
たん大気にさらす工程を含むため、半導体の特性を劣化
させてしまうという問題点があった。
[Problems and objectives to be solved by the invention] However,
This ion implantation method has problems with crystallinity and uniformity because the implanted atoms generate defects inside the crystal and the distribution of the implanted atoms in the depth direction varies. In addition, in order to activate the ion-implanted atoms, a heat treatment process that takes a long time is necessary, and in order to create a difference in threshold voltage between each FET, ions must be implanted separately, and equipment handling is required. There was a problem in that productivity was extremely low because it took a long time. moreover,
This method involves the step of exposing the compound semiconductor thin film to the atmosphere after it has been epitaxially grown, which has the problem of degrading the characteristics of the semiconductor.

そこで本発明はこのような問題点を解決するためのもの
で、その目的とするところは、所望の特性と集積度を持
ったFETを、均一に生産性良く製造できる方法を提供
するところにある。
The present invention is intended to solve these problems, and its purpose is to provide a method for manufacturing FETs with desired characteristics and degree of integration uniformly and with high productivity. .

〔作用〕[Effect]

有機金属熱分解結晶成長法(以下MOOVD法という)
によるGaA3結晶のエピタキシャル工程中に、基板表
面にエキシマレーザを照射することにより、エキシマレ
ーザを照射した部分のエピタキシャル層の電気的特性が
変化する。これは、気相原料である金属のアルキル化合
物や水素化物中に含まれる熱によっては分解されにくい
不純物原料が、エキシマレーザによって容易に分解され
ることと、結晶中への不純物のとり込みがエキシマレー
ザによって促進又は抑制されることから生じる結果とし
て、結晶中の不純物濃度がエキシマレーザ照射部のみ異
なることによる。エキシマレーザは結晶成長過程で照射
されるので、不純物濃度の膜厚方向の分布が均一になり
、結晶性も良い。また、エキシマレーザの波長や強度を
変えることで、とり込まれる不純物の種類や濃度を変え
ることができる。
Metal-organic pyrolysis crystal growth method (hereinafter referred to as MOOVD method)
By irradiating the substrate surface with an excimer laser during the epitaxial process of GaA3 crystal, the electrical characteristics of the epitaxial layer in the portion irradiated with the excimer laser change. This is because impurity raw materials that are difficult to decompose by heat contained in metal alkyl compounds and hydrides, which are gas phase raw materials, are easily decomposed by excimer laser, and impurities are not taken into crystals by excimer laser. As a result of being promoted or suppressed by the laser, the impurity concentration in the crystal differs only in the excimer laser irradiated area. Since the excimer laser is irradiated during the crystal growth process, the impurity concentration distribution in the film thickness direction is uniform and the crystallinity is good. Furthermore, by changing the wavelength and intensity of the excimer laser, the type and concentration of impurities that are taken in can be changed.

〔実施例〕〔Example〕

トリメチルガリウム(TMC)と略す)とアルシン(A
s H3と略す)を原料に用いたMOCjVD法で成長
したGaAθ結晶中のキャリア濃度のAeH,/TMG
モル比依存性を第1図に示す。図中の実線は通常の熱分
解MOCVD法により成長した結晶のものを、点線はこ
の通常の熱分解MOOVD法の結晶成長過程中に終始A
rFエキシマレーザを1.5W/、−jの強度で照射し
たときのものをそれぞれ示している。エキシマレーザ照
射により不純物の結晶中へのとり込み率が異なるため、
曲線が左側にシフトしている。AeH,/TMGモル比
が図中のA点のとき、エキシマレーザを照射した部分は
電子濃度が大きい。第2図はエキシマレーザ強度とキャ
リア濃度の変化分の関係を示している。キャリア濃度の
変化分は、結晶中のキャリア濃度をエキシマレーザを照
射していない結晶のキャリア濃度で割り算したものであ
る。エキシマレーザ強度を増加した場合、伝導型がn型
のときは電子濃度は増加し、伝導型がP型のときは正孔
濃度は減少する。
trimethylgallium (TMC)) and arsine (A
AeH,/TMG of the carrier concentration in the GaAθ crystal grown by the MOCjVD method using sH3 as the raw material
The molar ratio dependence is shown in FIG. The solid line in the figure shows the crystal grown by the normal pyrolytic MOCVD method, and the dotted line shows the crystal grown by the normal pyrolytic MOOVD method.
The results are shown when the rF excimer laser is irradiated with an intensity of 1.5 W/, -j, respectively. Because the rate of impurity incorporation into the crystal varies depending on excimer laser irradiation,
The curve has shifted to the left. When the AeH,/TMG molar ratio is at point A in the figure, the electron concentration is high in the part irradiated with the excimer laser. FIG. 2 shows the relationship between the excimer laser intensity and the change in carrier concentration. The change in carrier concentration is calculated by dividing the carrier concentration in the crystal by the carrier concentration in the crystal not irradiated with excimer laser. When the excimer laser intensity is increased, the electron concentration increases when the conductivity type is n-type, and the hole concentration decreases when the conductivity type is p-type.

これらのエキシマレーザ照射の効果を利用した本発明の
一実施例を第5図(α)および第3図(b)に示す。G
aAsIFKTの製造工程を説明する。まず充分に洗浄
された半絶縁性GaA3基板を準備し、MOOVD装置
内にセットする。セットした基板を加熱するとともに、
AsH,ガスを流す。次に予め金属マスク等によってパ
ターン化されたエキシマレーザを基板表面上に照射し、
その直後にTMGをMOOVD装置内に流し結晶成長を
開始する。所望の時間経過の後に、まずTMGを流すの
をやめ、次にエキシマレーザの照射分圧める。充分に基
板温度降下後、基板を装置外部に出して、エツチング、
オーミック電極形成およびショットキ電極を形成して完
了である。第S図(α)に結晶成長途中の半導体断面の
概略図を示す。501は半絶縁性GaA3結晶基板であ
る。
An embodiment of the present invention utilizing these effects of excimer laser irradiation is shown in FIG. 5(α) and FIG. 3(b). G
The manufacturing process of aAsIFKT will be explained. First, a sufficiently cleaned semi-insulating GaA3 substrate is prepared and set in the MOOVD apparatus. While heating the set board,
Flow AsH gas. Next, an excimer laser patterned in advance using a metal mask or the like is irradiated onto the substrate surface.
Immediately after that, TMG is poured into the MOOVD apparatus and crystal growth is started. After a desired time has elapsed, the flow of TMG is first stopped, and then the irradiation partial pressure of the excimer laser is reduced. After the substrate temperature has dropped sufficiently, the substrate is taken out of the equipment and etched.
Formation of ohmic electrodes and Schottky electrodes completes the process. FIG. S (α) shows a schematic cross-section of a semiconductor during crystal growth. 501 is a semi-insulating GaA3 crystal substrate.

502はエキシマレーザをパターン化するための金属マ
スクである。303は前記の金属マスクによってパター
ン化されたエキシマレーザである。
502 is a metal mask for patterning the excimer laser. 303 is an excimer laser patterned by the metal mask described above.

304は通常のMO(!VD法によって形成された5E
GaAθ結晶である。305はエキシマレーザ照射した
部分で、前記n−形GaAs結晶より電子濃度の高い−
形GaA3結晶である。
304 is a normal MO (!5E formed by the VD method)
It is a GaAθ crystal. 305 is a part irradiated with excimer laser, which has a higher electron concentration than the n-type GaAs crystal.
It is a type GaA3 crystal.

第5図<b>はしきい値電圧の異なる2種類のFETを
同一基板上に形成した際の完成構造図である。306は
301と同じく半絶縁性GaA3基板、507は304
と同じくn−形GaAS結晶、308は505と同じく
九 形GaAB結晶である。509は各GaAs結晶層
がらオーミックコンタクトを取るための金属で、この場
合にはA u −G e / N iを用いた。5o9
はPETのソースおよびドレインに当たる。510はゲ
ート金fm(Au )で307または508のGaAs
結晶とシッットキ接触している。このようにして製造し
た2161類のnナヤネルGaAs?ETのVU −よ
り特性を第4図に示す。エキシマレーザご照射しない5
−形GaA3結晶を用いたIPETはエンハンスメント
型であったのに対し、エキシマレーザ照射した外 形G
aAs結晶のPETはディプレッシヲン型となった。
FIG. 5<b> is a diagram of a completed structure when two types of FETs having different threshold voltages are formed on the same substrate. 306 is a semi-insulating GaA3 substrate like 301, 507 is 304
Similarly to 505, 308 is an n-type GaAS crystal, and like 505, it is a nine-type GaAB crystal. 509 is a metal for making ohmic contact with each GaAs crystal layer, and in this case, Au-Ge/Ni was used. 5o9
correspond to the source and drain of PET. 510 is gate gold fm (Au) and 307 or 508 GaAs
It is in direct contact with the crystal. The 2161 class n-nayanel GaAs produced in this way? Figure 4 shows the characteristics from VU- of ET. Do not irradiate with excimer laser 5
IPET using - type GaA3 crystal was an enhancement type, whereas external type G with excimer laser irradiation
The aAs crystal PET has become a depression type.

本発明はGaAs結晶系だけでなく、In2系やInG
aAs糸などにも応用できる。またm −■族化合物半
導体の製造だけでなく、n−VI族。
The present invention is applicable not only to GaAs crystal system but also to In2 system and InG crystal system.
It can also be applied to aAs thread. In addition to manufacturing m-■ group compound semiconductors, we also manufacture n-VI group compound semiconductors.

■−VI族、IV−tV族、カルコバイライト系などの
結晶成長に応用できる。本実施例では結晶成長方法とし
て、MOOVD法をとり上げたが、気相成長であるMO
MBK法、一般のVPE法および減圧OV D法に応用
が可能である。エキシマレーザの波長としてArIFの
193mmを用いたが、原料ガスの分解を選択的に行な
うことのできるAr、Kr、Xe系フロライドおよびク
ロライドをエキシマレーザの封入ガスとして用いること
が可能である。
■Applicable to crystal growth of group VI, group IV-tV, chalcobyrite, etc. In this example, the MOOVD method was used as a crystal growth method, but MOOVD method, which is a vapor phase growth method, was used.
It can be applied to the MBK method, general VPE method, and reduced pressure OVD method. Although 193 mm of ArIF was used as the wavelength of the excimer laser, it is possible to use Ar, Kr, and Xe-based fluoride and chloride, which can selectively decompose the source gas, as the filler gas of the excimer laser.

〔発明の効果〕〔Effect of the invention〕

本発明の効果として次のような事項が上げられる。 The effects of the present invention include the following.

(1)  結晶成長過程で不純物ドーピングを行なえる
ので結晶性が良く均一な膜質の結晶が得られる。
(1) Since impurity doping can be performed during the crystal growth process, a crystal with good crystallinity and uniform film quality can be obtained.

(2)  結晶成長工程中に同時にしきし)値や伝導型
の制御が行なえるので生産性が良く、装置的に安価にで
きる。
(2) Since the crystal value and conductivity type can be controlled simultaneously during the crystal growth process, productivity is high and equipment can be inexpensive.

(3)  エキシマレーザを使用するので、光の強度が
強く、平行光であるから微細/ぜターンにも有効である
(3) Since an excimer laser is used, the intensity of the light is strong, and since it is parallel light, it is effective for fine/zetaturns.

(4) エキシマレーザの強度を変えることで、しきい
値電圧を自由に制御することができる。
(4) The threshold voltage can be freely controlled by changing the intensity of the excimer laser.

(5)  結晶を大気にさらす工程が減るので特性の優
れたデバイスを作製できる。
(5) Devices with superior characteristics can be manufactured because the number of steps in which the crystal is exposed to the atmosphere is reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はMOC!VD法により成長したGaAl3結晶
中のキャリア濃度の(ASH,)/CTMG)  モル
比依存性を示したグラフである。実線がエキシマレーザ
照射しない部分、点線がエキシマレーザ照射した部分の
特性である。 第2図はエキシマレーザ強度とキャリア濃度の変化分の
関係を示したグラフである。201力1型の場合、20
2がP型の場合である。 第3図は本発明により製作したFF1T構造の概略図で
、第3図(α)はその結晶成長途中の断面図、(b)は
完成構造の断面図である。。 301.306・・・・・・半絶縁性GaAθ結晶基板
302・・・・・・金属マスク 503・・・・・・エキシマレーザ 304 、307==ts−形GaAe結晶305 、
308−=s  形GaAs結晶509・・・・・・オ
ーミック電極(ソース、ドレイン510・・・・・・シ
ョットキ電極(ゲート)第4図は製造したGaAsME
S?ETのゲート%ニードレイン電流特性である。40
1がエキシマレーザを照射しない?]lCTの特性、4
02が照射したFETの特性図である。 以  上 出願人 セイコーエプソン株式会社 第1図 工叛ンマし−IT”J’史iビ〜刺ヱ」υ支ハ慢」Vか
ハFJAI〜112゛ラフ第2図 8へへ3d外中^断山図 第3図(久) 光入講迂/S前闇凹 箪 2 FW  <F、; デート”電)L     V@− ’!i1し+5Cra八s HE5FETnVc、−工
o *t)I−’i第4図
Figure 1 is MOC! 2 is a graph showing the dependence of the carrier concentration in a GaAl3 crystal grown by the VD method on the (ASH,)/CTMG) molar ratio. The solid line shows the characteristics of the part not irradiated with the excimer laser, and the dotted line shows the characteristics of the part irradiated with the excimer laser. FIG. 2 is a graph showing the relationship between excimer laser intensity and carrier concentration change. 201 force type 1, 20
2 is the P type. FIG. 3 is a schematic diagram of the FF1T structure manufactured according to the present invention, FIG. 3 (α) is a cross-sectional view during crystal growth, and FIG. 3 (b) is a cross-sectional view of the completed structure. . 301.306...Semi-insulating GaAθ crystal substrate 302...Metal mask 503...Excimer laser 304, 307==ts-type GaAe crystal 305,
308-=s type GaAs crystal 509...Ohmic electrode (source, drain 510...Schottky electrode (gate)) Figure 4 shows the manufactured GaAsME
S? This is the gate % needle drain current characteristic of ET. 40
1 does not irradiate excimer laser? ]Characteristics of lCT, 4
02 is a characteristic diagram of the FET irradiated. Applicant Seiko Epson Co., Ltd. Figure 1 - IT ``J' History i Bi ~ String'' υ Support arrogant'' Mountain map 3rd figure (Ku) Light entrance lecture round/S front darkness concave 2 FW <F,; Date "den) L V@- '!i1shi+5Cra8s HE5FETnVc, -ko *t)I-' iFigure 4

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板上に化合物半導体薄膜を少なくとも一
層以上積層して成る化合物半導体装置の製造方法におい
て、該化合物半導体薄膜のエピタキシャル成長中に、該
半導体基板の表面に紫外光を照射する工程を含み、該紫
外光を照射した領域の該化合物半導体構膜にn型ディプ
レッション電界効果トランジスタを、該紫外光を照射し
ない領域の該化合物半導体薄膜にn型エンハンスメント
電界効果トランジスタをそれぞれ形成する工程からなる
ことを特徴とする化合物半導体装置の製造方法。
(1) A method for manufacturing a compound semiconductor device comprising stacking at least one compound semiconductor thin film on a semiconductor substrate, including the step of irradiating the surface of the semiconductor substrate with ultraviolet light during epitaxial growth of the compound semiconductor thin film, The step of forming an n-type depletion field effect transistor on the compound semiconductor thin film in the region irradiated with the ultraviolet light, and forming an n-type enhancement field effect transistor in the compound semiconductor thin film in the region not irradiated with the ultraviolet light. A method for manufacturing a compound semiconductor device characterized by:
(2)前記エピタキシャル成長の原料として、金属のア
ルキル化合物および水系化物を使用し、前記紫外光とし
てエキシマレーザを使用することを特徴とする特許請求
の範囲第1項に記載の化合物半導体装置の製造方法。
(2) The method for manufacturing a compound semiconductor device according to claim 1, characterized in that an alkyl compound and an aqueous compound of metal are used as raw materials for the epitaxial growth, and an excimer laser is used as the ultraviolet light. .
JP27961985A 1985-12-12 1985-12-12 Manufacture of compound semiconductor device Pending JPS62137871A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27961985A JPS62137871A (en) 1985-12-12 1985-12-12 Manufacture of compound semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27961985A JPS62137871A (en) 1985-12-12 1985-12-12 Manufacture of compound semiconductor device

Publications (1)

Publication Number Publication Date
JPS62137871A true JPS62137871A (en) 1987-06-20

Family

ID=17613502

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27961985A Pending JPS62137871A (en) 1985-12-12 1985-12-12 Manufacture of compound semiconductor device

Country Status (1)

Country Link
JP (1) JPS62137871A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9330908B2 (en) 2013-06-25 2016-05-03 Globalfoundries Inc. Semiconductor structure with aspect ratio trapping capabilities
US9349809B1 (en) 2014-11-14 2016-05-24 International Business Machines Corporation Aspect ratio trapping and lattice engineering for III/V semiconductors

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9330908B2 (en) 2013-06-25 2016-05-03 Globalfoundries Inc. Semiconductor structure with aspect ratio trapping capabilities
US9349809B1 (en) 2014-11-14 2016-05-24 International Business Machines Corporation Aspect ratio trapping and lattice engineering for III/V semiconductors
US9627491B2 (en) 2014-11-14 2017-04-18 International Business Machines Corporation Aspect ratio trapping and lattice engineering for III/V semiconductors

Similar Documents

Publication Publication Date Title
EP0165798B1 (en) Semiconductor device comprising n-channel and p-channel transistors and production method
JPH01502379A (en) Low leakage CMOS/insulating substrate device and its manufacturing method
US5532184A (en) Method of fabricating a semiconductor device using quantum dots or wires
JPH0259624B2 (en)
JPH0324782B2 (en)
JPS6086872A (en) Semiconductor device
JPS62137871A (en) Manufacture of compound semiconductor device
JPS5932173A (en) Manufacture of field effect transistor
JPH07111976B2 (en) Method for manufacturing semiconductor device
JPH02111073A (en) Insulated gate fet and integrated circuit device thereof
JPH0212927A (en) Manufacture of mesfet
JPH0350744A (en) Manufacture of field-effect transistor
JPH09172163A (en) Manufacture of semiconductor device
JP2674560B2 (en) FET manufacturing method
JPS60136264A (en) Manufacture of semiconductor device
JP2616032B2 (en) Method for manufacturing field effect transistor
JP3024172B2 (en) Semiconductor device and manufacturing method thereof
JPH0810701B2 (en) Method for manufacturing junction field effect transistor
JP2000307100A (en) Field effect semiconductor device
JPH03280552A (en) Manufacture of field effect transistor
JPH0226781B2 (en)
JPS596054B2 (en) Method for manufacturing semiconductor devices
JPS61161770A (en) Manufacture of semiconductor device
JPH0618217B2 (en) Method for manufacturing semiconductor device
EP0149541A2 (en) GaAs integrated circuit device and method for producing it