JPS62136940A - Monitoring circuit for non-symbolized binary bit flow - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention has an input terminal and an output terminal, and the rate at which the uncoded binary bit stream carried through the elastic store is provided to the input terminal of the elastic store is determined by the elastic Different from the speed of the uncoded binary bit stream at the output terminal of the store, the elastic store has n records 1.
n bits of the binary bit stream with α position are constantly written serially to the elastic store by a write register and read serially again by a read store;
The present invention relates to a monitoring circuit in which one of the registers is stopped for a period of one bit or more depending on the storage level of an elastic store.

In a PCM multiplex transmission system, an elastic store is provided in a block converter provided at the transmitting and receiving ends. At the transmitting end, an elastic store is provided after a series arrangement of an equalizer, a regenerator, and a decoder for generating a binary output signal. This binary output signal is therefore applied to the input terminal of the elastic store. The binary output signal of the elastic store feeds the multiplexer of the transmission system. At the receiving end, the binary output signal of the demultiplexer is supplied to the input terminal of the elastic store.

The output signal of this elastic store is fed to an encoder. Such conventional devices are described in Philips Telecommunications Review, No. 38L, No. 1, 1980.
Monthly, pages 11-22.

In the PCM multiplex transmission system described above, the binary bit streams to be multiplexed, which have slightly different frequencies, are initially passed at a common high rate. For this purpose,
Each of these binary bit streams is written to the elastic store at its own clock speed and read out at a common high speed. This read clock pulse is occasionally stopped to prevent the elastic store from emptying. In this case there is no need to monitor changes in the time relationship between the incoming and outgoing binary bit streams of the elastic store. The elastic store does not monitor the binary flow as it is conveyed through the elastic store by comparing the binary input signal and the binary output signal. Furthermore, the binary bitstream is not encoded as it passes through the elastic store, so it is not possible to monitor for disturbances in the encoding rules and take advantage of the redundancy created by encoding the bitstream.

It is an object of the invention to provide a circuit arrangement for monitoring an uncoded binary bit stream passing through an elastic store.

The present invention has an input terminal and an output terminal, and the rate at which the uncoded binary bit stream conveyed through the elastic store is supplied to the input terminal of the elastic store is determined by the uncoded bit stream at the output terminal of the elastic store. In contrast to the speed of the binary bit stream, the elastic store has n storage locations, and the n bits of the binary bit stream are constantly written serially to the write register and read serially again; In the monitoring circuit, the input terminal and the output terminal of the elastic store are respectively connected to the data input terminal of the comparator; A clock output terminal of a write register controlling a memory location is also connected to a first control input terminal of the comparator to determine a write time window consisting of n bits plus the number of bit periods during which the write register is stopped. the clock output terminal of the read register corresponding to the clock output terminal of the write register is connected to the second control input terminal of the comparator, n bits and the number of bit periods during which the read register is stopped. The present invention is characterized in that a read time window consisting of the sum of the above is opened at a predetermined repetition ratio, and the comparator compares the read time window with the write time window.

The invention will be explained with reference to the drawings.

In the monitoring circuit according to the invention shown in FIG. 1, the elastic store comprises a memory l having 10 storage locations, a write counter 2 and a read counter 3. The data input signal is supplied to input terminal 5, and the data output signal is supplied to output terminal 1.
Take it out from 9. Clock input terminal 4 of write counter 2
A write clock pulse having a frequency of, for example, 139264kllz is supplied to the.

The clock input terminal 6 of the read counter 3 has, for example, 14
Provide read clock pulses at a frequency of 1248 kHz. Clock output terminals 20 to 29 of write counter 2
are connected to clock input terminals at arbitrary locations 1 and α of the elastic store 1, respectively. Elastic store 1
The data output terminals of the storage locations are connected to the data input terminals of any of the read gates 7-16, respectively. The data output terminals of read gates 7 - 16 are interconnected and connected to data output terminal 19 of elastic store 1 . Further, the data input terminals of the elastic store 1 are interconnected and connected to the data input terminal 5. The data input terminal 5 is connected to the first signal input terminal 40 of the comparison circuit 17, and the second signal input terminal 41 of this comparison circuit 17 is connected to the data output terminal 1.
Connect to 9. Clock output terminal 2 of write counter 2
0 is connected to the first control pulse input terminal 42 of the comparison circuit 17, and the second control pulse input terminal 43 of the comparison circuit 17 is connected to the clock output terminal 30 of the read counter 3. The clock output terminal 29 of the write counter 2 is connected to the third control pulse input terminal 44 of the comparison circuit 17.

The operation of the circuit shown in FIG. 1 will be explained with reference to the time sequence diagram shown in FIG. FIG. 2a shows the incoming binary bit stream applied to the data input terminal 5, and FIG. 2r shows the binary bit stream delivered from the data output terminal 19. The input terminal 4 of the write counter 2 is supplied with a write clock pulse.

For example, set the pulse repetition ratio of this write clock pulse to 1
The frequency shall be 39264kHz. Each clock output terminal 20-2
9 generates clock pulses having the shape shown in FIG. 2b, that is, clock pulses each shifted in the direction from the clock output terminal 20 to the clock output terminal 29 over a time period equal to one data bit period. These clock pulses present at the clock output terminals 20-29 are used to constantly write each package of IO data bits to a memory location in the elastic store 1. That is, for example, writing the relevant IO data bits as shown in FIG. 2a in time intervals T, .about.T4 of FIG. 2b. For example, by a clock pulse present at the clock output terminal 20,
From the time interval T1, a first data bit or logical value I is introduced into the relevant position of the elastic store 1. The clock pulse present at the clock output terminal 21 then converts the second data bit or logical value l from the time interval T.
into the relevant positions of the elastic store l, and repeat this operation. Finally, the clock pulse present at the clock output terminal 29 introduces the 10th data bit, ie the logical value 0, into the relevant location of the elastic store I.

The tarlock input terminal 6 of the read counter 3 is supplied with a read clock pulse. The pulse repetition ratio of these pulses is, for example, 141.248kllz. Each of the clock output terminals 30 to 39 receives a clock pulse having the shape shown in FIG. Generate clock pulses. In order to make the read ratio of the elastic store 1 higher than its write ratio, the read clock pulse at the clock input terminal 6 of the read counter 3 is sometimes stopped during one or more data bits so that the elastic store 1 is empty. to prevent Such a situation is illustrated in FIG. 2 at time interval T with the read clock pulse stopping for a time period of AT=3 data bits.

The ten storage locations of elastic store I are read by clock pulses available at clock output terminals 30-39. That is, the logic value 1 stored in the relevant location of the elastic store 1 is read out via the read gate 16 by means of a clock pulse available at the clock output terminal 30 . The logic value 1 stored in the relevant location of the elastic store I is then read out via the readout gate 15 by means of a clock pulse obtained at the clock output terminal 31, and the same operation is repeated. Finally, the logic value 0 stored in the relevant location of the elastic store 1 is read out via the read gate 7 by means of a clock pulse available at the clock output terminal 39 .

This results in a time interval T
1, data package 1100111100 is introduced into elastic store 1. As shown in Figures 20 and 2r, this data package is then read out again for two hours. Therefore, the data package 1100000111100 appears at the data output terminal 19. This package adds three extra logical zeros. The reason is that no proactive measures are taken for elastic store 1, so that the read crotter pulse stops for a time interval equal to three data bits. If the system is further degraded, management bits can be added in place of these three logical zeros.

Using the clock pulses obtained at the clock output terminal 20 of the write counter 2 which controls the first storage location of the elastic store 1, the write time window I is determined as shown in FIG. 2d.
(1) Open and close. This opening and closing is performed at a repetition rate of: In the above example, the write time window (1) is assumed to be 10 bits long with a repetition ratio of 40 bits.
The readout time window 0(1) is opened and closed as shown in FIG. 2e by the clock pulses obtained at the clock output terminal 30 of. This opening/closing is the writing time window! The repetition rate is the same as in case (1). In the above example, the read time window 0 (1)
Let be 13 bits long with a repetition ratio of 40 bits. The write time window 1(1) is then compared with the read time window 0(1), for example with respect to the number of edges, ie parity. In the conventional example, it was impossible to compare only odd-even cases. The reason is that the last bit is held during the time period during which the read clock pulse is wasted. In the above case, this final bit has a logic value of 0, which does not adversely affect the parity.

However, if this final bit is set to 1, the three additional bits also become 1, so the parity actually changes. However, these bits can always be set to a logical value of 0 by comparing oddness. However, in this case the time AT
The readout time window is 3 bit positions longer than the write time window because the readout connought 3 stops over =3 bit positions. During this AT stop period, the data output terminal 19 holds the logical value of the level reached immediately before the read counter 3 stopped. Therefore, there is no need to add any extra 1' part to the output signal during this time AT.

FIG. 3 shows the circuit arrangement of comparator 17 of FIG. 1.

This comparator 17 is a D-flip-flop 50.51.6
0 and 61, R3-flip-flops 54 and 57, 52.55.56.5g, 59.62 and 6
3, and these circuit elements are connected and arranged as shown in the drawing. However, when the D-flip-flop is set, a logical value of 0 is obtained at the D input terminal, and when supplying a tarok pulse to the clock input terminal CL, Q=
1, and when the flip-flop is reset, a logic value of 1 is obtained at its D input terminal and the clock signal is 1M.
It has a characteristic that Q=O when supplying a clock pulse to the child CL. Both flip-flops 50 and 51 can therefore be interconnected to form a quarter divider. This allows four phase states to be obtained when the clock pulses available at the clock output 20 of the write counter 2 are applied to the input 42 of the comparator. That is,
As shown in FIG. 2b, in the first phase state T1, Q
(50) =Q(51)=O1O2O3 phase state T2
Then Q (50) = 1, Q (51) - 0, in the third phase state T3 Q (50) = Q (51) - 1
, and in the fourth phase state T4 Q(50) = 0
, Q(51)=1 are obtained. Pulse Q (50)
and Q(51) are supplied to the input terminal of the OR gate 58. An output terminal 66 of OR gate 58 is connected to an enable input terminal of D flip-flop 60. Only when the pulse signal applied to this enable input terminal goes low (-0) will the human data signal be transferred to the D flip-flop 60 via line 40. However, this state only occurs during the first phase state T1. Other phase states T2. At T3 and T4, the logic signal obtained at the output terminal 66 of the gate 58 is at a high level (=1),
Human input data signals are therefore blocked. In the first phase, FmT+, D flip-flop 60 changes state in response to each falling edge of the human data signal. Thus, at the end of this phase state, the Q output of D flip-flop 60 will assume a logic value of 1 or 0, depending on the number of falling edges of the input data signal during the first phase state.

Flip-flop 57 in combination with two NOR gates 55 and 56 forms a logic circuit which is normally a clocked RS flip-flop. NOR gate 52
The two input terminals of the input data time window ■(1)
Two logic 0 pulses are provided during phase state T1. Therefore, only during this phase state a logic 1 signal is generated at the set input terminal S of the flip-flop 54, which is supplied to the reset input terminal R of the flip-flop 54 and also to the input terminal of the gate 55. The flip-flop 57 is set by the first clock pulse applied to the input terminal l13 of the comparator 17. A logic 0 signal is therefore generated at the Q output terminal of flip-flop 57 to be applied to the enable input terminal 68 of flip-flop 61. Therefore, the output data time window is opened and the output data signal is transferred via line 41 to flip-flop 61. When the manual data time window ends, the set input terminal S of the flip-flop 54
A logic 0 signal appears at. Therefore, the flip-flop 54
The logic I L3 is changed to the reset input terminal R of the circuit. This causes flip-flop 54 to be reset. Logic 0 of the output terminal Q of this flip-flop 54
A signal is supplied to the input terminal of gate 56. line 43
Flip-flop 57 is reset by a second clock pulse applied to gate 56 via . Therefore, the output data time window 0(1) is closed and no output data is transferred to the flip-flop 61. When the output data time window is opened, flip-flop 61 changes state in response to each falling edge of the output data signal.

When output data time window 0(1) is closed, the Q output of flip-flop 61 will be a logical value of l or 0 depending on the number of falling edges of the output data time window.

The Q and Q output terminals of two flip-flops 60 and 61 are connected to input terminals 74-77 of exclusive OR gate 62, respectively. Such a configuration is shown in FIG. Input terminals 74 and 77 of this gate are connected to input terminals of AND gate 70, respectively. Further, input terminals 75 and 76 of this gate are connected to input terminals of an ND gate (ND gate) 71, respectively.

The output terminals of both gates 70 and 71 are connected to the input terminal of NOR gate 72, respectively. Two data time windows I(1
) and 0(1), if the values of the logic signals at the output terminals Q and Q are different, then at the output terminal 78 of the gate 62,
A logic 0 signal appears to be applied to the enable input terminal of gate 63. In the third phase state T3, Q(50)
= Q (51) = 0. These signals are supplied to the enable input terminals of gates 63, respectively.

When a clock pulse appears at the clock output terminal 29 of the write counter 2, this pulse is applied via the line 44 to the signal input terminal of the gate 63. In the third phase state T3 described above, this clock pulse appears at the output terminal 18 of the gate 63.

This pulse can activate the emergency circuit. In the fourth phase state T4, Q (50) = 0 and Q (51) = 0. These signals are applied to the enable input terminals of gates 59, respectively. However, when a clock pulse appears at the clock output terminal 26 of the write counter 2, this pulse is also supplied via the line 64 to the signal input terminal of the gate 59. The above mentioned number! 1
In phase state T4, this clock pulse is applied to gate 5.
9 output terminal. Using this clock pulse, reset the two flip-flops 60 and 61,
A new cycle of the four phase states described above can be started.

In order to eliminate the fixed delay time of a nearly one-bit circuit, the output data time window can be opened and closed by a clock pulse applied to the clock output terminal 31 of the read counter 3. Such a state is shown in FIG. 1 by dotted lines. In this case, the input terminal .multidot.13 of the comparator 17 is connected to this clock output terminal 31.

[Brief explanation of drawings]

Fig. 1 is a connection layout diagram showing the h configuration of the monitoring circuit of the present invention, Fig. 2 is a time waveform diagram showing the operation of the circuit of Fig. 1, and Fig. 3 shows a part of the circuit of Fig. 1 in detail. FIG. 4 is a connection layout diagram showing the configuration of an exclusive OR gate which is a part of the circuit of FIG. 1... Elastic store 2... Write counter 3... Read counter 4... Clock input terminal (2) 5... Data input terminal 6... Clock input terminal (3) 7-16. ... Readout gate 17 ... Comparison circuit 18 ... Output terminal (63
) 19...Data output terminals 20-29...Clock output terminals (2) 30-39.
...Clock output terminal (3) 40...First signal input terminal (17) 41...Second signal input terminal (17) 42...First control pulse input terminal (17) 43...
Second control pulse input terminal (17) 44...Third control pulse input terminal (17) 50, 51.60.61...D
Flip-flop 52, 55.56.58.59.62
．． 63... Gates 54, 57... R3 flip-flop 66... Output terminal (58) 70, 71... To NO gate 72... NOR gates 74-77... Input terminal (62) 78 ...Output terminal (62) Patent applicant NV Philips Fluiran Penfabriken

Claims (1)

[Scope of Claims] 1. has an input terminal and an output terminal, and determines the rate at which the uncoded binary bit stream conveyed through the elastic store is supplied to the input terminal of the elastic store. Different from the speed of the uncoded binary bit stream at the output terminal, the elastic store comprises n storage locations, where n bits of the binary bit stream are constantly written serially to the write register and read serially again. In a monitoring circuit in which one of the registers is stopped for a period of one bit or more depending on the degree of storage in the elastic store, the input terminal and output terminal of the elastic store are connected to the data input terminal of the comparator. and a clock output terminal of a write register controlling a memory location is also connected to a first control input terminal of said comparator, consisting of n bits and the sum of the number of bit periods during which the write register is stopped. The write time window is opened at a specific repetition rate, the clock output terminal of the read register corresponding to the clock output terminal of the write register is connected to the second control input terminal of the comparator, and the n bits and the read register are stopped. A read time window consisting of the sum of the number of bit periods in the bit period is opened at a predetermined repetition ratio, and the comparator compares the read time window with the write time window. Bit stream monitoring circuit. 2. The uncoded binary bit stream monitoring circuit according to claim 1, characterized in that the number of edges of the read time window is compared with the number of edges of the write time window. . 3. Claim 1, characterized in that the parity of the read time window is compared with the parity of the write time window.
A monitoring circuit for an uncoded binary bit stream as described in Section 1.