JPS62136939A - Code reception system - Google Patents

Abstract

PURPOSE:To extend the range decoded correctly by obtaining a deciding block code by majority decision at every bit in decoding of a block code and applying the soft decision of the code while using a weight coefficient. CONSTITUTION:Whether the reception block code from a reception input terminal 11 is a mark or space is decided at every bit by voltage comparison at a comparator 21. The series of mark/space being the result of decision is subjected to the majority decision for each bit of the block code sent for many number of times in the majority decision circuit 21 in the unit of bits and the result is outputted as a deciding block code. The information in the majority decision circuit 22 is fed to a weight coefficient decision circuit 23, the mark is taken as +1 and the space is taken as -1 at every corresponding bit of the block code received for many number of times, they are added respectively and the weight coefficient Ji to each bit of the block code is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a code reception method for receiving and decoding block codes transmitted many times. Specifically, this is a code for a transmission method that aims to improve reliability by transmitting multiple times on a transmission path where sufficient reliability cannot be obtained with just one transmission, such as control signal transmission in land mobile radio. This relates to the reception method.

[Conventional technology]

The following two methods have been adopted as conventional code reception methods for error correction block codes of multiple transmission codes.

Method 1: A method in which a received signal is decoded with an error correction code in units of frames (blocks), and the results are determined by majority vote.

Method 2: A method in which a majority vote is made on the bits corresponding to the received multiple frames (blocks) on a bit-by-bit basis, and the error correction code of the frame (1 block) is decoded based on the result.

FIG. 1 shows an implementation example of conventional method 1. The received human input signal from the reception input terminal 1) is subjected to error correction decoding by an error correction decoding circuit 12 in units of frames (blocks), and the error correction decoding output is supplied to a majority decision circuit 13. The majority decision circuit 13 makes a majority decision on the error correction decoding results for the number of input multiple transmission frames, and outputs the result to the output terminal 14.

FIG. 2 shows an implementation example of conventional method 2. Receive input terminal 1
) is input to the bit-by-bit majority decision circuit 1.
In step 5, each corresponding bit of the frame (block) transmitted multiple times is determined by majority vote. The bit-by-bit majority decision output is error corrected and decoded for each received frame (block) by the error correction decoding circuit 16, and the error correction decoded output is outputted to the output terminal 14.

These conventional methods 1 and 2 have the following drawbacks.

In conventional method 1, if a received word is received in which the distance 1liI between the received word and the transmitted code word in units of frames (pro-7ri) exceeds the error correction capability, that frame is received incorrectly. This condition is the same for all of the multiple frames that are transmitted multiple times i3, so when performing majority voting among multiple frames, depending on the false reception rate of each frame,
The non-reception rate and erroneous reception rate are determined as a result of the majority vote.

In conventional method 2, if the received word obtained as a result of bit-by-bit majority voting has an error exceeding the error correction ability, erroneous reception occurs.

On the other hand, regarding block codes, a method of performing soft-decision decoding using level information during bit-by-bit decoding is described in the literature, CD, Chase, “A C1assof
Algorithms for Decodin
g Block Codes WithChan
nel Measurement Infor+mat
ion”, IEEE.

Trans, IT-18, NO, 1, Jan, 1972
), and it has been shown that this method can expand the error correction capability for each block. In the block code soft-decision decoding method using this method, for the received word Y, Σ171Il(Yt ■X1.)→Min...
(1) Let the code word XJ, which is X, IEΩ, be the decoded output. Here, are respectively expressed. The effect of this method will be briefly explained by the following example.

Now, corresponding to two pieces of information of 0.1, Ω=(X,,X,
l-1(000), (1)1)) Consider the code to be encoded. When decoding this code, the received word consisting of 3 bits, whichever has the greater number of 0s or 1s, is used as the decoding result. Now, on the sending side, ■ is 1 (Volt) and 0 is -1
(VolL) Suppose that a K-compatible sasse Xz=(1)1) is transmitted, and the receiving side receives a waveform 18 as shown in FIG. 3A. In FIG. 3A, the numbers in parentheses represent the level values of the received waveform 18 at the time of decoding, and T represents the time slot of the received waveform 18. In the decoding method in which the positive and negative levels of the received waveform 18 at the time of decoding correspond to 1.0, in the example of FIG. 3A, the received word is Y÷(100
), and although there are more 0s, it is assumed that the code 0 has been transmitted, resulting in erroneous reception.

However, in the soft-decision decoding method using equation 1), J+=1°1z=0.2.1x=0.2, Y=('/+,
Yz.

Ys) = (100), but the reference word X, = (X++
, X+g, X13) = (000) vs. Σ1)
．． l (Yt ■Lt) = 1 ・ (1 ■ 0) + l −0,21・ (0
■O)+ 1 -0.2 l ・ (0■0)=1
．． 0 Reference word
Since it becomes 1-0.2 l° (0 180.4), which is the minimum when X2, it is assumed that 1 has been transmitted and it is correctly decoded.

In this way, in the block code soft-decision decoding method, the reference word (
A code that minimizes the distance P from the reference word weighted with a weight (level value 1) as a weighting coefficient) according to the degree of reliability of the judgment for different bits between the code word) and the received word. (
According to this method, the error correction capability of the block code is expanded. However, the level value jli (i-1 to N) when decoding in units of focus is an analog value, and such an analog level value is required to decode the error correction code, making the decoding process complicated. was there.

The purpose of the present invention is to provide a code reception method that performs hard decisions on each bit of the received code, that is, processing that is relatively slower than digital processing, and has higher decoding ability than conventional decoding that uses majority decision. There is a particular thing.

) [Means for Solving the Problems] The present invention is a code receiving method in which a signal is encoded into a multi-bit block code on the transmitting side, and a signal transmitted many times is received and decoded, and the received block code is In the comparing means, each bit is determined by voltage comparison as to whether it is a mark or a space, that is, a hard decision is made, and each determination result is used to make a majority decision for each bit of the block code that has been received many times to determine the determined block code. The weighting coefficient is obtained by the weighting coefficient determining means by determining the sum of each corresponding bit of the block code received a large number of times, with the mark of the determination result by the comparing means set to +1 and the space set to -1. The sum of the weighting coefficients for each difference or coincidence bit between the reference block code and the judgment block code is calculated for all reference block codes, and the reference block code with the minimum or maximum sum is determined as the decoding result by the soft-decision decoding means. Output.

For example, if the same frame (block) is transmitted five times and the receiving side makes a majority decision based on the focus, the judgment that a certain bit is '1' is J(5):151)i
ilI and all marks) J(4): (Out of 5 times, 4 times are marks and 1 time is a space) Jr3): (Out of 5 times, 3 times are marks and 2 times are spaces) 03 ways, This condition also applies to the determination of "0". So, +1 for marks and - for spaces.
+1 or -1 when determining “1” by matching 1
Find the sum of the values. When J(5), J= (+I)X5=
5. When J(4), J= (+1)x4+ (-1)XI
-3, J (3) J= (+1)X3+ (-1)X
2=1. The value of J obtained in this way is used as a weighting coefficient. Using this weighting coefficient instead of the level value 1) in the block code soft decision described above, and using the decision block code of the majority decision result for each bit as the block code to be decided, soft decision decoding of the block code sent out many times is performed. Do the following. At this time, since a hard decision is made using a voltage comparator on a bit-by-bit basis, decoding on a bit-by-bit basis is no different from the conventional method, and can be realized by a simple method.

On the other hand, in block code decoding, a decision block code is obtained by majority decision for each bit, and a soft decision is made using the weighting coefficients, so the range of correct decoding is expanded compared to conventional decoding methods. However, in the case of an error correction block code, the range of error correction is expanded and the non-reception rate characteristics are improved.

〔Example〕

FIG. 4 shows an embodiment of the invention, receiving input terminal 1)
The received block code is determined by voltage comparison in the comparator 21 for each bit as to whether it is a mark or a space. The sequence of marks and spaces resulting from the determination is passed through a bit-based majority decision circuit 22, where each bit of the block code sent out multiple times is subjected to majority decision and output as a determined block code. The information in the majority determination circuit 22 is supplied to the weighting coefficient determination circuit 23, and for each corresponding bit of the block code that has been received many times, the mark is added as +1 and the space as -1, and each bit of the block code is added. Obtain the weighting coefficient Ji for .

A specific example of the weighting factor determination circuit 23 is shown in FIG.

That is, the majority decision circuit 22 receives the mark and space series from the comparator 21 from the input terminal 24, for example, from the serial-in-serial-out/parallel-in-parallel-out shift registers 1) to 1. (m is the number of times the same block code is repeatedly transmitted on the transmitting side) is input to the data terminal at one end of the series connection. Shift registers 1) to 1. each consists of N stages (N is the number of bits of the block code), and shift registers II to 1. The parallel data output terminals of each corresponding stage are sequentially connected to the parallel data input terminals of the next stage. The parallel data input terminals of the first stage shift register l are each grounded. Each shift register 1. ~
1. is switched between serial operation and parallel operation by a serial/parallel control signal from terminal 25. Although not shown in the figure, a majority decision circuit receives the outputs of the parallel data output terminals of each corresponding stage of shift registers 1) to 1) 1, takes a majority decision, and outputs the result as a decision block code of the majority decision circuit 22. There is.

The parallel data output terminals of each stage of the final stage shift register 1) are connected to reversible counters 2I~ in the weighting coefficient determination circuit 23.
They are also connected to the 2H up/down switching terminals. Reversible counter 2. A bit synchronization pulse is applied from terminal 26 to each of the clock input terminals .about.2N, and a parallel/serial control signal from terminal 25 is applied to each reset terminal.

In this configuration, first, the serial/parallel control terminal 25 is set to the serial side, and mark and space sequences, which are the decoding results for each bit, are input to the terminal 24. Shift register II-1. Each block code transmitted multiple times is stored in each of the shift registers 1 . ~1. The same digit of each block code is stored in each stage 31-S, l.

Next, set the parallel/serial control terminal 25 to the parallel side, and set each of these stages SI to S, (7) "0".
” or “1” are sequentially input to the up/down switching terminals of the counters 21 to 2H.

When the parallel serial control signal at the terminal 25 becomes serial, the reversible counters 2I to 21) are reset. The reversible counters 21 to 2N operate in an amplifier count mode when the decoding result for each bit corresponding to the same digit of each block code is "1", and in a down count mode when the result is "0", using the bit synchronization pulse at the terminal 26. Count. The bit synchronization pulse is a clock pulse synchronized with the input signal,
or clock pulses at a rate proportional to that. Shift register II-1. A reversible counter 2. Reversible counter 2 when given to ~2N. ~2o
The counted values become the weighting coefficients J1 to J8.

Returning to the explanation of FIG. 4, the decision block code Y, which is the decision result of the majority decision circuit 22, and the weighting coefficient J from the weighting coefficient determining circuit 23 are supplied to the soft decision decoding circuit 28.

, the soft decision decoding circuit 28 outputs a code word (reference block code) Xj that satisfies the following for the decision block code Y and the weighting coefficient J. Here, are expressed respectively.

Next, the operation of this embodiment will be explained. For the sake of simplicity, a (7,4) Hamming code is used as the block code, and a case will be considered in which multiple transmissions are performed three times.

At this time, the results of the majority vote are determined to be "1" for the following two sets: J(31: (marked all three times) Jf2): (marked twice out of three times, spaced once), Therefore, the weighting coefficient J has two values: J=3 when J(3) and J=1 when J(2). Now, as an example, let's consider a case where the sending side sends the transmission word T = (1000101) three times (of course, T is (7, 4
) is the code word of the Hamming code), noise is added in the transmission path, and the received word three times (before the majority vote) is R,= (0001)01) RZ = (1001)1)) R3= ( 10001)1). However, 1 represents a mark and O represents a space. A 2-bit error occurs in R, , R2, and an 1-bit error occurs in R1. First, it will be shown that conventional methods cannot decode correctly.

Sub-method 1 of 1': Hamming (7°4) codes are decoded independently for R+, Rz, and R:+. In this case, humming (7,4
) Since the inter-symbol distance of the codes is 3, R,, R, will be received incorrectly, and R3 will be correctly decoded. However, since each result is decoded into a different result, a majority vote cannot be taken, and the result as a whole is non-optical (S).

By performing majority voting on each bit of R+, Rz, and Rs, Y=(1001)1)) is obtained as the received word. However, since the exclusive OR of the corresponding bits of this received word and the correct transmitted code word T is YeT= (0001010,), a 2-bit error has also occurred in Y, and Hamming (7, 4) Even if the code is decoded, erroneous reception will occur.

Next, it will be shown that correct decoding can be achieved by decoding according to the present invention. The majority vote result of each bit for R+, Rz, and R3, that is, the decision block code is Y=(1001)1)), and the corresponding weighting coefficient is J=(1-3-31313), Hamming (7 , 4) There are 16 codewords (reference block codes) The reference block code x,= (10
00101), this is the minimum, and this X2 is reproduced as the transmission word T=(1000101). On the other hand, for example, Xl is one of the code words of the Hamming (7,4) code. Considering = (1001)10),
XIO■Y= (0000001), and the received word Y is X. It is obtained by one bit error from . In other words, if only the normal error decoding operation is performed, there is a risk that the received word Y will be erroneously received as X+o. but,
According to this invention, X. When formula (2) is calculated for , it is not the minimum, but X. will not be erroneously decrypted.

In addition, in the above, formula (2) was calculated for all possible code words (reference block codes) and the code word with the minimum value of the result was calculated. If the word length of the code word is short, this may be used, but for example, BCH (6
3, 51), it would be impractical to perform the calculation of equation (2) for all of the reference block codes as it would require a huge amount of calculation. However, an efficient algorithm for minimizing equation 2) may be the method described in detail in the above-mentioned literature.

In FIG. 4, instead of the majority decision circuit 22 and the weighting coefficient determination circuit 23, the decision block code and the weighting coefficient may be determined by software, respectively. In the above, the minimum value was obtained by adding the values of the corresponding bits (digits) of the weighting coefficients for the judgment block code and the reference block code that differ by 7 corresponding bits (digits) using equation (2). The reference block code having the maximum value may be obtained by adding the values of the corresponding bits of the weighting coefficients of the corresponding bits of the block code and the reference block code that have lost one. Further, in the above description, the present invention has been applied to receiving error-correcting block codes, but it is clear that the present invention can also be applied to decoding block codes in general to obtain effects even when error correction is not possible.

"Effects of the Invention" As explained above, according to the present invention, it is possible to correctly decode received words that are not received or sometimes received incorrectly in the conventional method, and the range that can be correctly decoded is expanded compared to the conventional method. Ru. Moreover, since hard decisions are made using voltage comparators on a bit-by-bit basis, there is almost no increase in hardware when implementing this invention, and most of the work can be done digitally without using analog circuits. Can be configured as a circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional method, FIG. 2 is a block diagram showing conventional method 2, and FIG. 3 is a diagram showing received waveforms.
FIG. 4 is a block diagram showing an embodiment of the present invention, and FIG. 5 shows a part of the majority decision circuit 22 and the coefficient determination circuit 2 in FIG.
FIG. 6 is a diagram showing all code words of a Hamming (7,4) code and the calculation result of equation (2) in the description of the embodiment. Patent applicant: Nippon Telegraph and Telephone Corporation Agent: Takuo Kusano
1 Decoy number 2 Fig'yp 3 Fig A B 1 0 0shi 4 Fig 6 Fig.

Claims (1)

[Claims] (1) A code reception method in which the transmitting side encodes the code into a multi-bit block code and receives and decodes the signal transmitted multiple times, and the received block code is compared with the voltage of each bit for each mark or space. a comparison means that performs a majority judgment on each bit of a block code received many times using each judgment result to obtain a judged block code; a mark of the judgment result by the comparison means; +1" space is set as "-1", and weighting coefficient determining means obtains a weighting coefficient by calculating the sum of each corresponding bit of a block code received a large number of times; A code receiving system comprising soft decision decoding means for calculating the sum of the values of the weighting coefficients for each difference or coincidence bit with a block code, and decoding a reference block code with the minimum or maximum sum as a decoding result.