JP3386699B2 - Frame synchronization circuit and communication system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame synchronization circuit suitable for data transmission having a frame structure in an environment where code errors are likely to occur, and a communication system to which the frame synchronization circuit is applied.

[0002]

2. Description of the Related Art In the case of transmitting information data, in order to detect / correct a code error occurring in a transmission line, redundant data is added according to a predetermined coding rule, or the amount of data to be transmitted is compressed. Information data is often compressed according to the encoding rule of. A set of information data and redundant data is called a frame, and decoding is performed in frame units on the receiving side. Therefore, a method of adding a unique word indicating a frame position in a frame is widely used so that the frame can be detected on the receiving side. The position where the unique word is added is not particularly limited, but it is usually placed at the beginning of the frame in order to simplify the circuit configuration. Then, the receiving side detects the unique word to identify the frame position and decode the transmitted information data.

A block diagram of a conventional frame synchronization circuit is shown in FIG. When the received data series D is supplied to the input buffer 15 in the unique word detection circuit 12 via the input terminal 11, the received data series D is stored therein. The input buffer 15 sequentially shifts the received data series D bit by bit to generate data for a unique word length, and supplies this to one input of the comparator 16. A correct unique word is supplied from the unique word generator 17 to the other input of the comparator 16. The comparator 16 compares these and outputs "1" to the synchronization determination circuit 13 if they match and to "0" if they do not match.

For example, when the reception data series D shown in FIG. 12 (A) is received, the output of the comparator 16 becomes that shown in FIG. 12 (B). In this example, it is assumed that there is no code error in the transmission line and that there is no bit pattern matching the unique word in the information data.

Next, the operation of the synchronization determination circuit 13 will be described with reference to FIG. FIG. 13 is a state transition diagram of a conventional synchronization determination circuit. The first is the asynchronous state S1 in which frame synchronization is not established. Here, the comparator 16 outputs "1".
Is output, and "0" is output, it is "non-detection". In the case of detection, the state transits to the rear one state S2.
On the other hand, if it is not detected, it remains in the asynchronous state S1 and waits for the next output from the comparator 16.

After the transition to the rear one state S2, the received data sequence D is skipped by a fixed frame length and the comparator 16
Wait for the output of and detect / not detect. In the case of detection similar to the above, transition to the rear two states S3, and further detection /
Determine non-detection. Then, the determination is similarly repeated in the rear two states S3 and thereafter, and if the detection continues, the synchronization establishment state S5
Leading to. On the other hand, when no detection is made between the backward 1 state S2 and the backward N state S4, the state immediately returns to the asynchronous state S1. Here, the backward 1 state S2 to the backward N state S4 is called backward protection and is set to avoid erroneous synchronization. That is, if a portion of the received data series D other than the unique word coincidentally coincides with the unique word, the unique word will be erroneously detected (erroneous detection). This avoids false synchronization due to detection.

Even in the synchronization establishment state S5, the reception data series D is skipped by a fixed frame length and the comparator 16
The detection / non-detection determination is continued by the output of. If it is detected, it remains in the synchronization established state, and if it is not detected, it transits to the forward 1 state S6.

After the transition to the forward one state S6, the received data sequence D is skipped by a fixed frame length and the comparator 16
Wait for the output of and detect / not detect. In the same manner as above, in the case of non-detection, the state transits to the front 2 state S7, and further detection / non-detection is determined. Then, the determination is repeated in the same manner after the front two states S7, and if non-detection continues, the asynchronous establishment state S1 is reached. On the other hand, the front 1 state S6 to the front M state S
8 is detected, the synchronization establishment state S is immediately issued.
Return to 5. Here, the front 1 state S6 to the front M state S8
Up to what is called forward protection, it is set to avoid loss of synchronization. That is, even if non-detection occurs due to a code error, it is intended to avoid the loss of synchronization by repeating the match determination M times.

By the way, in encoding moving images, variable length encoding may be used in order to compress the amount of data. In this case, since the frame length is variable, even if the unique word is detected and the frame position can be identified, the position of the next unique word cannot be predicted. Therefore, the method such as the fixed frame length as described above cannot be used, and the received data sequence D is sequentially advanced by 1 bit for all frames, and the matching determination is repeated until detection is performed. Therefore, the synchronization protection as shown in FIG. 13 cannot be applied. In this case, especially the false detection of the unique word gives the most catastrophic result. That is, if a bit pattern that coincides with the unique word happens to exist in the received data series D, it is determined to be the correct frame position, and meaningless data will be extracted and decoded.

As a method of avoiding this, an operation called "stuffing" may be performed on the data series in advance. This is to avoid erroneous detection of a unique word by checking the data to be transmitted and inserting a predetermined dummy bit into a portion that matches the unique word. Widely used in. For example, if the unique word is "11111111", it is said that "0" is inserted as a dummy bit at the 8th bit in the portion where the data to be transmitted has 8 or more consecutive "1" s. It is a thing. This allows
The minimum Hamming distance between the unique word and the transmission data sequence can be set to 1 or more, and erroneous detection can be avoided.

A method for obtaining stronger frame synchronization by using a coding rule for information data in a frame has also been proposed (Act. 57-64815).
issue). In addition to the unique word detection method described above, this error detection and correction apparatus monitors the number of coding violations in the received data series D, and if the number of violations is below a certain threshold, it is determined to be the frame synchronization position. The judgment method is also used.

[0012]

By the way, in both the fixed length frame and the variable length frame described above, the unique word is used as the synchronization code. Therefore, when a code error occurs in the transmission path, the unique word is used. Words have been undetected or erroneously detected, causing problems such as loss of synchronization or erroneous synchronization. On the other hand, in order to improve this, it is necessary to increase the Hamming distance from the received data series D by increasing the unique word length, which is redundant.

When the probability of non-detection or erroneous detection is high, forward protection (S2 to S2) in the state transition diagram shown in FIG. 13 is performed.
S4) and backward protection (S6 to S8) are increased in number to prevent out-of-synchronization and erroneous synchronization. However, this has a drawback that it takes a long time to establish synchronization, and that it takes a long time to escape once missynchronization occurs.

Further, in the case of a variable length frame, if the above-mentioned stuffing is performed, it is necessary to add dummy data, so it is necessary to give redundancy to the transmission data only for frame synchronization. Moreover, in order to avoid non-detection due to a code error, if a method of allowing a mismatch of a fixed number of bits in the match determination is applied, the dummy bits to be inserted must be increased to secure a larger Hamming distance. However, there was a drawback that it became more redundant.

The method described in Japanese Utility Model Laid-Open No. 57-64815 described above assumes that all the information data to be transmitted are coded according to the same coding rule, and is currently widely used. A part of information data such as PDC (Foundation / Radio System Development Center "now renamed to Corporation / Industry Association" Standard 27 Chapter 5 Speech Coding), which is a known highly efficient digital signal transmission method. It cannot be applied if the coding is applied only to the frame, or if it is applied, a significant deterioration in frame synchronization performance occurs.

That is, it is general that the information data of the uncoded part is a random sequence, and if coding violation detection is performed on such a part, it is the same as in the case of the unique word detection described above. Therefore, it is difficult to know which is the correct frame synchronization position. In particular, when applied to a wireless transmission line or the like in which a code error often occurs on the transmission line, the detection threshold is set loosely in order to avoid non-detection, and thus false detection occurs at a higher frequency.

When a code error is present, the unique word is usually more reliable than the compensation signal obtained by violating the coding rule. Therefore, if the frame synchronization position obtained by using the unique word is compensated by the frame synchronization position obtained by using the coding rule violation, the reliability of frame synchronization may be deteriorated. on the other hand,
In order to avoid this, the above-mentioned actual exploitation 57-64815
In this publication, a detection method over a plurality of frames is described, but this requires a long time until the frame synchronization is established. Therefore, this method has a drawback that the initial frame synchronization establishment time and the recovery time from the loss of frame synchronization become long.

The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to prevent an increase in redundancy necessary for frame synchronization even in a transmission line with many code errors.
Moreover, the probability of non-detection / erroneous detection of frame synchronization timing, which is the main cause of loss of synchronization or false synchronization, is low, and the time required to establish synchronization and the recovery time from loss of synchronization are short. To provide a circuit.

The basic idea is derived from the skillful use of the following facts and characteristics. That is, when performing data transmission on a transmission path with many code errors, it is widely practiced to apply an error detection code or an error correction code to the data in order to protect the data or to transmit the data many times. thing. In this case, in order to suppress the redundancy of the whole, it is often the case that a plurality of error detection / correction codes having different redundancy and coding rules are used according to the code error sensitivity of the information data. The error detection code, error correction code, or redundant data encoding rule required for multiple transmissions must be able to be decoded without violating the encoding rule only when data is extracted from the correct frame position. The cause of the coding rule violation is that there is a code error in the transmission path other than the error in the frame synchronization position. The coding rule violation can be detected by using the Hamming distance of the unique word or the likelihood of the error correction code, but these values and the probability of non-detection / erroneous detection of the frame synchronization timing, that is, the reliability of the frame synchronization timing. The relationship with degree changes depending on the coding rule and the nature of the transmission path error.

[0020]

In order to solve the above-mentioned problems, in the invention described in claim 1, M (2≤M) coding rules for a part or all of the information data in the frame. In a frame synchronization circuit used when receiving a data sequence that has been subjected to, the received data sequence corresponds to N (2 ≦ N ≦ M) coding rules of the M coding rules. N likelihood calculating means for calculating each likelihood, N weighting means for multiplying each output of the likelihood calculating circuit by a coefficient, and adding means for adding each output of the weighting means. And a determination unit that compares the output of the addition unit with a threshold value and determines the frame synchronization position based on the comparison result.

Further, in the invention according to claim 2, the likelihood calculating means calculates the hamming distance between the received data series and a predetermined unique word indicating a frame position. And an error number calculation means for calculating the number of errors when error correction decoding is performed in a portion of the received data sequence encoded by Golay (23, 12) error correction encoding.

According to the third aspect of the invention, M (2) is applied to a part or all of the information data in the frame.
≤M), when one of the rules is applied, one of the rules is a frame synchronization circuit used when receiving a data sequence added with a unique word indicating a frame position. A detection unit that detects a Hamming distance with a word, a comparison unit that compares the Hamming distance with a predetermined threshold value, and a generation unit that generates a detection signal that becomes true when the value falls below the threshold value, and a received data sequence , N out of the M coding rules (2 ≦ N ≦
M) N likelihood calculating means for calculating likelihoods corresponding to the encoding rules, N weighting means for multiplying the output of the likelihood calculating circuit by a coefficient, and each weighting The output of the means is added, and the output of the addition means is compared with a threshold value, and the determination means for determining the frame synchronization position based on the comparison result, and at the timing when the detection signal becomes true, The likelihood calculating means, the weighting means, the adding means, and the determining means are operated.

According to the invention of claim 4, at least one of the coefficient of the weighting means and the threshold value of the judging means is controlled according to the state of the transmission channel related to the received data sequence. 1 is provided.

Further, in the invention according to claim 5, the weighting means of the weighting means is based on the synchronization state detecting means for detecting the frame synchronization state and the past frame synchronization state detected by the synchronization state detecting means. And a second control means for controlling at least one of the coefficient and the threshold value of the determination means.

Further, the invention according to claim 6 is characterized in that soft-decision demodulated data which is multi-valued data is used as the received data series.

Further, in the invention according to claim 7, a plurality of base stations connected to the communication network are wirelessly communicated with any one of the plurality of base stations and are connected to the communication network. In another communication terminal, or a communication system including a communication terminal that exchanges various data with another communication terminal via another base station among the plurality of base stations, the communication terminal receives the signal from the base station. Of the M coding rules, the first receiving unit that receives and demodulates the received data sequence demodulated by the first receiving unit is N
N first likelihood calculating means for calculating likelihoods corresponding to (2 ≦ N ≦ M) encoding rules, and outputs of the first likelihood calculating circuit are multiplied by coefficients. The N first weighting means, the first adding means for adding the outputs of the first weighting means, and the output of the first adding means are compared with a threshold value, and based on the comparison result. It is characterized by comprising first determining means for determining a frame synchronization position and first data processing means for extracting data from the received data series based on the determination result of the first determining means.

In the invention according to claim 8, the base station is demodulated by the second receiving means for receiving and demodulating a signal from the communication terminal and the second receiving means. N second likelihood calculating means for calculating likelihoods corresponding to N (2 ≦ N ≦ M) coding rules of the M coding rules for the received data sequence, respectively. The second
Output of the likelihood calculating circuit, N weighting means for multiplying each by a coefficient, second adding means for adding respective outputs of the second weighting means, and output of the second adding means. Is compared with a threshold value, and second determination means for determining a frame synchronization position based on the comparison result, and second data processing for extracting data from the received data series based on the determination result of the second determination means And means.

[0028]

DETAILED DESCRIPTION OF THE INVENTION

A. First Embodiment In the first embodiment, in order to simplify the description, the encoding rule to be applied is set to a minimum of 2, and a unique word is added as a synchronization code as the first encoding rule. As a rule, it is assumed that a part of the information data is error correction coded. Also, as an example of the unique word length, 3
As an example of the 2-bit error correction code, Golay (23, 12) known as a binary complete code will be taken up and described. This Golay code is a binary (23,12) linear code with a minimum distance of 7. It should be noted that these codes are actually widely used, and the generality of the description is not lost.

1: Structure of First Embodiment A frame synchronization circuit according to the first embodiment, which is an embodiment of the present invention, will be described with reference to the drawings. FIG. 1 is a block diagram of a frame synchronization circuit according to the first embodiment.
In the figure, A1, A2 ... AN are likelihood calculation circuits respectively connected to the input terminals 20, in which the likelihoods of the coding rules are calculated. FIG. 1 shows N likelihood arithmetic circuits A
1, A2 ... AN are shown, but it is sufficient to provide only the applicable coding rules. In this example, since the first and second coding rules are applied, the likelihood is calculated using the likelihood arithmetic circuit A1 and the likelihood arithmetic circuit A2.

The likelihood arithmetic circuit A1 corresponds to the first coding rule, holds a predetermined unique word, and stores the input received data series D and this unique word bit by bit. Always compare while shifting to
Both Hamming distances are output as likelihood data d1.
Further, the likelihood arithmetic circuit A2 is obtained by performing error correction decoding while always shifting the portion of the input received data sequence D encoded by Golay (23, 12) error correction encoding by 1 bit. The number of errors is output as likelihood data d2.

Further, B1, B2 ... BN are weighting circuits connected to the likelihood calculating circuits A1, A2 ... AN, respectively, and the weighting coefficient k is applied to the likelihood data d1, d2.
1, k2 ... kN are respectively multiplied, and the weighted likelihood data d
1 ', d2' ... dN 'are output. Weighting factor k1,
k2 ... kN are set so that the frame synchronization position can be accurately determined in consideration of the coding rule and the nature of the code error occurring in the transmission path. The likelihood arithmetic circuits A1, A2 ... A
Like N, it is sufficient to provide as many weighting circuits B1, B2 ... BN as there are coding rules applied. Therefore, in this example, the weighting circuits B1 and B2 are used.

Reference numeral 21 denotes an adder which adds the weighted likelihood data d1 ', d2' ... dN 'and outputs the result. 22
Is a threshold value judgment circuit, which compares the output data of the adder 21 with a predetermined threshold value, and judges "0" if the output data is greater than or equal to the threshold value, and "1" if it is less than the threshold value. Generate the signal DT. Reference numeral 23 denotes a synchronization determination circuit, which determines whether synchronization is established or asynchronous based on the threshold determination signal DT,
A synchronization determination signal SD which becomes "1" when synchronization is established and "0" when asynchronous is generated is output to a circuit (not shown) in the subsequent stage via the output terminal 24. In the simplest case, the threshold value determination signal DT is used as it is, and if it indicates "1", it is determined that synchronization is established, and if it indicates "0", it is determined that it is asynchronous.

2: Operation of First Embodiment Next, the operation of the first embodiment will be described with reference to the drawings.
Here, the unique word is the 0th, 100th, 200th and 300th words of the received data sequence D.
It is assumed to be placed in the word.

In this case, assuming that the received data series D is received through a transmission line in which a code error occurs with a predetermined probability, the Hamming distance (likelihood) calculated by the likelihood calculation circuit A1 and the bit shift. The relationship is as shown in FIG. 2, for example. In this example, at the correct frame position (positions of 0th, 100th, 200th, and 300th words),
The Hamming distance (value indicated by the likelihood data d1) is 0 or 1. Hamming distance is 1 in the 100th word
The reason is that a code error has occurred in the transmission path. On the other hand, at other timings, it can be seen that the value changes between 0 and 32. In general, information data other than the unique word can often be regarded as random. For this reason, at a wrong frame position, the Hamming distance may be close to the unique word, or the bit patterns may be completely the same. In this example, the Hamming distance is 2 at the 150th word, and
The Hamming distance is 0 at the 60th, 140th and 250th words. In these cases, it is difficult to distinguish from the Hamming distance obtained from the correct frame position. Therefore, if the frame synchronization position is determined only based on the detection of the unique word, missynchronization will occur.

Next, when the above-mentioned received data series D is supplied to the likelihood arithmetic circuit A2, the likelihood arithmetic circuit A2 decodes the received data series D to calculate the number of errors (the value indicated by the likelihood data d2. ). The relationship between the number of errors and the bit shift is as shown in FIG. 3, for example. If the likelihood is calculated at the correct synchronization position, the number of errors is 0 or 1. 20th
The number of errors is 1 in 0 word because a 1-bit code error occurs in the information data. On the other hand, in other cases, it can be seen that the change is in the range of 0 to 3. In this example, the error number is 0 or 1 in the 80th, 190th and 230th words. In these cases, it is difficult to distinguish from the number of errors obtained from the correct frame position. Therefore, if the frame synchronization position is determined based only on the number of errors, missynchronization results.

As described above, if the frame synchronization position is determined based on only one of the detection of the unique word and the number of errors, erroneous synchronization will be caused. Therefore, in the present embodiment, the weighted likelihood data d1 ′, d obtained by multiplying the likelihood data d1, d2 by the weighting factors k1, k2.
2'is added by the adder 21, and the synchronization position is determined based on the output data.

Here, the weighting factors k1 and k2 are both set to 1
Then, the output data of the adder 21 takes the values shown in FIG. In this case, at the correct frame sync position,
The 0th word is 0, the 100th word is 1, the 200th word is 0, and the 300th word is 0. On the other hand, the 60th word and the 140th word which are erroneously detected only by detecting the unique word
It becomes 3 for both the word and the 250th word.
Further, if the number of errors is detected only, the 80th word is 6, the 190th word is 13, and the 230th word is 18, which are erroneously detected. Therefore, the threshold value of the threshold value judgment circuit 22 is set to, for example, 2
Then, the synchronization can be established at the correct frame synchronization position, and in other cases, the synchronization can be established.

As described above, according to this embodiment, the likelihoods corresponding to a plurality of types of coding rules are calculated by the likelihood calculation circuit A1.
.. to AN, weighting them and determining the frame synchronization position based on this, the unique word length can be shortened even if a transmission path in which a code error easily occurs is used. Also, the time required to establish synchronization can be shortened. Also, the recovery time can be shortened after the loss of synchronization.

B. Second Embodiment In the second embodiment, except that the weighting factors k1, k2 ... kN are switched according to the state of the transmission channel (transmission path),
It is similar to the first embodiment. Further, the frame synchronization circuit in this example is applied to mobile communication used in mobile phones and the like.

FIG. 5 is a block diagram of a frame synchronization circuit according to the second embodiment. In the figure, CS is channel information, which is information indicating the state of the transmission channel. The channel information CS indicates, for example, the fading pitch of the wireless channel, the received electric field strength, and the like. Fading (variation in received electric field strength) occurs when a mobile station moves at high speed. In this case, if the received electric field strength falls below a certain level, a burst error occurs. On the other hand, the code error when the mobile station is stopped is often a random error. Therefore, by referring to the fading pitch or the like of the channel information CS, it is possible to know the nature of the error that occurs in the transmission channel.

Numeral 25 is a controller, which generates control signals for controlling the weighting coefficients k1, k2 ... kN based on the channel information CS, and outputs the control signals to the weighting circuits B1, B.
2 ... Output to BN.

By the way, the likelihood data d from the likelihood calculating circuits A1, A2, ... AN is determined depending on the state of the transmission channel.
The reliability of 1, d2 ... dN is different. This point will be specifically described. Here, as in the first embodiment, the likelihood arithmetic circuit A1 detects the Hamming distance between the received data series D and the unique word as the likelihood data d1, and the likelihood arithmetic circuit A2 makes an error. It is assumed that the number is detected as the likelihood data d2.

If the mobile station is moving at high speed, the code error occurring in the transmission channel is often a burst error as described above. In this case, even if the frame synchronization position is correct, if there is an error at this timing, it will be continuous. Therefore, the Hamming distance between the received data series D and the unique word becomes large. on the other hand,
When the mobile station is stopped, code errors occurring in the transmission channel can be regarded as random errors,
Even if an error occurs in the correct frame synchronization position, the probability that a plurality of code errors will occur in the unique word is low. Therefore, the Hamming distance between the received data series D and the unique word is small. Therefore, if the transmission channel is in a state where burst errors are likely to occur, the reliability of the likelihood data d1 is low,
It can be said that the reliability of the likelihood data d1 is high when the transmission channel is in a state where random errors are likely to occur.

On the other hand, the change in the likelihood data d2 due to the change in the state of the transmission channel differs depending on the coding method of the received data series D. For example, when a burst error-resistant one such as a fire code is used as an encoding method, even if a burst error occurs, it can be detected with certainty. In this case, the reliability of the likelihood data d2 is high regardless of the state of the transmission channel. Therefore, the reliability of the likelihood data d1 and the likelihood data d2 relatively changes as the state of the transmission channel changes.

As described above, the likelihood data d from the likelihood calculation circuits A1, A2, ... AN depending on the state of the transmission channel.
The reliability of 1, d2 ... dN changes individually and relatively. Focusing on this point, the present embodiment calculates the reliability of the likelihood data d1, d2 ... dN based on the channel information CS, and changes the weighting factors k1, k2 ... kN accordingly. . In the above example, when it is determined from the channel information CS that the state of the transmission channel is likely to cause a burst error, the weighting factor k1 is reduced and the contribution of the likelihood data d1 is relatively reduced. On the other hand, when it is determined from the channel information CS that the state of the transmission channel is prone to random errors, the weighting factor k1 is set to a normal value. As a result, the weighting factors k1, k2 ... k
Since N can be adaptively controlled, it is possible to reliably detect the frame synchronization position even if the state of the transmission channel changes.

C. Third Embodiment The third embodiment is the same as the first embodiment except that the threshold value of the threshold value judgment circuit is controlled based on the past synchronization judgment result. In addition, in the third embodiment, it is assumed that the information data is subjected to variable-length coding, and the header portion of the received data series D is provided with auxiliary data indicating a frame length.

FIG. 6 shows a block diagram of a frame synchronization circuit according to the third embodiment. In the figure, a synchronization determination circuit 2
3'is a threshold control signal SS based on the received data sequence D and the threshold determination signal DT supplied via the input terminal 20.
To generate. The threshold control signal SS indicates a threshold, and when this is fed back to the threshold determination circuit 22, the threshold is changed.

Here, a circuit diagram of the synchronization determination circuit 23 'is shown in FIG. In the figure, when the received data sequence D and the threshold judgment signal DT are supplied to the separation circuit 230, the separation circuit 230 receives the data based on the frame synchronization position ("1") indicated by the threshold judgment signal DT. The auxiliary data HD is separated from the data series D, and this is down-counter 231.
Supply to. After loading the auxiliary data HD, the down counter 231 starts down counting using the clock signal reproduced from the received data series. Then, the ripple carry signal RC is set to "1" when the count value becomes 0 and to "0" otherwise.

Since the auxiliary data HD indicates the frame length, the timing at which the ripple carry signal RC becomes "1" is the timing at which the next unique word is predicted to be detected. If the current frame sync position is correctly detected and the next frame sync position is correctly detected, unless a code error occurs in the auxiliary data HD,
The ripple carry signal RC and the threshold judgment signal DT are "1".
The timing will be the same. On the other hand, if erroneous synchronization occurs in either one, the ripple carry signal RC is "1".
And the timing when the threshold determination signal DT becomes "1" do not match. The AND circuit 232 detects the former, and "1" if the detection of the frame synchronization position is continuously correct.
Becomes On the other hand, the EX-OR circuit 233 detects the latter,
It becomes "1" when false synchronization occurs. The output of the AND circuit 232 is supplied to the up-counting terminal of the up counter 234, and the output of the EX-OR circuit 233 is supplied to the down-counting terminal thereof.

In this case, the count value of the up / down counter 234 is increased when the correct frame synchronization position is continuously detected, and the count value is decreased when erroneous synchronization occurs. Therefore, it can be said that the count value of the up counter 234 at a certain time indicates the degree to which the past synchronization result was true. The threshold control circuit 235 generates a threshold control signal SS based on this count value, and the threshold is controlled by this signal.

By the way, when the received data sequence D is supplied to the frame synchronization circuit via a transmission line where a burst error is likely to occur, once synchronization is correctly established in a portion where there is no code error, the code is continued thereafter. It is estimated that there are few errors and the correct frame synchronization position can be easily detected. In such a case, if the threshold value of the threshold value judgment circuit 22 can be lowered, false synchronization can be reduced. On the other hand, in the case where the received data series D enters via a transmission line where a code error is likely to occur, asynchronous is likely to occur continuously. Therefore, it can be estimated that the asynchronization is likely to occur even when the asynchrony is continuous. In such a case, if the threshold value of the threshold value judgment circuit 22 can be increased, the asynchronism can be prevented.

In this example, the threshold value of the threshold value judgment circuit 22 is controlled according to the count value of the up / down counter 234 indicating the past synchronization result. Specifically, when the count value is large, the control is performed to lower the threshold value, and when the count value is small, the control is performed to increase the threshold value. With this, the threshold is adaptively controlled,
Asynchronous / missynchronous can be avoided.

D. Fourth Embodiment The fourth embodiment is similar to the first embodiment except that a unique word detection circuit 30 and a first threshold value judgment circuit 31 are newly provided.

FIG. 8 is a block diagram of a frame synchronization circuit according to the fourth embodiment. In the figure, the unique word detection circuit 30 calculates the Hamming distance between the received data series and the unique word, and outputs the value to the first threshold value judgment circuit 31. The first threshold value determination circuit 31 generates a trigger signal TS that becomes "1" when the Hamming distance is equal to or less than the first threshold value and otherwise "0". Here, the first threshold value is set so as not to miss the synchronization position and not be detected, and to reduce the amount of calculation. For this reason,
The timing at which the trigger signal TS becomes "1" is not non-detection, although the synchronization position may have been erroneously detected.

The trigger signal TS is the circuit 1 surrounded by the dotted line.
00 (frame synchronizing circuit of the first embodiment). This point will be described with reference to FIG. FIG. 9 is a flowchart showing the operation of the frame synchronization circuit. In the figure, when the input of the received data series D is started (step ST1), it is determined whether or not the trigger signal TS becomes "1" (step ST2). If the trigger signal TS is "0", this determination is repeated until it becomes "1". When it becomes "1", the process proceeds to step ST3 and the circuit 100 executes the operation. After that, the process returns to step ST2 and the processes of steps ST2 and ST3 are repeated. That is, the unique word detection circuit 30 and the first threshold value determination circuit 31 perform the first-stage synchronization determination, and the circuit 100 performs the second-stage determination. In the first-stage synchronization determination, the frame synchronization position is estimated, which reduces the calculation amount of the circuit 100. Second
The frame synchronization position is accurately identified in the stage synchronization determination.

As described above, according to the present embodiment, the calculation of the circuit 100 is executed only when the trigger signal TS becomes "1". Therefore, it is possible to accurately identify the frame synchronization position while reducing the calculation amount. You can In particular, when calculating the number of errors as the likelihood in the likelihood arithmetic circuit, it is usually necessary to obtain the remainder in the Galois field, and further, it is necessary to calculate this while sequentially shifting the frame synchronization position in bit units. The amount of calculation can be greatly reduced.

E. Modifications The present invention is not limited to the above-mentioned embodiment,
For example, the following modifications are possible. In each of the above-described embodiments, the received data sequence may be convolutionally coded, and in this case, the likelihood at Viterbi decoding is calculated by one of the likelihood calculation circuits A1 to AN. do it. Further, the likelihood arithmetic circuits A1 to
The AN may calculate the likelihood based on detection of unique words having different unique word lengths, error detection by CRC, violation of Huffman coding rules, error detection of stuffing, and the like.

In each of the above-mentioned embodiments, the number of coding rules relating to the received data sequence and the likelihood arithmetic circuit A
The numbers of 1 to AN do not necessarily match. Specifically, when the number of coding rules is M, the N likelihoods corresponding to N (2 ≦ N ≦ M) coding rules of the M coding rules are calculated. A likelihood calculation circuit may be provided.

Further, the second embodiment and the third embodiment may be combined. In addition, in the second embodiment described above,
Although the weighting factors k1 to kN are controlled based on the channel information CS, the threshold value of the threshold value determination circuit 22 may be controlled based on this information. Further, in the third embodiment, the threshold value is controlled based on the threshold value control signal SS, but the weighting factor k1 to
You may make it control kN. Moreover, you may combine suitably the above modified example and 2nd-4th embodiment.

The received data sequence may be soft decision demodulation data which is multi-valued data. In this case, the likelihood may be obtained based on soft decision decoding or Hamming distance calculation using soft values.

F. Application Example This application example is the first to fourth embodiments (especially, the second embodiment) described above.
It is an application example applied to the mobile communication system using the frame synchronization circuit described in the embodiment). Here, FIG.
0 is a block diagram of a mobile communication system. In the figure, the mobile communication system includes a mobile unit 40 that can be carried by a user or mounted in a vehicle, and a mobile unit 40.
0 and a base station 50 that connects the mobile device 40 to the communication network 60. Although only one mobile device 40 and one base station 50 are shown in the illustrated example, a plurality of mobile devices 40 and base stations 50 may be provided.

The mobile unit 40 includes an antenna 401, a transmission / reception unit 402, a frame synchronization circuit 403, and a data processing unit 40.
4, voice processing unit 405, speaker 406, microphone 407
Etc. The transmission / reception unit 402 modulates the signal supplied from the data processing unit 404, and the antenna 401
By transmitting to the base station 50 by the antenna 40
The signal received in 1 is demodulated and supplied to the data processing unit 404.

The frame synchronization circuit 403 is the frame synchronization circuit of the present invention described above. When the frame position is identified by the signal (frame configuration signal) supplied from the transmission / reception unit 402 and the synchronization is established, the data is transmitted. Processing unit 404
To the data processing unit 404 in the case of non-synchronization, the synchronization determination signal SD of "1" is supplied to the data processing unit 404.

The data processing unit 404 extracts user data (data, voice data), error correction code, error detection code, etc. from the signal (frame configuration signal) supplied from the transmission / reception unit 402 according to the synchronization determination signal SD. At the same time, after scrambling or the like is added to the audio data from the audio processing unit 405, control data or the like is added to form a frame and the frame is supplied to the transmitting / receiving unit 402.

The voice processing unit 405 is the data processing unit 4 described above.
The voice data taken out at 04 is converted into an analog voice signal by D / A conversion, and the speaker 406 produces a sound. Further, the voice processing unit 405 converts the analog voice signal input from the microphone 407 into voice data by A / D conversion, encodes the voice data by a predetermined method, and the data processing unit 4
Supply to 04.

The base station 50 includes an antenna 501, a transmission / reception section 502, a frame synchronization circuit 503, and a data processing section 50.
4, a network control unit 505 and the like.
The transmission / reception unit 502 modulates the signal supplied from the data processing unit 504, transmits the signal to the mobile device 40 by the antenna 501, demodulates the signal received by the antenna 501, and supplies the signal to the data processing unit 504.

The frame synchronization circuit 503 is the frame synchronization circuit of the present invention described above, and when the frame position is identified by the signal (frame configuration signal) supplied from the transmitting / receiving unit 502 and the synchronization is established, the data is transmitted. Processing unit 504
To the data processing unit 504 in the case of non-synchronization.

The data processing unit 504 extracts user data (data, voice data), error correction code, error detection code, etc. from the signal (frame configuration signal) supplied from the transmission / reception unit 502 according to the synchronization determination signal SD. At the same time, after scrambling or the like is added to the signal from the network control unit 505, control data or the like is added to form a frame and the frame is supplied to the transmission / reception unit 502.

The network control unit 505 converts the voice data extracted by the data processing unit 504 into an analog voice signal by D / A conversion and sends it to the communication line network 60. Further, the network control unit 505 converts the signal supplied from the communication line network 60 into a digital signal by A / D conversion, encodes the signal by a predetermined method, and supplies the data processing unit 504.

According to the above configuration, in the mobile unit 40 and the base station 50, the data processing units 404 and 50 respectively.
In 4, the user data (data, voice data), error correction code, error detection code, etc. are extracted from the received signal based on the synchronization determination signal SD supplied from the frame synchronization circuits 403, 503. Therefore, it is possible to reliably detect the frame synchronization position. In addition, the time required to establish synchronization can be shortened, and the recovery time after loss of synchronization can be shortened.

[0071]

As described above, according to the present invention,
Even in transmission lines with many code errors, there is no increase in redundancy necessary for frame synchronization, and the probability of non-detection / erroneous detection of frame synchronization timing, which is the main cause of loss of synchronization and false synchronization, is low, and synchronization is established. It is possible to provide a frame synchronization circuit having features such as a required time to reach and a short recovery time from loss of synchronization.

[Brief description of drawings]

FIG. 1 is a block diagram of a frame synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a Hamming distance calculated by a likelihood calculating circuit A1 and a bit shift according to the same embodiment.

FIG. 3 is a diagram showing the relationship between the number of errors and bit shift according to the same embodiment.

FIG. 4 shows weighting factors k1 and k2 in the same embodiment.
FIG. 6 is a diagram showing a relationship between output data of the adder 21 and bit shift when both are set to 1.

FIG. 5 is a block diagram of a frame synchronization circuit according to a second embodiment.

FIG. 6 is a block diagram of a frame synchronization circuit according to a third embodiment.

FIG. 7 is a circuit diagram of a synchronization determination circuit 23 ′ according to a third embodiment.

FIG. 8 is a block diagram of a frame synchronization circuit according to a fourth embodiment.

FIG. 9 is a flowchart showing an operation of the frame synchronization circuit according to the fourth embodiment.

FIG. 10 is a block diagram of a mobile communication system to which a frame synchronization circuit according to the present invention is applied.

FIG. 11 is a block diagram of a conventional frame synchronization circuit.

FIG. 12 is a timing chart for explaining the operation of the conventional frame synchronization circuit.

FIG. 13 is a state transition diagram of a conventional synchronization determination circuit.

[Explanation of symbols]

D reception data series A1 to AN likelihood calculation circuit (likelihood calculation means) B1 to BN weighting circuit (weighting means) 21 addition circuit (adder) 22 threshold value determination circuit (determination means) 30 unique word detection circuit (detection means) 31 first threshold value judgment circuit (generation means) TS trigger signal (detection signal) 23 'synchronization judgment circuit (synchronization state detection means, second control means) 25 controller (first control means)

─────────────────────────────────────────────────── ─── Continuation of front page (56) Reference JP-A-60-128735 (JP, A) JP-A-61-262333 (JP, A) JP-A-5-7189 (JP, A) JP-A-6- 350589 (JP, A) Japanese Patent Laid-Open No. 4-72933 (JP, A) SAI 57-64815 (JP, U) Special Table 9-503359 (JP, A) U.S. Pat. No. 4,495,619 (US, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 7/08 H04J 3/06 H03M 13/00

Claims (8)

(57) [Claims] 1. A received data sequence in a frame synchronization circuit used when receiving a data sequence subjected to M (2 ≦ M) coding rules for a part or all of information data in a frame. On the other hand, N likelihood calculation means for respectively calculating likelihoods corresponding to N (2 ≦ N ≦ M) coding rules among the M coding rules, and the likelihood calculation circuit. N to multiply the output by the coefficient
Individual weighting means, addition means for adding the outputs of the weighting means, and determination means for comparing the output of the addition means with a threshold value and determining the frame synchronization position based on the comparison result. And a frame synchronization circuit. 2. The likelihood calculating means calculates a hamming distance between a received data series and a predetermined unique word indicating a frame position, and a Hamming distance calculating means Golay (23, 12) of the received data series. 2. The frame synchronization circuit according to claim 1, further comprising error number calculation means for calculating the number of errors when error correction decoding is performed in a portion coded by error correction coding. 3. When applying M (2 ≦ M) coding rules to a part or all of the information data in a frame, one of the rules adds a unique word indicating a frame position. In the frame synchronization circuit used when receiving the data sequence, the detection means for detecting the hamming distance between the received data sequence and the unique word is compared with the hamming distance and a predetermined threshold value, and falls below the threshold value. And a likelihood corresponding to N (2 ≦ N ≦ M) coding rules of the M coding rules for the received data sequence. N likelihood calculating means for calculating each, and N for multiplying the output of the likelihood calculating circuit by a coefficient.
Individual weighting means, addition means for adding the outputs of the weighting means, and a determination means for comparing the output of the addition means with a threshold value and determining the frame synchronization position based on the comparison result, the detection signal A frame synchronization circuit, wherein the likelihood calculation means, the weighting means, the addition means, and the determination means are operated at the timing when is true. 4. A first control means for controlling at least one of a coefficient of the weighting means or a threshold value of the judging means according to a state of a transmission channel related to the received data sequence. Claims 1 to 3
The frame synchronization circuit according to any one of the above. 5. A synchronization state detection means for detecting a frame synchronization state, and at least one of a coefficient of the weighting means or a threshold value of the determination means based on a past frame synchronization state detected by the synchronization state detection means. The frame synchronization circuit according to claim 1, further comprising a second control unit that controls one of the two. 6. The frame synchronization circuit according to claim 1, wherein soft-decision demodulation data that is multivalued data is used as the received data sequence. 7. A plurality of base stations connected to a communication line network, and another communication terminal connected to the communication line network by wirelessly communicating with any one of the plurality of base stations, or the plurality of base stations. In a communication system including a communication terminal that exchanges various data with another communication terminal via another base station, the communication terminal includes a first receiving unit that receives and demodulates a signal from the base station. , N (2 ≦ N ≦) of the M coding rules for the received data sequence demodulated by the first receiving means.
M) N first likelihood calculating means for calculating likelihoods corresponding to the encoding rules, and N number of multipliers for multiplying the output of the first likelihood calculating circuit by a coefficient. No. 1 weighting means, first adding means for adding the outputs of the first weighting means, and comparing the output of the first adding means with a threshold value, and determining the frame synchronization position based on the comparison result. A communication system, comprising: a first determining means for performing the above; and a first data processing means for extracting data from the received data series based on the determination result of the first determining means. 8. The base station receives second signals from the communication terminal and demodulates the second signals, and the reception data sequence demodulated by the second reception device includes M number of signals. Of the encoding rules, N (2 ≦ N ≦
M) N second likelihood calculating means for calculating likelihoods corresponding to the encoding rules, and N weighting for multiplying the output of the second likelihood calculating circuit by a coefficient. A second addition means for adding the outputs of the second weighting means and the output of the second addition means with a threshold value, and a frame synchronization position is determined based on the comparison result. 8. The communication system according to claim 7, further comprising: a second data processing unit that extracts data from the received data series based on the determination result of the second determination unit.