JPS6213262Y2 - - Google Patents

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Publication number
JPS6213262Y2
JPS6213262Y2 JP18893581U JP18893581U JPS6213262Y2 JP S6213262 Y2 JPS6213262 Y2 JP S6213262Y2 JP 18893581 U JP18893581 U JP 18893581U JP 18893581 U JP18893581 U JP 18893581U JP S6213262 Y2 JPS6213262 Y2 JP S6213262Y2
Authority
JP
Japan
Prior art keywords
output
circuit
amplifier
capacitor
range amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP18893581U
Other languages
Japanese (ja)
Other versions
JPS5894124U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP18893581U priority Critical patent/JPS5894124U/en
Publication of JPS5894124U publication Critical patent/JPS5894124U/en
Application granted granted Critical
Publication of JPS6213262Y2 publication Critical patent/JPS6213262Y2/ja
Granted legal-status Critical Current

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  • Television Signal Processing For Recording (AREA)

Description

【考案の詳細な説明】 本考案はノンリニアプリエンフアシス回路の改
良に関するものである。
[Detailed Description of the Invention] The present invention relates to an improvement of a nonlinear pre-emphasis circuit.

第1図は従来の磁気記録再生装置のノンリニア
プリエンフアシス回路を示す。図において1,
2,3,8は抵抗、4,5はコンデンサ、6,7
はダイオードである。入力信号は入力端子Aから
入り、低周波成分は抵抗2を、高周波成分は抵抗
3、高域増強コンデンサ4を通り次段へ進む。抵
抗2,3の比を適当に選ぶことにより高周波成分
は低周波成分に比較し利得をもたせることが出来
る。次に低域しや断コンデンサ5及びダイオード
6,7により、高周波成分の振幅制限を行つて出
力端子Bに出力信号が出ていくわけである。かよ
うにして、入力信号の高周波成分に相対的な利得
を与え振幅制限を行なうことにより、入力信号が
小さくなればなるほど低周波成分に対し高周波成
分の利得をあげるノンリニアプリエンフアシス回
路を構成している。第2図はVTRにおけるノン
リニアプリエンフアシスのVHS規格の特性を示
すものである。
FIG. 1 shows a nonlinear pre-emphasis circuit of a conventional magnetic recording/reproducing device. In the figure 1,
2, 3, 8 are resistors, 4, 5 are capacitors, 6, 7
is a diode. The input signal enters from the input terminal A, and the low frequency component passes through the resistor 2, and the high frequency component passes through the resistor 3 and the high frequency enhancement capacitor 4 before proceeding to the next stage. By appropriately selecting the ratio of the resistors 2 and 3, the high frequency component can have a gain compared to the low frequency component. Next, the amplitude of the high frequency component is limited by the low frequency shedding capacitor 5 and the diodes 6 and 7, and an output signal is output to the output terminal B. In this way, by giving a relative gain to the high frequency components of the input signal and limiting the amplitude, a non-linear pre-emphasis circuit is constructed that increases the gain of the high frequency components relative to the low frequency components as the input signal becomes smaller. ing. Figure 2 shows the VHS standard characteristics of nonlinear pre-emphasis in a VTR.

しかるにこの回路をIC化する場合、入出力端
子がIC内で接続されているにしても2つのコン
デンサ4,5がある為、最低3つのICピンが必
要となり、回路構成が簡素であるにもかかわら
ず、ICの出力ピンが多くなるという点、又最低
2コのコンデンサを外付部品とせざるを得ぬ欠点
があつた。
However, when converting this circuit into an IC, even though the input and output terminals are connected within the IC, there are two capacitors 4 and 5, so at least three IC pins are required, and even though the circuit configuration is simple, However, there were disadvantages in that the number of IC output pins increased and that at least two capacitors had to be external components.

本考案は、上記のような従来のものの欠点をを
除去するためになされたもので振幅制限ダイオー
ドの低域しや断のために用いられたコンデンサの
機能を集積回路化可能な電圧発生器に行なわせ高
域増強用コンデンサは一端接地で使える回路とし
て集積回路化しした時のピン数と外付部品を減少
せしめたノンリニアプリエンフアシス回路を提供
することを目的としている。
The present invention was made to eliminate the drawbacks of the conventional ones as described above, and it is possible to integrate the function of a capacitor used for cutting off the low frequency range of an amplitude limiting diode into a voltage generator that can be integrated. The purpose of the high-frequency enhancement capacitor is to provide a nonlinear pre-emphasis circuit that can be used with one end grounded, reducing the number of pins and external components when integrated.

第3図は本考案のノンリニアプリエンフアシス
回路の一実施例である。
FIG. 3 shows an embodiment of the nonlinear pre-emphasis circuit of the present invention.

図において8,9,10,12,13,18,
20,25,26,27は抵抗、14,15はダ
イオード、11,16,21,23,24はトラ
ンジスタ、17,22は定電流源、19はコンデ
ンサである。
In the figure 8, 9, 10, 12, 13, 18,
20, 25, 26, 27 are resistors, 14, 15 are diodes, 11, 16, 21, 23, 24 are transistors, 17, 22 are constant current sources, and 19 is a capacitor.

入力端子A′い加えられた入力信号はトランジ
スタ11,16,21のベースに加えられる。ト
ランジスタ21のコレクタ−電圧は定電流源22
で引いているので定電位となる。一方トランジス
タ16に加えられた信号をは抵抗18、コンデン
サ19でエミツタピーキングし高周波成分に利得
をもたせ高域成分のみがトランジスタ16のコレ
クタに出力される。
The input signal applied to input terminal A' is applied to the bases of transistors 11, 16, and 21. The collector voltage of the transistor 21 is the constant current source 22.
Since it is pulled by , it becomes a constant potential. On the other hand, the signal applied to the transistor 16 is subjected to emitter peaking by a resistor 18 and a capacitor 19, giving a gain to the high frequency component, and only the high frequency component is output to the collector of the transistor 16.

またトランジスタ16とトランジスタ21間に
はダイオード14,15のクリツパが接続され高
域の振幅制限を行なう。
Further, clippers of diodes 14 and 15 are connected between the transistor 16 and the transistor 21 to limit the amplitude in the high range.

この高域分はトランジスタ23,24のMIX回
路で全域増幅信号と混合することになる。
This high frequency component is mixed with the overall amplified signal in the MIX circuit of transistors 23 and 24.

すなわち出力端子B′には高周波成分に利得をも
たせ、また入力信号レベルが小さくなるにつれ低
周波成分に対する高周波成分の利得が大きくなる
出力信号をが得られる。諸元選択で例えば第2図
に示すようなVHS規格の特性を得られる。
That is, an output signal can be obtained at the output terminal B' in which the high frequency component has a gain, and the gain of the high frequency component increases with respect to the low frequency component as the input signal level decreases. By selecting the specifications, for example, characteristics of the VHS standard as shown in FIG. 2 can be obtained.

第4図、第5図、第6図に他の実施例を示す。 Other embodiments are shown in FIGS. 4, 5, and 6.

第4図ないし第6図において28,32,3
6,37,38,42,45,46,50,5
3,56,59,61は抵抗、29,34,35
はダイオード、31,40,44,52,55は
定電流源、33,47,57はコンデンサ、3
0,39,41,43,48,49,51,5
4,58,60はトランジスタである。
28, 32, 3 in Figures 4 to 6
6, 37, 38, 42, 45, 46, 50, 5
3, 56, 59, 61 are resistances, 29, 34, 35
is a diode, 31, 40, 44, 52, 55 are constant current sources, 33, 47, 57 are capacitors, 3
0, 39, 41, 43, 48, 49, 51, 5
4, 58, and 60 are transistors.

第4図は第3図で示すC部のIC内部の実際の
回路で第5図はダイオードではなくトランジスタ
を使用した場合の実施例である。
FIG. 4 shows an actual circuit inside the IC of section C shown in FIG. 3, and FIG. 5 shows an example in which transistors are used instead of diodes.

第6図は第3図で示すD部のMIX回路の他の実
施例である。
FIG. 6 shows another embodiment of the D section MIX circuit shown in FIG.

なお、第3図で全域増幅器は抵抗10,12ト
ランジスタ11で、高域増幅器は抵抗13,18
トランジスタ16定電流源17コンデンサ19で
エミツタピーキング回路により構成されまたクリ
ツプ回路はダイオード14,15で、高域増幅器
動作点回路は抵抗20トランジスタ21定電流源
22で、加算器はトランジスタ23,24抵抗2
5,26,27で構成されている。
In addition, in FIG. 3, the full range amplifier is made up of resistors 10 and 12 and the transistor 11, and the high range amplifier is made up of resistors 13 and 18.
The emitter peaking circuit includes a transistor 16, a constant current source 17, and a capacitor 19. The clip circuit includes diodes 14 and 15, the high-frequency amplifier operating point circuit includes a resistor 20, a transistor 21, a constant current source 22, and the adder includes transistors 23 and 24. resistance 2
It consists of 5, 26, and 27.

ここで従来の低域しや断コンデンサ5の動作を
高域増幅器動作点回路にすることにより2ピン、
高域増強用コンデンサ4の代わりに高域増幅器を
使用し1ピンと合計3ピンのピン数を少なくする
ことができる。
Here, by changing the operation of the conventional low-frequency cutoff capacitor 5 to a high-frequency amplifier operating point circuit, the 2-pin,
By using a high-frequency amplifier instead of the high-frequency enhancement capacitor 4, the number of pins can be reduced to 1 pin and a total of 3 pins.

以上のように、従来の回路では第1図に示すよ
うに、コンデンサを2個使用していたが、本考案
では1個のコンデンサで従来と同等の特性を得る
ことができた。この為、この回路をIC化するの
に入出力ピンがIC内部で他の回路と接続されて
いた場合3ピン必要であつたものが1ピンで実現
可能となりIC化の目的とする周辺部品の削減及
びICピンのピン数を少なくすることができるな
どの効果がある。
As described above, the conventional circuit uses two capacitors as shown in FIG. 1, but in the present invention, the same characteristics as the conventional circuit can be obtained with one capacitor. For this reason, when converting this circuit into an IC, what would have required three pins if the input/output pins were connected to other circuits inside the IC can now be realized with one pin. This has the effect of reducing the number of IC pins and reducing the number of IC pins.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のノンリニアプリエンフアシス回
路の回路図、第2図はVTRにおけるノンリニア
プリエンフアシス回路のVHS規格の特性図、第
3図は本考案のノンリニアプリエンフアシス回路
の一実施例を示す回路図、第4図ないし第6図は
本考案の他の実施例の回路図である。 図において、8,9,10,12,13,1
8,20,21,22は抵抗、14,15はダイ
オード、11,16,21,23,24はトラン
ジスタ、17,22は定電流源、19はコンデン
サ、A′は入力端子、B′は出力端子である。
Figure 1 is a circuit diagram of a conventional non-linear pre-emphasis circuit, Figure 2 is a VHS standard characteristic diagram of a non-linear pre-emphasis circuit in a VTR, and Figure 3 is an example of the non-linear pre-emphasis circuit of the present invention. The circuit diagrams shown in FIGS. 4 to 6 are circuit diagrams of other embodiments of the present invention. In the figure, 8, 9, 10, 12, 13, 1
8, 20, 21, 22 are resistors, 14, 15 are diodes, 11, 16, 21, 23, 24 are transistors, 17, 22 are constant current sources, 19 is a capacitor, A' is an input terminal, B' is an output It is a terminal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 全域増幅器と、高域増幅器と、電圧発生手段
と、前記全域増幅器と前記高域増幅器の出力加算
器と、前記電圧発生手段出力と前記高域増幅器出
力の電位差が所定のレベルになつたとき、前記高
域増幅器出力をクリツプする双方向性クリツプ手
段を備え、前記電圧発生手段出力と前記高域増幅
器動作点間電位差を前記クリツプ手段作動レベル
以下に設定してなるノンリニアプリエンフアシス
回路。
a full range amplifier, a high range amplifier, a voltage generation means, an output adder of the whole range amplifier and the high range amplifier, and when a potential difference between the output of the voltage generation means and the output of the high range amplifier reaches a predetermined level; A non-linear pre-emphasis circuit comprising bidirectional clipping means for clipping the output of the high-frequency amplifier, the voltage difference between the output of the voltage generating means and the operating point of the high-frequency amplifier being set below the operating level of the clipping means.
JP18893581U 1981-12-17 1981-12-17 Nonlinear pre-emphasis circuit Granted JPS5894124U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18893581U JPS5894124U (en) 1981-12-17 1981-12-17 Nonlinear pre-emphasis circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18893581U JPS5894124U (en) 1981-12-17 1981-12-17 Nonlinear pre-emphasis circuit

Publications (2)

Publication Number Publication Date
JPS5894124U JPS5894124U (en) 1983-06-25
JPS6213262Y2 true JPS6213262Y2 (en) 1987-04-06

Family

ID=30103096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18893581U Granted JPS5894124U (en) 1981-12-17 1981-12-17 Nonlinear pre-emphasis circuit

Country Status (1)

Country Link
JP (1) JPS5894124U (en)

Also Published As

Publication number Publication date
JPS5894124U (en) 1983-06-25

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