JPS62132416A - Digital delay circuit - Google Patents

Abstract

PURPOSE:To speed up the data processing by providing an output means outputting a data stored in the 1st latch means and the 2nd latch means in the clock rate of a basic clock pulse alternately. CONSTITUTION:A digital delay circuit outputs an n-bit input data while retarding the data by M-cycle, an address space corresponding to the delay is divided into two memory cell arrays 55, 65, the memory cell array 55 forms an even order address plane and the memory cell array 65 forms an odd number address plane. The memory cells 55, 65 in each split address space are subject to R-M-W operation in a cycle twice that of the basic clock pulse phis, the two address spaces are accessed alternately by the 1st and 2nd read/write means while the phase is shifted by one cycle of the basic clock pulse phis, the read data from both the address spaces is outputted alternately in the cycle of the pulse phis and the input data inputted in the cycle of the pulse phis is written alternately in both the address spaces. Thus, high speed performance is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital delay circuit, and particularly to a digital delay circuit used for video signal processing of a digital television receiver.

[Prior Art] Conventionally, as a large-capacity digital delay means, a delay circuit has been known which sequentially reads and writes signals to Iζ memory cells arranged on a matrix to obtain a desired delay. It is being

FIG. 6 is a schematic block diagram showing the first stage of such a conventional digital delay circuit. First, the configuration of a conventional digital delay circuit will be described with reference to FIG.

A basic clock pulse φ is input to the input terminal 1. The unit il! in this digital delay circuit! The extended opening time (small delay width) is equal to one cycle of the basic clock pulse φ. The basic tally clock pulse φ8 input from the input terminal 1 is applied to the address counter 2. Address counter 2 is incremented at the rising edge of basic clock pulse φ6, and provides X address signal to X decoder 3 and Y address signal to Y decoder 4.

Input terminal 13. 1 to 1311 are terminals that receive input data signals that are input in synchronization with the basic clock pulse φS, and will be described here with a configuration that receives n-bit input. The MSB (most significant bit) of the input data signal is connected to terminal 13.
．． It is assumed that the LSB (least significant bit) is applied to the terminal 13o. Input data signal is input latch 1
1 to the memory cell array 5 via the transfer gate 6 from the 1-in circuit 10 controlled by the signal WE.

The memory cell array 5 is a group of memory cells arranged in a matrix, and its storage capacity is MXnpi1-.

The transfer gate 6 transmits data from the 1-in circuit 10 to the memory cell array 5, and also transmits data read from the memory cell array 5 to the sense amplifier 7. The sense amplifier 7 is controlled by the signal @SE, and amplifies the read data and supplies it to the data latch 8. The data latch 8 temporarily stores the output of the sense amplifier 7. The data latch 8 is electrically isolated from the sense amplifier 7 during the period when the signal SE is high.The output of the data latch 8 is given to the output latch 9. The delayed output from
．． Give from 12 to 12. The MSB of the output data signal is output from terminal 121, and the LSB is output from terminal 12.1.

The basic tarock pulse φ input from the input terminal 1 is also applied to the timing generator 14. The timing generator 14 receives the basic clock pulse φ and generates the signal SE and the signal WE in the timing sequence shown in FIG. 2 mentioned above. The signal SE is l
The sense amplifier 7 is put into operation state during the period of “Hl”, and the signal W
E puts the write circuit 8 into operation during the period of °H'.

Note that the matrix counter 2 is reset every M cycles by a reset circuit (not shown).

To give concrete numbers, for example, in a PAL television receiver, an analog video signal is sampled at a frequency of 4fsc <fyc: color subcarrier frequency) to generate a digital video signal and then digitally processed. Considering the delay of one scanning line (I
The aim is to realize a 1-line memory that achieves 1-line delay (H delay) with the configuration shown in Fig.
35, n -8. Also, the X address is XO to X7. The Y address can be realized by connecting Y to Y, and one cycle of eight O-clock pulses φ is 56 n5ec.

Note that such specific numerical values can be arbitrarily selected depending on the relationship with the device to be used, so they will not be used in the following explanation, that is, in the explanation of the prior art and in the explanation of one embodiment of the present invention. , will be explained in general terms so that any numerical value can be selected.

FIG. 7 is a timing chart for explaining the operation of the conventional digital delay circuit shown in FIG.

Next, the operation of the conventional digital delay circuit will be described in detail with reference to FIGS. 6 and 7. In this example, M
Explain how the cycle delay is obtained. In this digital delay circuit, the memory used is arranged in n sets of arrays each having an address capacity of M, and 1H memory cells of each set of arrays correspond to one address. is specified, a total of n memory cells from n sets of arrays are accessed in parallel. Here, in a byte-structured memory, the number is n-8.

In the following explanation, Iyi is assigned to each address from Δ to A.
Each input data is stored in l.

to D gates, and output data read from addresses A to An are respectively t'IPDI to PDM.

first,! One click pulse φ causes the address counter 2 to operate, giving an X address signal to the X decoder 3 and a Y address signal to the Y decoder 4.

In the memory cell array 5, among the cells belonging to the row selected by the X decoder 3, data of n-bit memory cells belonging to the column connected to the transfer gate 6 selected by the Y decoder 4 is output to the I10 line 17. Ru. For example, the output of address counter 2 is address A,
, each address A of n arrays is
, the information PD of a total of nlJ memory cells corresponding to , is read out in parallel via transfer gates 1-6.

The read n-bit data PD has a signal SE of H°.
The signal is amplified by the sense amplifier 7 during the period ', and taken into the data latch 8. Since data latch 8 is electrically disconnected from sense amplifier 7 as signal SE falls, data latch 8 holds read data PCI while signal SE is at low level. Read data P D
+ is transmitted to the output latch 9 and n output terminals 12 .
or 12. are output in parallel. In this way, as shown in FIG. 2, data is sequentially read out in response to changes in the address signal for each cycle of the basic clock pulse φ.

On the other hand, after the signal SE falls, during the designated period of the same address, during the H'' period of the signal WE, the write circuit 10 operates and writes the n-bit input signal sent from the input latch 11! 10 line 17 and rewrites the data of the selected memory cell.For example, address A
, the previous data PD is read out and stored in the data latch 8, and the new data D1 is at address A.

is written to the memory cell of Data D is read out when address A is designated again after M cycles. In this way, READ-MODIFIED-W is performed every M cycles for the memory cell at each address.
11 RI TE (R-M-W) operations are performed and the newly written data is output after M cycles, achieving a delay of M cycles.

[Problems to be Solved by R-Mei] As described above, the conventional digital delay circuit must perform reading and writing during one cycle of the basic clock pulse φ. Therefore, the cycle of the basic tallock pulse φ must be determined by taking into consideration the read access time up to the data latch, the write completion time, the pulse width of the signal SE, the timing margin between address signals, etc. Momentum makes the cycle longer. Therefore, there are problems such as difficulty in increasing the data latch speed.

Therefore, the main object of the present invention is to obtain a digital delay circuit that can operate at a higher speed than the conventional configuration using the same process technology as the conventional one.

Means for Solving Problems] The digital delay circuit according to the present invention has aP! The address space of the divided memory cell group is divided into two halves, and the memory cells in each divided address space are R-Med at twice the cycle of the basic clock pulse φS.
-W operation, and the two address spaces are accessed alternately by the first and second reading self-transfer means with a phase shift of one cycle of the basic clock pulse φ, and both address spaces are The read data from the address space is output alternately in the cycle of the basic clock pulse φ, while the input data inputted in the cycle of the basic clock pulse φ$ is alternately input into both address spaces.

[For l\] The digital delay circuit according to the present invention substantially converts each of the seven dress blanks into a basic tarok pulse φ.

While operating at a clock rate of 211 cycles,
Since the data input/output operation can apparently be completed in the cycles of M lock pulses φ9, the digital delay circuit can be operated in a half cycle of the minimum operating It cycle for each of the 7 address spaces. , a digital delay circuit capable of high-speed operation.

[Embodiment of the invention] FIG. 1 is a schematic block diagram of an embodiment of the invention.
FIG. 2 is a specific circuit diagram of the delay latch circuit shown in FIG. 1.

First, the configuration of an embodiment of the present invention will be described with reference to FIGS. 1 and 2. The digital delay circuit shown in FIG. 1 delays the input data of n pins 1- by M cycles and outputs it, and divides the address space corresponding to the amount of delay into two memory cell arrays 55 and 65. The memory cell array 55 forms an even address plane, and the memory cell array 65 forms an odd address plane.The capacity of each memory cell array 55 and 65 is equal and is (M/2)×n pits. .

A basic clock pulse φ is applied to the input terminal 51. The cycle time of this basic clock pulse φ8 is chosen to be equal to the unit delay time. This basic Otsuk pulse φ8
is given to the timing generator 64. This timing generator 64 will be explained in detail in FIG. 3 below, but the internal clock pulse φ5. (2) and timing signals 5EeV, 5Eoo, WEev, and WEoo are generated in accordance with the timing sequence shown in FIG. 4, which will be described later. Internal clock pulse φt, ■LGt basic clock pulse φ,
It is a frequency division of
It has twice the period and is applied to address counter 52, delay latch circuits 71.72, and data latches 58.68. Timing signals 5Eev and 5Eoo control the sense amplifiers 57 and 67, respectively, and put the sense amplifiers 57 and 67 into operation during the "I-1" period. The timing signals WE, .

Address counter 52 receives internal clock pulses φ, or
This is ■, the period of tfJ (tL water 0tsuku pulse φ.

An X address signal of an even number address is given to the X decoder 53, and a Y address signal of an even number address is given to the Y decoder 54 at a frequency twice In2). The output of the X decoder 53 is given to the memory cell array 55 and the delay latch circuit 72,
The output of the decoder 54 is applied to a transfer gate 1-56 and a delay latch circuit 71.

The output of the delay latch circuit 72 is the memory cell array 65
The output of the delay latch circuit 71 is applied to the transfer gate 66. These delay latch circuits 71
．． 72 is I'll 1 due to the internal clock φ
It consists of a plurality of parallel latches that are zeroed. The delay latch circuit 71 basically delays the output of the Y decoder 54 by the period of the basic clock pulse φ8, and the delay latch circuit 72 similarly delays the output of the Y decoder 54 by the period of the basic clock pulse φ8.

The output of the X decoder 53 is delayed by a period of .

Next, the configuration of the delay latch circuit 72 will be explained with reference to FIG. In addition, f erase r ludge circuit 71
The delay latch circuit 72 is a well-known static latch circuit of 0MO8, and includes an inverter circuit 75, 76, a transfer gate 73 of NMO8, and a 1-transfer gate 7 of PMO8.
4. The output of the X decoder 53 shown in FIG. Transfer gate 74 is provided between the input end of inverter circuit 75 and the output end of inverter circuit 76 , and the output end of inverter circuit 76 is connected to memory cell array 65 . Further, an internal open pulse φ is input to the gate electrodes of the transfer 1 gates 73 and 74.

Referring again to FIG. 1, transfer gate 56 transfers read data from memory cell array 55 to sense amplifier 57 via 1.10*80, and also transfers data read from write circuit 60 via l10Ii180. Memory cell array 5
5. Similarly, the transfer gate 66 transmits read data from the memory cell array 65 to the sense amplifier 67 via l101181, and r1068
Data from the write circuit 70 is transmitted to the memory cell array 65 via the write circuit 1.

Data latch circuits 58 and 68 temporarily hold the output data of sense amplifiers 57 and 67, and their respective outputs are both given to output latch 59. The data latch 58 also receives a timing signal 5Eev.
During the period when the signal is L', it is electrically connected to the sense amplifier 57.
．． ? The data latch 68 is electrically disconnected from the sense amplifier 67 while the timing signal 5Eoo is "L'".

Furthermore, the data of the data latch 68 is transmitted to the five output latches during the period when the internal clock pulse φ is "°H", and the data of the data latch 68 is transmitted to the five output latches during the period when the internal clock pulse φ is "°H". ” is transmitted to the output latch 59. The output latch 59 outputs an n-bit M-cycle delayed output to output terminals 621 and 62 at a basic clock pulse φ and a zero rate. In addition, the input terminal 63.
63 to 63 basically receive n-bit input data signals inputted at the D clock pulse φ and the D clock rate, and these input data signals are transmitted to the aforementioned write circuits 60 and 70 via the input latch 61. .

Note that the address counter 52 is controlled by a reset circuit (not shown) and is reset every M cycles.

3 is a specific circuit diagram of the timing generator shown in FIG. 1, and FIG. 4 is a time chart for explaining the operation of the timing generator shown in FIG. 3.

Next, the configuration and operation of the timing generator will be described with reference to FIG. 3 and FIG. ia4.

Incidentally, FIG. 3 shows timing signals SE and V for writing and reading of the memory cell array 55 constituting the even-numbered seven dress planes shown in FIG.

Although only the timing generator that generates WEev is shown, the timing signal SE for writing and reading of the memory cell array 65 constituting the odd-numbered AT1 node is shown.
The timing generator that generates W-work is also constructed in the same way.

First, the memory cell array 5 constituting the even address plane
The read operation of No. 5 starts with the fall of the internal a clock pulse φ1. In other words, as is clear from the timing chart shown in FIG. 4, the states of each signal before the internal clock pulse φL falls are: PCeV="L", dummy word line-"L", LVEev""H"
, 5Eey” “L”.

It is EC Shrimp-H''.

The address is determined by the fall of the internal clock pulse φ. Then, the internal clock pulse φ is applied to one input terminal of the 2NAND gate 23,
PCev rises from l L 11 to °H°° by the NAND gate 23, and precharging is stopped. 2
The output of the NAND gate 23 is given to one input terminal of the 2NAND gate 24.
The output becomes "L" and is further inverted to "Hoo" by the inverter 35. The output of the inverter 35 serves as a dummy word line that generates the same delay as when an arbitrary word line is selected.

After that, the output of inverter 935 is transferred to inverter 27.28
The output of the inverter 28 is 1L°.
' to H°'. The output of this inverter 28 is delayed by the delay circuit 20 at a certain time ll1i! ! The signal is extended, inverted by an inverter 29, and applied to one input terminal of a 2NAND gate 22.

Since the output of the inverter 28 is given to the other input terminal of the 2NAND gate 22, the 2NAND gate 22
The output of 2 remains "L" for a certain period of time, "l-1"
Since this output is inverted by the inverter 30, the timing signal SF:ev becomes "H" for a certain period of time and then falls to 11L11.

The pulse width of this timing signal SE:@v can be arbitrarily set by the delay time of the delay circuit 20.

Next, the memory cell array 5 constituting the even address plane
The 1-input operation of 5 is an internal clock pulse φ.

It begins by standing up. In other words, the state of each signal before the internal clock pulse φ rises is the fourth
As is clear from the timing chart in the figure, -e at the door
v = "H", dummy word line - "H",
WEev=”H”, 5Eev-”, ECeV-”
1-1".

Internal clock pulse φ is delayed by delay circuit 21, and its delayed output is inverted by inverter 34 and applied to one input terminal of 2NAND gate 26. Since the internal clock pulse φL is applied to the other input terminal of this 2NAND gate 26, the timing signal WEe
v remains constant for a certain period of time and then falls to 11 L II, starting the write operation. This timing signal W
The EeV pulse width can be arbitrarily set by the delay time of the delay circuit 21.

As the timing signal WEev falls,
The output of the 3NAND gate 25 causes ev to fall to L, which causes the 2NAND gate 24 to rise to hHH, which is inverted by the inverter 35, causing the dummy word line to fall to low.
PmCev falls to "L" by the 2NAND gate 23 and starts precharging for the next cycle. When this "81" falls to L°', the "L" signal is Since the signal is input to the 3NAND gate 25, the output of the 3NAND gate 25 becomes H'', and ev is returned to its original "H" state at r.

Referring again to FIG. 1, internal clock pulse φ, generated from timing generator 64.

φ is the address counter 52 and delay latch times 287
1.72 and data latches 58.68. Furthermore, the timing signals SE, , 5Eoo are respectively given to sense amplifiers 57 and 67, and these sense amplifiers 5
7.67 and puts the sense amplifier 57.67 into the 111 operating state during the 1('' period.Furthermore, the timing signals WE, v, and WEoo are controlled by the write circuit 60, respectively.
．． 70, the 1-included circuit 6 is activated during the “°L” period.
Subtract 0.70 from the operating state. , and data latch 58.
The output of 68 is controlled by internal clock pulses φL,'/'L.

Figure 5 is the vJ of Figure 1! It is a time chimeto to explain ¥.

Next, with reference to FIGS. 1 to 5, a specific dynamic f\ of an example M of the present invention will be described.

Input terminal 63. ．． 632...63. to input latch 6
1 is input at 1°C, address A1. A2... Receive n bits of input data newly stored in AM,
D2...D pipe (see Figure 5(b)), address A
1. Let the output data read from A2...AM be PD, PDz...PDM, respectively.

The timing generator 64I divides the basic tarlock pulse φ shown in FIG. 5(a) to generate an internal clock pulse φ shown in FIG. 5(C).

The address counter 52 is incremented by the falling edge of the internal clock pulse φ, and the even address signal 174 has a period twice that of the basic clock pulse φ.
Ad (see FIG. 5(d)), gives an even-numbered address signal to the X decoder 53, and
4 is given a Y address signal of an even address. In this way, in even address cycles, the X decoder 53 and the Y decoder 53
Decoder 54 selects a particular address cell within memory cell array 55 forming an even address plane.

Since the delay latch circuit 72 is configured as shown in FIG. 2 of about 4, it takes in the output of the It is applied to the memory cell array 65 constituting the odd address plane. Similarly, the delay latch circuit 71 delays the output of the Y decoder 54 by one cycle of the basic clock pulse φ, and applies it to the transfer gate 66. Therefore, a specific address cell in the memory cell array 65 constituting the odd address plane is selected by the output of the delay latch circuits 71 and 72, but the odd address cycle is longer than the even address cycle by one cycle of the basic clock pulse φ. Only you will always be late.

Now, if address A2 is specified by the address counter 52, the The n-bit data PD2 stored in is read out to the I10 line 80 via the transfer gate 56.The data PD2 is sensed when the timing signal 5Eev shown in FIG. The data latch 58 is amplified by the amplifier 57 and latched by the data latch 58 as shown in FIG.
Since the timing signal 5 is electrically disconnected from 7, the timing signal 5
During the period when Eev="L", data PD2 is data latch 5.
It is held at 8. The data PD2 is transmitted to the output latch 59 during the H'' period of the internal open pulse φL, and the read data PD2 is output from the output terminals 621, 622, . . . , 62° of n1lJ.

On the other hand, the timing signal WEev shown in FIG.
During the "L" period, the write circuit 60 operates, and the input terminals 63. ．． 63□...631. New n-pit data D2 input from the input latch 61 and stored in the input latch 61
is set to 1 in the cell at the same address Δ2. In this way, in the address cycle of A2, READ-MO
DIFI ED-WRITE operation is completed.

On the other hand, due to the operation of the delay latch circuits 71 and 72,
A2. The address cycle A is started one cycle of the basic clock pulse φS after the address cycle, and the n1ll cell located at address A in the memory cell array 65 is selected and has already been stored (M~1) cycles ago. The nth data PD, which is being read out, is read out to the 1.10 line 81 via the transfer gate 66. The data PD is the timing signal S shown in FIG. 5(J).
E. 0 is amplified by the sense amplifier 67 during the H'' period and latched into the data latch 68. data latch 6
8 is electrically disconnected from the sense amplifier 67 at the fall of the timing signal 5E0o, so during the period when the slow timing signal 5Eoo is "L", the data PD,
is latched in data latch 68. When the internal clock pulse fL becomes H'', data PD is output from the horn latch 5.
9 and n output terminals 62 . ．． 622...6
2. is output from.

On the other hand, the write circuit 70 operates during the 'L'° period when the timing signal WE is 0, as shown in FIG. 5(k), and the input terminal 637
．． New n-pit data D input from 632...63n and stored in the input latch 61 is written to the same address A. Thus, in A, address cycle, REAO-MOD [F I ED
-WRI TE operation is completed.

In the memory cell array 55, the A2 address cycle ends and the A3 address cycle is delayed by one cycle of m lock pulses φ from the start of the A3 address cycle.
, an address cycle begins, and a read operation of data PD is performed.

As mentioned above, the n-bit input data input in the cycle of the clock pulse φ5 is input to the memory cell array 55.
and memory cell array 56, and simultaneously write to output terminal 62. ．． 622...62, 1, the read data from memory cell 7 lay 55.56 is delayed by M cycles of basic clock pulse φ8 from the time of input, and alternately at the clock rate of basic clock pulse φ. Output. In this way, it operates as a digital delay line achieving a delay of M cycles.

In addition, in Example C of above j-e, data delay for even stages could be obtained in order to access two memory cells 55 and 65 having the same capacity address space, respectively, but data delay for odd stages could be obtained. In order to reduce the data delay by 1q, a one-stage delay circuit such as a register may be provided immediately before or immediately after the output latch 59.

Further, the digital delay circuit according to the present invention may be realized using a static memory circuit or a dynamic memory circuit.

[Effects of the Invention] As described above, according to the present invention, the address space corresponding to the amount of delay is divided into two storage means, and each storage means stores data within an address cycle that is twice the period of the basic clock pulse. READ-MOD f FIED-WRITE processing is performed, and the phases of the address cycles are made to differ by one cycle of the basic D-pulse between the two storage means, and the read data from the two storage means is basically The clock pulses are output alternately at the clock rate, while the basic clock pulse clock rates 1 to r are configured to alternately store the input data in the two storage means. While operating each storage means at a clock rate corresponding to two cycles of the basic clock pulse, it is possible to apparently complete the data production at the clock rate h of the basic clock pulse. Therefore, the digital delay circuit can be operated at a clock rate corresponding to a half cycle of the minimum operation cycle of the storage means, and high-speed performance can be improved. In addition, since the read and write operations are configured to be started by the rising or falling edge of the divided clock pulse of the basic clock pulse, the timing control circuit can be configured simply and can operate reliably. can.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. Second
The figure is a specific circuit diagram of the delay latch circuit shown in FIG. 1. FIG. 3 is a specific circuit diagram of the timing generator shown in FIG. 1. FIG. 4 is a time chart for explaining the operation of the timing generator shown in FIG. 3. FIG. 5 is a time chart for explaining the operation of FIG. 1. FIG. 6 is a block diagram showing the configuration of a conventional digital delay circuit. FIG. 7 is a timing chart for explaining the operation of the conventional digital delay circuit shown in FIG. In the figure, 52 is an address counter, 53 is an X decoder, 54 is a Y decoder, 55.65 is a memory cell 7-ray, 56.66 is a transfer gate, 57°67 is a sense amplifier, 58.68 is a data latch, and 59 is a Output latch, 60
．． 70 is a 1-include circuit, 61 is an input latch, 64 is a timing generator, and 71.72 is a Tilley latch circuit.

Claims (1)

[Scope of Claims] A digital delay circuit whose operation is controlled in synchronization with a basic clock pulse and outputs an input signal after delaying it by a predetermined time, wherein input signals synchronized with the basic clock pulse are sequentially input. an input terminal; a timing signal generating means for generating a first timing signal obtained by dividing the basic clock pulse into a frequency twice that of the basic clock pulse; and a second timing signal in which the polarity of the first timing signal is inverted; first and second storage means that are accessed, read data from the first storage means at one of the rising and falling timings of the first timing signal; and a first read/write means for writing an input signal input from the input terminal to the address from which the data was read at the other timing of the rising and falling edges of the second timing signal; At either one of the timings, data is read from the second storage means, and at the other timing of the rising or falling edge of the second timing signal, the input signal is transferred to the address from which the data was read. a second read/write means for temporarily storing and holding the data read from the first storage means; a first latch means for temporarily storing and holding the data read from the second storage means; A digital device comprising: second latch means for storing and retaining data; and output means for alternately outputting data stored in the first latch means and the second latch means at a clock rate of the basic clock pulse. delay circuit.