JPS62131679A - Picture transmission equipment - Google Patents

Abstract

PURPOSE:To reproduce a sampling clock synchronously with a synchronizing signal at the reception side by providing a means for detecting the location of the synchronizing signal included in a picture signal in a transmission frame period at the transmission side and sending the location information together with the said picture signal. CONSTITUTION:A horizontal synchronizing signal is extracted from an input picture signal to drive a flip-flop 20. An output of the flip-flop 20 is inputted to a phase comparator 23 of a PLL circuit to recover the clock fS synchronized with the horizontal synchronizing signal. As a result, the clock fS of the output of a voltage-controlled oscillator 24 obtained is used as the sampling clock in an A/D converter, a coder and a buffer memory. A frame signal sent from a transmission section enters a separation panel 31. A value of an address signal section A in the panel 31 is shifted to a register 33 automatically and a counter 35 starts counting by using a transmission clock f0 frequency-divided by a frequency divider 34. When the count reaches the value in the said register 33, a carry signal is sent. The position of transmitting the carry signal is the same position as that of the horizontal synchronizing signal.

Description

[Detailed Description of the Invention] [Summary] When transmitting an image signal via a digital transmission path, the transmitting side transmits the position information of the horizontal synchronizing signal for the frame of the transmission path, and the receiving side converts the horizontal synchronizing signal from this position information. A sampling clock synchronized with the horizontal synchronization signal is created by reproducing and inputting it to the PLL circuit.

[Industrial application field]

The present invention relates to a sampling clock generation method when transmitting an image signal through a digital transmission path.

When transmitting image signals using a digital transmission path,
The clock of the image signal is naturally not synchronized with the clock of the digital transmission line.

Therefore, on the receiving side, it is not possible to directly extract from the received signal a clock that is synchronized with the clock of the image signal on the transmitting side.

Various methods have been proposed to solve this problem.

C. Prior Art FIG. 4 is a diagram for explaining a conventional image transmission device.

FIG. 5 is an explanatory diagram of a conventional method for extracting a horizontal synchronization signal.

In the figure, 1 is an A/D converter, 2 is a KOG, 3 is a buffer memory, 4 is a synchronization separation circuit, 5 is a PLL circuit, 6 is a multiplexing circuit, 7 is a frequency dividing circuit, and 8 is a U/B converter. , 9 is an oscillator,
10 is a D/A converter, 11 is a decoder, 12 is a backup memory, 14 is a separation circuit, 15 is a B/U converter,
50 is a counter, 51 is a voltage controlled oscillator, 52 is a frequency divider, 53 is a counter, 54 is a difference circuit, 55 is a low-pass filter, and 56 is a D/A converter circuit. The same symbols represent the same objects throughout all the figures below.

FIG. 5(a) shows the input image signal, which is sliced by the synchronization separation circuit 4 at the level shown by the chain line in FIG. A horizontal synchronization signal is input to the PLL circuit 5 to generate synchronized sampling clocks f and J.

On the other hand, the clock f of the transmission line. The sampling clock f of the input signal is synchronized with the clock frequency-divided by the frequency divider 7,
is counted by a counter 50, the lower bits of the counted value, for example 8 bits, are multiplexed by a multiplexing circuit 6, converted into a bipolar signal by a U/B conversion circuit 8, and transmitted.

On the receiving side, the B/U conversion circuit 15 converts the signal into a unipolar signal, the separation circuit 14 separates the lower bits, and the difference circuit 54 digitally calculates the difference between the unipolar signal and the output of the counter 53. This difference is converted into an analog signal by the D/A converter 56, and then sent to the PLL via the low-pass filter 55.
The voltage is inputted as a control voltage of the voltage controlled oscillator 51 of the circuit, and a clock fs, that is, a clock fs' synchronized with a synchronization signal is created.

Using the clock fs' thus obtained, the signal is read from the buffer memory 12, decoded by the decoder 11, and D/A converted by the D/A converter 10 to demodulate the signal.

[Problem that the invention seeks to solve]

However, in the above conventional method, especially when converting the difference circuit output to D-A on the receiving side, not only is a highly accurate and expensive A-A converter required to ensure accuracy, but also the configuration of the difference circuit is complicated. Therefore, the disadvantage is that the scale of the hardware becomes large.

[Means for solving problems]

The problem mentioned above is the clock f of the transmission line. A clock f that is asynchronous with the input signal but synchronized with the input signal.

and when transmitting a digital signal, the transmitting side detects the position of the synchronization signal and clock of the input signal within the transmission frame period, and transmits the position information in a frame as shown in FIG. 1, This problem can be solved by detecting a synchronizing signal and a clock from the received position information on the receiving side, regenerating a clock whose phase is synchronized with the detected signal, and using it as a sampling clock.

[Effect]

According to the present invention, the transmitting side extracts the horizontal synchronizing signal from the input signal, contains the position information and the presence/absence information of the horizontal synchronizing signal in a transmission frame, and sends it out, and the receiving side extracts the horizontal synchronizing signal from the input signal, and transmits it by storing the position information and information on the presence or absence of the horizontal synchronizing signal in the transmission frame, and the receiving side extracts the horizontal synchronizing signal from the input signal. Since the PLL circuit is used to create a clock that is synchronized with the sampling clock on the transmitting side, the effect is that the sampling clocks on the transmitting side and the receiving side are synchronized.

〔Example〕

FIG. 2 shows an embodiment of an image transmission device according to the present invention.

In the figure, 13 is a PLL circuit, 16 is a frequency dividing circuit, 17 is a position decoding circuit, and 18 is a counter.

On the transmitting side, the horizontal synchronization signal (15, 75Hz) is separated from the input image signal by the synchronization separation circuit 4, and the PLL
A clock f is inputted to the circuit 5, and a clock f is generated in the PLL circuit 5, and the A/D converter 1, Korg 2, buffer memory 3, etc. are operated using this clock f as a sampling clock.

Note that both buffer memories 3 and 12 use elastane ink type buffer memories.

The image signal stored in the buffer memory 3 in accordance with the sampling clock fs is multiplexed with the output of the counter 18 in the multiplexing circuit 6 using the transmission lock f0, that is, the output clock of the oscillator 9, and then sent to the U/B converter. At step 8, the unipolar format signal is converted into a bipolar format signal, and then sent out to the transmission path.

On the receiving side, the bipolar format received signal is B/U.
The converter 15 converts the signal back into a unipolar format signal,
The position signal is separated in the separation circuit 14 and enters the buffer memory 12.

The image signal that has entered the buffer memory 12 is driven by the clock f5, is decoded in the decoder 11, and is sent to the D/
Although it is converted into an analog signal by the A converter 10, the problem here is how to transmit the sampling clock fS from the transmitting side to the receiving side in order to synchronize the clock f5' and the sampling clock fsO.

For this reason, in the present invention, the frame sent from the transmitting side contains information on the presence or absence of a horizontal synchronization signal and the position information of the horizontal same-month signal, and the receiving side creates a sampling clock based on the above information and the transmission lock. Restore the image signal.

FIG. 1 shows an example of a frame structure according to the present invention.

In the figure, F is a frame signal section, G is a signal section indicating the presence or absence of a horizontal synchronization signal, A is an address signal section, and P is an image signal section.

The frame structure of the present invention differs from the conventional frame structure in that, as is clear from FIG. 1, a signal section G indicating the presence or absence of a horizontal synchronization signal and an address signal section A are added.

In the example shown in FIG. 1, for example, the frame signal part F has 10 bits, the signal part G indicating the presence or absence of a horizontal synchronization signal has 1 bit,
Address signal part A is 10 bits, image No. 18 part P is 10 bits.
03 bits, therefore one frame consists of 1024 bits.

FIG. 3 (al indicates an embodiment of the transmitter configuration according to the present invention).

In the figure, 20 is a flip-flop (F/F), 21.22
is a Nant gate, 23 is a phase comparator (PC), 24 is a voltage controlled oscillator (VCXO), 25 is a frequency divider, 26 is a counter, 27 is a register, 28 is a frame control signal circuit,
29 is a frequency divider, and 30 is a frame configuration circuit.

A horizontal synchronization signal is extracted from the input image signal and drives the flip-flop 20. In order to reproduce the clock fs synchronized with this horizontal synchronization signal, the output of the flip-flop 20 is set to P.
It is input to the phase comparator 23 of the LL circuit. The clock fS of the output of the voltage controlled oscillator 24 obtained as a result is the A/D
It is used as a sampling clock in the converter 1, Korg 2, buffer memory 3, etc.

On the other hand, the oscillator 9 is used as a clock f0 source for the transmission line, and its output is input to the frame control signal circuit 28, the frame configuration circuit 30, and the frequency divider 29.

In response to an instruction from the frame configuration circuit 30, the frame control signal circuit 28 starts the counter 2 in response to a start signal from the frame signal section F.
6 is cleared, and the counter 26 starts counting the output pulses of the frequency divider 29. At the same time, the start signal is Nantes Gate 21
is applied to As mentioned above, the flip-flop 20 is repeatedly turned on and off in synchronization with the horizontal synchronizing signal.

Therefore, when the flip-flop 20 is turned on while the counter 26 is counting, an output is generated to the Nant gate 22, which transfers the count value at that time to the register 27 and sends information to the frame configuration circuit 30 that a horizontal synchronization signal is present. .

The frame configuration circuit 30 receives the information about the presence of horizontal synchronization number 18 (1 means it is present, 0 means it is absent), the contents of the register 27 (
It receives position information (210) and image (No. 8), composes a frame signal shown in FIG. 1, and transmits it using lock f.

FIG. 3(b) shows an embodiment of the configuration of the receiving section according to the present invention.

In the figure, 31 is a separation board, 32 is an AND gate, 33 is a register, 34 is a frequency divider, 35 is a counter, 36 is a phase comparator (PC), 37 is a voltage controlled oscillator (V CX O),
38 is a frequency divider, and 39 is a frequency divider.

The frame signal transmitted from the transmitter enters the separation board 31. The separation board 31 accommodates frame signals.

The value of the address signal part A in the separation board 31 is automatically transferred to the register 33, and when the signal part G indicating the presence or absence of the horizontal synchronization signal is "1" and the frame signal part F is normal, The AND gate 32 opens, loads the value of the register 33 into the counter 35, starts counting at the transmission lock f0 frequency-divided by the frequency divider 34, and the count value is set in the register 35.
When the value reaches 3, a carry signal is sent. The transmission position of this carry signal is the same as that of the horizontal synchronization signal.

Therefore, this carry signal is sent to the phase comparator 36 of the PLL circuit.
, a sampling clock f5' synchronized with the eight sampling clocks f and sent to the output of the voltage controlled oscillator 37 can be obtained.

〔Effect of the invention〕

As described above in detail, the present invention has the great effect of allowing the receiving side to reproduce a sampling clock that is synchronized with the sampling clock on the transmitting side, that is, synchronized with the synchronization signal.

[Brief explanation of drawings]

FIG. 1 shows an example of a frame structure according to the present invention. FIG. 2 is a diagram showing an image transmission device according to the present invention. FIG. 3+a) shows the configuration of the transmitting section according to the present invention, and FIG. 3(b+
1 and 2 respectively show an example of the configuration of the receiving section. FIG. 4 is a diagram showing a conventional image transmission device. FIG. 5 is a diagram for explaining a conventional method of extracting a horizontal synchronization signal. In the figure, F is a frame signal section, G is a signal section indicating the presence or absence of a horizontal synchronization signal, A is an address signal section, P is an image signal section, 1
is A/D converter, 2 is Korg, 3 is buffer memory, 4
is a synchronous separation circuit, 5 is a PLL circuit, 6 is a multiplexing circuit, 7
is a frequency dividing circuit, 8 is a U/B converter, 9 is an oscillator, and 10 is a D
/A converter, 11 is a decoder, 12 is a buffer memory,
13 is a PLL circuit, 14 is a separation circuit, and 15 is a B/L circuit.
U converter, 16 is a frequency dividing circuit, 17 is a position decoding circuit, 18
is a counter, 20 is a flip-flop (F/F), 2
1.22 is a sund gate, 23 is a phase comparator (PC
), 24 is a voltage controlled oscillator (VCXO), 25 is a frequency divider, 26 is a counter, 27 is a register, 28 is a frame control signal circuit, 29 is a frequency divider, 30 is a frame configuration circuit,
31 is a separation board, 32 is an AND gate, 33 is a register,
34 is a frequency divider, 35 is a counter, and 36 is a phase comparator (P
C), 37 is a voltage controlled oscillator (VCXO), 38 is a frequency divider, 39 is a frequency divider, 50 is a counter, 51 is a voltage controlled oscillator, 52 is a frequency divider, 53 is a counter, 54 is a difference circuit,
55 is a low-pass filter, and 56 is a D/A converter circuit. FU Kinoshita F
The formula of prisoner Ijt-Iodto E-Kai to Buddha 1-iu and Hokto] Kaya 4
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Claims (1)

[Claims] A transmitting side is provided with means for detecting the position of a synchronizing signal included in an image signal within a transmission frame period and transmitting the positional information together with the image signal; An image transmission device comprising: means for detecting the synchronization signal from position information; and means for performing phase synchronization with the synchronization signal detected by the detection means.