JPS62131552A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62131552A
JPS62131552A JP27218485A JP27218485A JPS62131552A JP S62131552 A JPS62131552 A JP S62131552A JP 27218485 A JP27218485 A JP 27218485A JP 27218485 A JP27218485 A JP 27218485A JP S62131552 A JPS62131552 A JP S62131552A
Authority
JP
Japan
Prior art keywords
semiconductor device
signal terminals
side surfaces
taken out
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27218485A
Other languages
Japanese (ja)
Inventor
Shinobu Takahama
忍 高浜
Akira Fujita
晃 藤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP27218485A priority Critical patent/JPS62131552A/en
Publication of JPS62131552A publication Critical patent/JPS62131552A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To implement high density packaging, by bending and taking out base signal terminals and emitter signal terminals from the side surfaces of a semiconductor device in the horizontal direction with respect to the attaching direction or from the horizontal direction of the side surfaces of the semiconductor device in the vertical direction, thereby omitting connecting wirings, and making it possible to perform printed wirings. CONSTITUTION:Base signal terminals 4a-4f and emitter signal terminals 5a-5f are bent and taken out of both side surfaces of a semiconductor device in the horizontal direction. Or the terminals are bent and taken out of the horizontal direction of both side surfaces of the semiconductor device toward the lower surface, i.e., in the vertical direction. The semiconductor device is fixed to a heat sink 6. The connection between the base semiconductor device and a control substrate 7 is performed by inserting the base signal terminals and the emitter signal terminals, which are taken out of the side surfaces of the semiconductor device, into a connector 8, which is fixed on the control substrate 7. The base signal terminals and the emitter signal terminals, which are bent and taken out of the side surfaces toward the lower surface, are directly soldered to the control substrate 7. Since the base signal terminals and the emitter signal terminals do not undergo interconnecting wiring and the like and are connected to the control substrate 7, high density packaging and improvement in workability can be implemented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、電力用半導体モジュール等の半導体装置の
信号端子の改良に、より高密疫実装を可能にした半導体
装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device that enables higher-density packaging in order to improve signal terminals of semiconductor devices such as power semiconductor modules.

〔従来の技術〕[Conventional technology]

第3図は従来の半導体装置の外形を示す斜視図であり、
以下ではインバータ用6素子入り電力用半導体モジュー
ルを例にして説明する。
FIG. 3 is a perspective view showing the external shape of a conventional semiconductor device.
In the following, a six-element power semiconductor module for an inverter will be explained as an example.

第3図において、1および2は主電極である正および負
の直流入力端子、3a〜3cは三相交流出力端子、41
〜4fはペース信号つ(1;子、5a〜5目よエミッタ
信号端子である。
In FIG. 3, 1 and 2 are main electrodes, which are positive and negative DC input terminals, 3a to 3c are three-phase AC output terminals, and 41
~4f are pace signal terminals (1; child, 5a~5th emitter signal terminals).

一最に電力用半導体装置は、小電流を流す信号端子と大
電流の流れる主電極とを有している。
First of all, a power semiconductor device has a signal terminal through which a small current flows and a main electrode through which a large current flows.

第3図に示す従来の半導体装置も例外ではなく、小電流
を流す信号端子としてベース信号端子4a〜4[お1び
−T−5ツタ信号端子5a〜5[を有ずろ。また大電流
の流れる主電極として正、負の直流入力端子1,2お上
び三相交流出力端子3a〜3cを有する。
The conventional semiconductor device shown in FIG. 3 is no exception, and has base signal terminals 4a to 4 [1 and -T-5 signal terminals 5a to 5] as signal terminals through which small currents flow. It also has positive and negative DC input terminals 1, 2 and three-phase AC output terminals 3a to 3c as main electrodes through which large current flows.

この半導体装置を使用ずろ際は、ベース43号端子4a
〜4[およびエミッタ1コ号幅1了5a〜5[を制御基
板と電気的に接続し、かつ正、負の1α流入力端子1,
2および三相交流出力端子33〜3cを、それぞれ外部
機器と配線時の抵抗およびインピーダンス等による損失
が少なくなるように電気的に接続する必要がある。
When using this semiconductor device, please contact the base No. 43 terminal 4a.
~4 [and emitter 1 width 1 ryo 5a ~ 5] are electrically connected to the control board, and positive and negative 1α flow input terminals 1,
It is necessary to electrically connect the two- and three-phase AC output terminals 33 to 3c to external equipment so that losses due to resistance, impedance, etc. during wiring are reduced.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

そこで、第3図の従来の半導体装置であるが2そのベー
ス43号端子11 t1〜4「お上びエミッタ信号端子
5Q〜5丁からの入力43号はスイッチング動作の場合
、集積回路(IC)または混成集積回路に上るパルス信
号であり、主電極に流れる電流に比べれば非常に小さい
。しかしながら、従来の半導体装置のベース45号端子
4a〜4【お、Lびエミッタ信号端子5a〜5fの形状
からすると、大電流を必要とする主電極である正、負の
直流入力端子1.2および三相交流出力端子3a〜3c
に近接させて小電流でよいベース信号端子48〜4fお
よびエミッタ信号端子5a〜5fと制御基板(図止せず
)とを接続配線する必要があるため高密度実装が困難で
あり、配線作業時に手間がかかる等の問題点があった。
Therefore, in the conventional semiconductor device shown in FIG. It is also a pulse signal that goes up to the hybrid integrated circuit, and is very small compared to the current flowing through the main electrode. From the perspective, positive and negative DC input terminals 1.2 and three-phase AC output terminals 3a to 3c are the main electrodes that require large currents.
Since it is necessary to connect and wire the base signal terminals 48 to 4f and emitter signal terminals 5a to 5f, which require a small current, to the control board (not shown) in close proximity to There were problems such as the amount of water required.

この発明は、上記のような問題点を解消するためになさ
れたもので、ベース信号端子およびエミ・ツク信号端子
への接続配線をなくし、プリント配線を可能にするとと
もに、高密度実装ができる半導体装置を得ることを目的
とする。
This invention was made in order to solve the above-mentioned problems, and it eliminates the connection wiring to the base signal terminal and the emitter signal terminal, making it possible to use printed wiring, and to create a semiconductor that can be mounted in high density. The purpose is to obtain equipment.

〔問題点を解決するための手段〕[Means for solving problems]

この発明にかかる半導体装置は、ベース49号端子およ
びエミッタ信号端子を半導体装置の側面から取付方向に
対して水平方向あるいは半導体装置の側面の水平方向か
ら垂直方向に曲げて取り出すようにしたものである。
In the semiconductor device according to the present invention, the base No. 49 terminal and the emitter signal terminal can be taken out from the side of the semiconductor device by bending them horizontally to the mounting direction or vertically from the horizontal direction of the side of the semiconductor device. .

〔作用〕[Effect]

この発明においては、その半導体装置の6tlJ 面よ
り水平方向、あるいは水平方向から垂直方向に曲げて取
り出しているため、基板との接続には基板に直付け、あ
るいはコネクタ等を使用したプリント配線が容易になる
ため接続配線が不要であり、かつ高密度実装が可能にな
る。
In this invention, since the semiconductor device is bent horizontally from the 6tlJ plane or bent vertically from the horizontal direction, it is easy to connect it to the board by directly attaching it to the board or by using printed wiring using a connector, etc. This eliminates the need for connection wiring and enables high-density packaging.

〔実施例〕〔Example〕

第1図、第2図はこの発明の一実施例をそれぞれ示す斜
視図で、第3図と同一符号は同じものを示すが、第1図
の実施例ではベース(ffi号端子4a〜4fおよびエ
ミッタ信号端子5a〜5「は半導体装置の両側向より水
平方向に取り出されており、第2図の実施例ではベース
信号端子4a〜4fおよびエミッタ信号端子58〜5f
が半導体装置の両側面より水平方向から下面に向けて、
すなわち垂直方向に曲げて取り出されている。そして、
これら半導体装置は放熱板6に固定されている。
1 and 2 are perspective views showing an embodiment of the present invention, and the same reference numerals as in FIG. 3 indicate the same parts, but in the embodiment of FIG. Emitter signal terminals 5a-5'' are taken out horizontally from both sides of the semiconductor device, and in the embodiment of FIG. 2, base signal terminals 4a-4f and emitter signal terminals 58-5f.
from both sides of the semiconductor device horizontally to the bottom surface,
That is, it is bent vertically and taken out. and,
These semiconductor devices are fixed to a heat sink 6.

第1図における半導体装置と制御基板7との接続は、半
導体装置の側面より取り出したベース信号端子48〜4
fおよびエミッタ信号端子58〜51を制御基板7上に
固着されたコネクタ8に差し込むことにより行う。
The connection between the semiconductor device and the control board 7 in FIG.
This is done by inserting the f and emitter signal terminals 58 to 51 into the connector 8 fixed on the control board 7.

また第2図におけろ半導体装置と制御基板7との接続は
、半導体装置の側面より下面に向けて曲げて取り出した
ベース信号端子4a〜4fおよびエミッタ信号端子58
〜5[を制御基板7に直に半田付は等をすることにより
行う。
In addition, in FIG. 2, the connection between the semiconductor device and the control board 7 is made by base signal terminals 4a to 4f and emitter signal terminals 58 bent downward from the side surface of the semiconductor device.
~5 [is performed by soldering, etc. directly to the control board 7.

上記のように、この実施例によれば、半導体装置はベー
ス信号端子4a〜4fおよびエミッタ信号端子58〜5
rを接続配線等をせずに制御基板7と接続するようにし
たため、高密度実装および作業性の向上を図ることも可
能である。
As described above, according to this embodiment, the semiconductor device has base signal terminals 4a to 4f and emitter signal terminals 58 to 5.
Since r is connected to the control board 7 without any connection wiring or the like, it is also possible to achieve high-density mounting and improve workability.

なお、上記実施例においては、インバータ用6素子入り
トランジスタモジュールについて説明したが、これはど
のような電力用半導体モジュールや電力用半導体装置で
あってもよく、上記実施例と同様の効果を奏することは
明らかである。
In the above embodiment, a six-element transistor module for an inverter has been described, but any power semiconductor module or power semiconductor device may be used, and the same effects as in the above embodiment can be achieved. is clear.

〔発明の効果〕〔Effect of the invention〕

この発明は以上説明したとおり、ベース信号端子および
工5ッタイ3号端子を半導体装置の両側面より水平方向
または水平方向から垂直方向に曲げて取り出すように構
成したので、制御基板への接続は直に行うことができる
。したがって、半導体装置と制御基板との高密度実装な
らびに作業性の向上が図れる効果がある。
As explained above, this invention is configured so that the base signal terminal and the terminal No. 3 of the connector are taken out from both sides of the semiconductor device in the horizontal direction or by bending from the horizontal direction to the vertical direction, so that they can be directly connected to the control board. can be done. Therefore, there is an effect that high-density packaging of semiconductor devices and control boards and improvement of workability can be achieved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図はこの発明の一実施例をそれぞれ示す半
導体装置と制御基板の接続過程を示す斜視図、第3図は
従来の半導体装置を示す斜視図である。 図において、1,2は直流入力端子、3a〜3cは三相
交流出力端子、41〜4目よベース(t−i号端子、5
a〜5fはエミッタ信号端子、6は力父熱板である。 なお、各図中の同一符号は同一まtコは相当部分を示す
。 代理人 大 岩 増 雄   (外2名)第1図 第2図 第3図
FIGS. 1 and 2 are perspective views showing a connection process between a semiconductor device and a control board, respectively showing one embodiment of the present invention, and FIG. 3 is a perspective view showing a conventional semiconductor device. In the figure, 1 and 2 are DC input terminals, 3a to 3c are three-phase AC output terminals, 41st to 4th are the base (t-i terminal, 5th
a to 5f are emitter signal terminals, and 6 is a power source heating plate. Note that the same reference numerals in each figure indicate corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 所要数の主電極および信号端子を備え、樹脂により封止
された半導体装置において、前記各信号端子を前記半導
体装置の側面から水平方向、または水平方向から垂直方
向に曲げて取り出したことを特徴とする半導体装置。
A semiconductor device comprising a required number of main electrodes and signal terminals and sealed with resin, characterized in that each of the signal terminals is taken out from a side surface of the semiconductor device by bending it horizontally or from the horizontal direction to the vertical direction. semiconductor devices.
JP27218485A 1985-12-03 1985-12-03 Semiconductor device Pending JPS62131552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27218485A JPS62131552A (en) 1985-12-03 1985-12-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27218485A JPS62131552A (en) 1985-12-03 1985-12-03 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62131552A true JPS62131552A (en) 1987-06-13

Family

ID=17510254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27218485A Pending JPS62131552A (en) 1985-12-03 1985-12-03 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62131552A (en)

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