JPS62130467A - Fast fourier transform device - Google Patents

Abstract

PURPOSE:To execute a fast Fourier transform with a buffer memory small in capacity by providing a selection part which selects whether a data after a butterfly arithmetic is to be stored at a buffer memory, or it is to be transferred to a butterfly arithmetic part at the next stage. CONSTITUTION:A pipe-line type fast Fourier transform (FFT) device is constituted with n-number stage of butterfly arithmetic parts 31, 32,..., 3n, buffer memories 41, 42,..., 4n provided between the butterfly arithmetic parts, and selectors 51a, 51b,..., 5n-1a, and 5n-1b consisting of selection circuits, and the FFT having data of N=2 is executed in a pipe-line manner. At the FFT device, the half of the data is directly transferred to the next stage at the first half, and all of the data are stored at the buffer memory at the latter half. By constituting a device in such a way, a perfect pipe-line operation can be realized even with a small buffer memory capacity, that is N/2.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a fast Fourier transform device that executes a fast Fourier transform (hereinafter referred to as FFT) operation in a pipeline format, and particularly relates to a fast Fourier transform device that executes a fast Fourier transform (hereinafter referred to as FFT) operation in a pipeline format. This relates to a circuit for transferring data.

[Conventional technology]

In conventional "FFT" devices, when performing high-speed processing, a butterfly operation unit and a buffer memory have been combined in a pipeline format.For example, when performing FFT on data with ■ = 21 points, as shown in Fig. 5. Like, n
The butterfly calculation units 11 to 1n of the stages and each butterfly calculation unit 11 to 1? During t, 2N words of backup memory 21~
The configuration was such that 2n-1 was provided. The buffer memory capacity is 2N words, which is twice the number of points.
This is to simultaneously write the calculation result at the previous stage and read out the data required at the next stage, thereby operating the pipeline by 1oos=1.

[Problem that the invention seeks to solve]

This type of conventional FFT device has a large buffer memory capacity. For example, if the number of points is 1024. The data word length per point (complex data) is 64 bits, each stage has a memory capacity of 2 x 1024 x 64 = 128 Kb. required each time. This poses a major obstacle in realizing an LSI for FFT operation with a reduced buffer memory, and is particularly difficult to realize when the number of points is large.

[Means for solving problems]

In order to solve the problems of the conventional art, the present invention provides a fast Fourier transform device in which a butterfly calculation unit and a pack memory are connected in a pipeline. Store the data later in the memory, or
It is characterized in that it includes a selection section that selects whether to transfer to the next-stage butterfly operation section.

[For production]

The present invention eliminates the need to increase the buffer memory capacity of each stage by providing a selection circuit for storing the data after the butterfly calculation in each stage in the buffer memory or directly transferring it to the butterfly calculation unit in the next stage. FFT can be performed without reducing the pipeline pumping rate. Examples will be described below based on the drawings.

〔Example〕

Figure 1 shows the first embodiment of the present invention, Vibly/type F.
This shows an FT device. The FFT of the data with the number of points N = 2" is performed by the n-stage butterfly calculation unit 3+, 3z, ・
. . . The butterfly calculation unit 31 is executed in a pipeline manner by 3M. Buffer memos +)4+1421..., 4n-+ are provided between .about.3m, each having a capacity of i. In addition, in order to control the flow of data, a butterfly calculation unit 31. ~5TL
Selector 5+a+ 51br -=, 5rL, which is composed of a selection circuit constituting a selection unit for selecting either the path connecting 411 to 4n-1 or the path directly connecting butterfly calculation units 61 and 3n. -1a
, 5n-+b are provided.

Next, the flow of data will be explained in order. First, FIG. 2 is a diagram showing the flow of data in FFT calculation, and shows the case where the number of points is 2-16. Third
FIGS. A to 5F are diagrams showing the flow and arrangement of data to explain the first embodiment, and show the progress of FFT calculation in the case of 24 points. Here 131-13
Reference numeral 4 indicates a butterfly calculation unit, and reference numerals 141 to 145 indicate buffer memories.

Note that the selector section is omitted because it only shows the flow of data. The capacity of the backup memory may be 2'/2=8 words. Furthermore, the broken line indicates the destination to which data will be transferred in the next cycle.

FIG. 3A shows the initial state. At the beginning of the first stage, a butterfly operation is performed using data Ao and A8 of frame A, and the execution result is stored in a buffer memory 141. Similarly, A1 and A9. A2 and A10゜A3 and 41
A butterfly operation is performed on the set of ill
It is then stored in the buffer memory 141. When the butterfly computation is completed for the total number of points A, the buffer memory 141 becomes full. Figure 3B shows this state.
It is. At this point, the butterfly operation is being performed on 44 and A12 in the first stage. The next state is shown in FIG. 6C, where the second stage butterfly calculation is started.

At this time, a butterfly operation is performed using data AO' stored in the buffer memory 141 and A4' for which the butterfly operation at the first stage has been completed. That is, the first stage calculation result A4' is stored in the buffer memory 14. The data is directly transferred to the second stage butterfly calculation unit without being stored in the data processing unit. On the other hand, another data A12' for which the first stage calculation has been completed will be stored after AD' in the buffer memory 141 is read out. This state is shown in FIG. 3C. Thereafter, in the same manner, in the first stage, A5 and A13. A6
and A14. Butterfly calculation is performed sequentially on the set of A7 and A15, and among the calculation results, A5', A6', A
7' is directly transferred to the second stage butterfly calculation section 132. On the other hand, the remaining A15'.

The data of A14' and A15' are stored in 41' of the buffer memory 141.

After A2' and A3' are read out, they are sequentially stored. The data arrangement at this point is shown in Figure 6.

In the sixth diagram, the butterfly operation is executed on the data BO and B8 of the next frame B in the first stage, and the buffer memory 141 has 8 (=7) of A8' to A15'.
) data are stored. Also, in the second stage A5'
and A7', and the backup memory 142 has AO' to A2', A4' to A
The next state in which 7' is stored is shown in FIG. 3E. In the second stage, a butterfly operation is performed on 9 AB' and A12' stored in the buffer memo 'J14+', and the first stage calculation result BO',
8B' is A12' and A8' of the buffer memory 141
is stored after being read. Similarly, A9' and A13', A10' and 114', A11'
and 415' are sequentially read out from the buffer memory 141 in pairs and the butterfly calculation is executed in the second stage, and the calculation results of the first stage of the power cylinder EV and B9', B12' and 810',
B3' and 811' are sequentially stored in the buffer memory 141. In this manner, in the second half of the frame, data is not directly transferred from the butterfly calculation unit 151 to the butterfly calculation unit 162, but all data is transferred to and from the buffer memory 14+. That is, two words of data are read out from the buffer memory 141 to the calculation unit 132, and two words of the calculation result of the butterfly calculation unit 131 are routed to the buffer memory 141.

, FIG. 6F shows the final state of the above. All of the data in the buffer memory 141 has been replaced by the data of frame B, and is restored to H in FIG. 6 of frame A, and the same calculations are repeated thereafter.

As explained above, in the first half of the frame, half of the data can be transferred directly to the next stage, and in the second half of the frame, all the data can be stored in the buffer memory. By doing this, complete pipeline operation can be realized with a buffer memory capacity of 2 and the conventional (2N). . . . Also, for the second and subsequent stages, there is no problem because the interval between the data required for the butterfly calculation gradually decreases as shown in FIG.

Next, a second embodiment of the present invention will be described.

The first embodiment is an example in which the present invention is applied to data transfer between the first stage and second stage butterfly calculation units.

The second embodiment shows an example in which the present invention is also applied to data transfer between subsequent stages. In this second embodiment, the buffer memory of each stage can be reduced to the memory capacity of the previous stage, making it possible to further reduce the memory capacity.

FIG. 4A to FIG. 4F show the data arrangement in the middle of the process.

The capacity of each buffer memory is gradually decreasing. First, FIG. 4A shows the same state as FIG. 5C. FIG. 4B shows the data arrangement at the time when the 4-word buffer memory 152 is full by the butterfly operation section in the second stage. FIG. 4C shows the next state. Data AO' and A2' required by the third stage butterfly operation section
are transferred from the buffer memory 152 and the second stage butterfly calculation unit 132, respectively. Thereafter, data transfer is performed in the same manner as shown in FIGS. 4D to 4F.

As explained above, the backup memory can rarely be reduced with each stage. Therefore, the total buffer memory capacity is 2 n-1+ 2tL-2+ , , , , + 22
+ 21 = 2? L-2, which enables a reduction of n-2 2 (?L-+) compared to the conventional total buffer memory capacity of 2X2 x (tb-1). For example, in the case of Voight number 2I0, the total buffer memory capacity can be reduced to about 1/18.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to perform FFT with a conventional buffer memory of A or less without reducing the efficiency of Vibry/9.

Therefore, L for FFT operation with built-in buffer memory
It becomes easy to realize SI. Built-in buffer memory improves the internal data transfer rate, further increasing the FFT execution speed.

[Brief explanation of drawings]

FIG. 1 shows the first embodiment of the present invention.
Iffi configuration diagram, Figure 2 is a diagram showing the data flow and arrangement in FFT calculation, but it is not necessary to explain the data flow, Figure 4
Figures A to 4F are block diagrams of an FFT device showing a second embodiment of the present invention, and diagrams showing the data flow and arrangement. Figure 5 shows a butterfly operation unit and a buffer memory combined in a vibrating format. It is a block diagram of the conventional FET @ arrangement. 11~1yt, 5+~5n, 13+~134: Butterfly operation section 2l-27L-+, 4+~4? l-+,
14+-14g, 15+-153: Buffer memory 51α, 51b to 5? ! -+α, 5? L-1b: Selector patent applicant Nippon Telegraph and Telephone Corporation agent Patent attorney Gobe Tamamushi (2 others) 31-3n
To butterfly operation section 41 4n-+ / to rough memory 514L
~5n-+a, 5+b -5n-+i+ Selector of FFT competition 1 showing the first embodiment of the present invention. The first embodiment of the present invention is explained in 3rd 141 to 143. Figure 4 shows the flow and arrangement of the FE device configuration I21 pumper.
figure

Claims (1)

[Scope of Claims] In a fast Fourier transform device in which a butterfly calculation unit and a buffer memory are connected in a pipeline, data after the butterfly calculation in the butterfly calculation unit is stored in the buffer memory between the butterfly calculation unit and the buffer memory. , a selection section for selecting whether to transfer data to a next-stage butterfly calculation section.