JPS62130021A - ガリウム砒素半導体集積回路 - Google Patents
ガリウム砒素半導体集積回路Info
- Publication number
- JPS62130021A JPS62130021A JP60268376A JP26837685A JPS62130021A JP S62130021 A JPS62130021 A JP S62130021A JP 60268376 A JP60268376 A JP 60268376A JP 26837685 A JP26837685 A JP 26837685A JP S62130021 A JPS62130021 A JP S62130021A
- Authority
- JP
- Japan
- Prior art keywords
- normally
- node
- mesfet
- gate
- gallium arsenide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 19
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 title claims description 12
- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims description 12
- 230000005669 field effect Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 230000004888 barrier function Effects 0.000 abstract description 9
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000002747 voluntary effect Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Electronic Switches (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60268376A JPS62130021A (ja) | 1985-11-30 | 1985-11-30 | ガリウム砒素半導体集積回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60268376A JPS62130021A (ja) | 1985-11-30 | 1985-11-30 | ガリウム砒素半導体集積回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62130021A true JPS62130021A (ja) | 1987-06-12 |
JPH0411130B2 JPH0411130B2 (enrdf_load_stackoverflow) | 1992-02-27 |
Family
ID=17457633
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60268376A Granted JPS62130021A (ja) | 1985-11-30 | 1985-11-30 | ガリウム砒素半導体集積回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62130021A (enrdf_load_stackoverflow) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09139657A (ja) * | 1995-11-13 | 1997-05-27 | Oki Electric Ind Co Ltd | ラッチ回路 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5492158U (enrdf_load_stackoverflow) * | 1977-12-13 | 1979-06-29 | ||
JPS58130620A (ja) * | 1982-01-29 | 1983-08-04 | Toshiba Corp | 論理回路 |
-
1985
- 1985-11-30 JP JP60268376A patent/JPS62130021A/ja active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5492158U (enrdf_load_stackoverflow) * | 1977-12-13 | 1979-06-29 | ||
JPS58130620A (ja) * | 1982-01-29 | 1983-08-04 | Toshiba Corp | 論理回路 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09139657A (ja) * | 1995-11-13 | 1997-05-27 | Oki Electric Ind Co Ltd | ラッチ回路 |
Also Published As
Publication number | Publication date |
---|---|
JPH0411130B2 (enrdf_load_stackoverflow) | 1992-02-27 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4491747A (en) | Logic circuit using depletion mode field effect switching transistors | |
US4682055A (en) | CFET inverter having equal output signal rise and fall times by adjustment of the pull-up and pull-down transconductances | |
US4400636A (en) | Threshold voltage tolerant logic | |
US5148244A (en) | Enhancement-fet and depletion-fet with different gate length formed in compound semiconductor substrate | |
US4469962A (en) | High-speed MESFET circuits using depletion mode MESFET signal transmission gates | |
EP0084844B1 (en) | Fet circuits | |
JPS62114325A (ja) | ゲ−ト回路 | |
US4654547A (en) | Balanced enhancement/depletion mode gallium arsenide buffer/comparator circuit | |
US4713559A (en) | Multiple input and multiple output or/and circuit | |
US4518871A (en) | Ga/As NOR/NAND gate circuit using enhancement mode FET's | |
US4489246A (en) | Field effect transistor logic circuit having high operating speed and low power consumption | |
US4716311A (en) | Direct coupled FET logic with super buffer output stage | |
US4725743A (en) | Two-stage digital logic circuits including an input switching stage and an output driving stage incorporating gallium arsenide FET devices | |
US4639621A (en) | Gallium arsenide gate array integrated circuit including DCFL NAND gate | |
US4712022A (en) | Multiple input OR-AND circuit for FET logic | |
JPS62109428A (ja) | 温度補償つき論理ゲ−ト | |
JPS62130021A (ja) | ガリウム砒素半導体集積回路 | |
US4996447A (en) | Field-effect transistor load circuit | |
EP0170134B1 (en) | Schottky diode field effect transistor logic circuit | |
JPH0247638Y2 (enrdf_load_stackoverflow) | ||
JPH0411131B2 (enrdf_load_stackoverflow) | ||
JPH0691456B2 (ja) | 広温度範囲mesfet論理回路 | |
EP0023210B1 (en) | Tri-state logic buffer circuit | |
JP2545712B2 (ja) | ガリウム砒素半導体集積回路 | |
JPH0254690B2 (enrdf_load_stackoverflow) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |