JPS6212985A - Fifo memory control device - Google Patents

Abstract

PURPOSE:To dynamically change the length of a word of an FiFo memory by providing a memory, a memory limit pointer, an FiFo memory writing pointer, an FiFo memory reading pointer, the first, the second, the third comparators, an FiFo memory managing part, and an FiFo memory size changing control circuit. CONSTITUTION:A value of a stack pointer 10 is compared with an FiFo memory limit pointer 12 by a comparator 15. When the value coincides with a value of the FiFo memory limit pointer 12, a stack memory area full information is outputted to an arithmetic processing part 2. The idle information and the full information of the FiFo memory area are managed by an FiFo memory managing part 6, and by using its output, the idle information and the full information of the FiFo memory area generated in a fixed time are counted by an FiFo memory size change control circuit 16. The value of the FiFo memory limit pointer 12 is changed so as to reduce the number of times of generation for a fixed time. Thereby, the size of the FiFo memory area can be dynamically changed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a FiFo memory control device for a part of a human power buffer of an arithmetic processing unit.

BACKGROUND OF THE INVENTION Many conventional arithmetic processing devices use FiFo memories in their input buffer sections, and the following literature can be cited as an example of this. “32-bit microprocessor with successive product announcements” 1 Nikkei Electronics April 3, 1984
0th issue PP6l-69゜Figure 2 is a block diagram of the FiFo memory control device of the conventional arithmetic processing unit manual buffer 1 section. 1 is a FiFo memory that buffers input data, 2 is an arithmetic processing unit, 3 is an input control circuit that controls data input to the FiFo memory, and 4 is a FiFo memory write that stores the write address of input data to the FiFo memory 1. 6 is a FiFo memory read pointer that stores the read address of the data in the FiFo memory 1 by the arithmetic processing unit 2; 6 is a FiFo memory management unit that manages the empty information and full information of the FiFo memory 1; Fi
It consists of a Fo memory empty flag and 8 FiFo memory full flags. Reference numeral 9 denotes a stack memory constituting a stack area used in the arithmetic processing operation of the arithmetic processing unit 2, and 1o represents a stack pointer that stores an address when the arithmetic processing unit 2 accesses the stack memory 9.

In the above configuration, the input control circuit 3 inputs data to the FiFo memory 1 regardless of the execution operation of the arithmetic processing section 2. The data input operation is stopped only when the FiFo memory full flag 8 is on and the FiFo memory is full. On the other hand, the arithmetic processing unit 2
Calculation is executed regardless of data input from the input terminal as long as the iFo memory empty flutter flag is in the state. FiF
oMemory write pointer 4 is set to Fi by input control circuit 3.
The FiFo memory read pointer 6 is incremented every time data is input to the Fo memory 1, and the FiFo memory read pointer 6 is incremented every time data is output from the FiFo memory 1 by the arithmetic processing unit 2, so that the FiFo memory 1 is a memory with a first-in, first-out function. Constructed as.

The FiFo memory management unit 6 manages the empty information and full information of the FiFo memory 1 by detecting the coincidence status between the FiFo memory write pointer 4 and the FiFo memory read pointer 6.

Problems to be Solved by the Invention However, in such a configuration, in order for the input data to be supplied to the FiFo memory 1 and the input data to be consumed by the arithmetic processing unit 2 to be performed without waiting operations, the FiFo memory 1 must be
It is necessary to set the word length appropriately. FiFo memory 1
If the word length of is too small, when the input data is consumed by the arithmetic processing section 2 at a high speed, the input data will disappear from the FiFo memory 1, and the arithmetic processing section 20 will frequently have to wait for input data. Furthermore, if the word length of the FiFo memory 1 is too large, bus transfers for data input will occur frequently, and path transfers for data output and arithmetic processing will be obstructed.

That is, although the quality of the word length setting of the FiFo memory 1 greatly affects the processing efficiency of the entire apparatus, there was a problem in that the word length of the FiFo memory 1 once set cannot be changed.

In view of the above problems, it is an object of the present invention to provide a FiFo memory control device that can dynamically change the word length of the FiFo memory so that the processing efficiency of the entire device is maximized.

Means for Solving the Problems The present invention provides a memory and an F for input data in the memory.
FiF that stores the final address of the iFo memory area
o a memory limit pointer and a FiFo memory write pointer that stores an input data write address to the memory;
FiFo that stores data read address from memory
a first comparator that compares the memory read pointer, a value of the FiFQ memory write pointer and a value of the FiFo memory limit pointer, and a second comparator that compares the value of the FiFo memory read pointer and the value of the FiFo memory limit pointer. a stack pointer that stores an access address to a stack memory area used for arithmetic processing in the memory; a third comparator that compares the value of the stack pointer with the value of the FiFo memory limit pointer;
A FiFo memory management unit that manages the Fo memory area;
FiFo that inputs the iFo memory management unit output and system clock to change the value of the FiFo memory limit pointer
This is a FiFo memory control device including a memory size change control circuit.

Operation The present invention has such a configuration, and uses the FiFo memory empty information and full information outputted by the FiFo memory management unit to the FiFo memory management unit.
o The memory size change control circuit counts.

Then, the FiFo memory limit pointer is changed depending on the number of FiFo memory excess/deficiency states that occur within a certain period of time.
Change iFo memory size. I can do this. Furthermore, by treating the FiFo memory area that is no longer needed as a stack memory area, it is possible to effectively utilize memory.

Embodiment FIG. 1 is a block diagram of a FiFo memory control device in an embodiment of the present invention. In FIG. 1, 2 is an arithmetic processing unit, 3 is an input control circuit, 4 is a FiFo memory write pointer, 6 is a FiFo memory read pointer, and 6 is a FiFo memory read pointer.
Memory management section, 7 is FiFo memory empty flag, 8 is Fi
Fo memory full flag, 10 is a stack pointer, and the above is the same as the configuration shown in FIG. 11 is memory, 1
2 is a FiFo memory limit pointer that stores the final address of the FiFo memory area for input data in the memory 11; 13 is a FiFo memory limit pointer that compares the values of the FiFo memory write pointer 4 and the FiFo memory limit pointer 12;
a first comparator that resets when the value of the memory write pointer 4 becomes greater than or equal to the value of the FiFo memory limit pointer 12;
14 is the value of FiFo memory read pointer 6 and FiFo
The value of the memory limit pointer 12 is compared and the value of the FiFo memory read pointer 5 is the value of the FiFo memory limit pointer 12.
A second comparator 15, which is reset when the value exceeds the value of
a third comparator that outputs stack area fullness information to the arithmetic processing unit 2 when the value matches the value of the memory limit pointer 12;
16 inputs the output of the empty flag 7 and the output of the full flag 8 of the FiFo memory, and the system clock, and counts the empty information and full information axis of the FiFo memory area that occur in a certain period of time,
This is a FiFo memory size change control circuit that changes the FiFo memory limit pointer 12.

The operation of this embodiment will be explained below. Input control circuit 3 is F
As long as iFo memory full flag 8 is off, memory 1
Assuming that there is an empty area in the FiFo memory area No. 1, input data is read and the FiFo memory write pointer 4 is incremented. The value of the FiFo memory write pointer 4, which is sequentially incremented, is compared with the FiFo memory limit pointer 12 by a comparator 13, and when it exceeds the value of the FiFo memory limit pointer 12, it is reset. Therefore, F
The iFo memory write pointer 4 repeats addresses from address 0 to the value of the FiFo memory limit pointer 12.

Further, as long as the FiFo memory empty flag 7 is off, the arithmetic processing unit 2 assumes that there is valid input data in the FiFo memory area of the memory 11, reads the data, and increments the FiFo memory read pointer 6. The value of the FiFo memory read pointer 6, which is sequentially incremented, is compared with the FiFo memory limit pointer 12 by a comparator 14, and when it exceeds the value of the FiFo memory limit pointer 12, it is reset.

Therefore, like the FiFo memory write pointer 4, the FiFo memory read pointer 5 repeats the addresses from address 0 to the value of the FiFo memory limit pointer 12. On the other hand, the area after the value of the FiFo memory limit pointer 12 in the memory 11 is used as a stack memory area when the arithmetic processing section 2 executes calculations using the stack pointer 10. The value of the stack pointer 10 is compared with the FiFo memory limit pointer 12 by the comparator 16, and if it matches the value of the FiFo memory limit pointer 12, stack memory area full information is output to the arithmetic processing unit 2. Empty information and full information of the FiFo memory area are managed by the yi and yo memory management unit 6, and using the output thereof, the FiFo memory size change control circuit 16 calculates the empty information and full information of the FiFo memory area that occur at a certain time. Count. In the counting results, if the number of occurrences of sky information is greater than the preset value, FiFo
The FiFo memory size change control circuit 16 controls to decrease the value of the memory limit pointer 12, and to increase the value of the FiFo memory limit pointer 12 when the number of occurrences of full information is greater than a preset value. However, Fi
The value of the stack pointer 1o is also input to the Fo memory size change control circuit 16, and if the value of the FiFo memory limit pointer 12 becomes larger than the value of the stack pointer 10 due to the change, the value of the stack pointer 10 increases, FiFo memory limit pointer 12 to be changed
Wait until the value is greater than or equal to , then change it. This can prevent data in the stack memory area from being destroyed.

As described above, according to this embodiment, the number of occurrences of empty information and the number of occurrences of full information in the FiFo memory area of the FiFo memory management unit 6 is counted by the FiFo memory size change control circuit 16, and the number of occurrences for a certain period of time is reduced. Like Fi
By changing the value of the Fo memory limit pointer 12, the size of the FiFo memory area can be dynamically changed.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the size of the FiFo memory area can be dynamically changed.

It is possible to set the optimal FiFo memory size for the target processing data. Furthermore, an unnecessary FiFo memory area can be used as a stack memory area, and memory can be used effectively. In particular, the ability to dynamically change the FiFo memory size is effective in cases where it is impossible or extremely difficult to change a circuit once created, such as an LSi circuit. The practical effects of the invention are significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a FiFo memory control device according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional FiFo memory control device. 2... Arithmetic processing unit, 3... Input control circuit, 4... FiFo memory write pointer, 6
...FiFo memory read pointer, 6...
...FiFo memory management unit, 1o...Stack pointer, 11...Memory, 12...
・FiFo memory limit pointer, 13...1st
Comparator, 14...Second comparator, 15...
...Third comparator, 16...FiFo memory size change control circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
figure

Claims (1)

[Claims] a memory, an arithmetic processing unit that sequentially reads and performs calculations on input data to the memory, an input control circuit that controls data input to the memory, and a final section of the memory that handles input data as a FiFo (first-in-first-out) memory; A FiFo memory limit pointer that stores the address, and a FiFo memory limit pointer that stores the address.
A FiF that is incremented every time data is input to the memory area and stores a data write address to the memory.
o The memory write pointer and the arithmetic processing section are FiFo
Fi that is incremented every time input data in a memory area is read and stores a data read address to the memory;
The value of the FiFo memory read pointer, the value of the FiFo memory write pointer, and the value of the FiFo memory limit pointer are compared, and when the value of the FiFo memory write pointer, which is sequentially incremented, is greater than or equal to the value of the FiFo memory limit pointer, the value of the FiFo memory limit pointer is a first comparator that resets a memory write pointer; and a first comparator that compares the value of the FiFo memory read pointer with the value of the FiFo memory limit pointer, such that the value of the sequentially incremented FiFo memory read pointer is equal to the value of the FiFo memory limit pointer. a second comparator that resets the FiFo memory read pointer when the FiFo memory read pointer is greater than or equal to the FiFo memory;
The area after the address indicated by the iFo memory limit pointer is treated as a stack memory area, and a stack pointer stores an address to be accessed by sequentially decrementing the stack memory area from the memory final address by the arithmetic processing unit, the value of the stack pointer, and the stack memory area. comparing the values of the FiFo memory limit pointers, and when the value of the stack pointer matches the value of the FiFo memory limit pointer;
a third comparator that outputs fullness information of the stack memory area to the arithmetic processing unit; and empty information of the FiFo memory area of the memory by inputting the value of the FiFo memory write pointer and the value of the FiFo memory read pointer; a FiFo memory management unit that manages full information; empty information of the FiFo memory management unit; empty information of the FiFo memory area that occurs at a certain time by inputting full information and a system clock;
A FiFo memory control device comprising: a FiFo memory size change control circuit that counts fullness information and changes the value of the FiFo memory limit pointer.