JPS62126476A - Device for improving picture quality - Google Patents

Abstract

PURPOSE:To improve picture quality by executing interpolation calculation for respective picture element near a border of image parts in accordance with the inclination of the border. CONSTITUTION:A border detecting circuit 11 detects the border of an image part of input image information DIN and an inclination detecting circuit 12 obtains respective horizontal and vertical inclination information DSP for picture elements on respective border points constituting the border based on the detected result. A correcting circuit 13 executes interpolation calculation for the image information of horizontal and vertical picture elements near respective border points in accordance with the inclination information DSP to correct the stair-like zigzag along the border line. Consequently, the picture quality can be improved.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A: Industrial field of application B: Outline of the invention C: Prior art (Fig. 13) D: Problem to be solved by the invention (Fig. 13) E: Means for solving the problem (Fig. 1): F: Effect (Fig. 1) Fig. 1) G Embodiment (Figs. 1 to 12) H Effects of the Invention A Industrial Application Field The present invention relates to an image quality improvement device, and in particular to computer graphics using raster display images, special effects devices for broadcasting, etc. It is suitable for application to.

B. Summary of the Invention The present invention, in computer graphics using raster display images, special effects equipment for broadcasting, etc., calculates the slope of the boundary of an image part and performs an interpolation operation for each pixel near the boundary according to this slope. By doing this, it is possible to obtain an image in which the jaggedness of the staircase shape that occurs along the boundary line is reduced.

C. Prior Art Conventionally, in computer graphics, special effects equipment for broadcasting, etc., image information represented by digital signals is processed and displayed on the display screen of a raster display type display made of, for example, a cathode ray tube (CRT). For example, images that have been rotated, enlarged, or reduced, or images are displayed three-dimensionally.

Since these display images are displayed pixel by pixel, as shown in FIG. A jagged staircase shape occurs depending on the inclination of the direction, and this causes an unsightly appearance to the operator in practical use.

Conventionally, as a method to reduce this phenomenon, a method has been adopted in which the display image signal as a whole is passed through a filter to blur the jaggedness of the staircase shape.

D Problems to be Solved by the Invention However, when the entire display image signal is filtered, there is a problem in that not only the boundary portion but the entire display image becomes blurred.

As a means to solve this problem, for example, Japanese Patent Application No. 60-891
There is a method disclosed in No. 76 specification. This method detects the boundary part from the image information of the displayed image, and based on this detection result, filters only the boundary part to blur the jagged part of the staircase shape, but in this case, the jagged part of the staircase shape There is also a drawback that an image of a boundary with no boundary, for example, a boundary without a horizontal or vertical direction, is unnecessarily blurred.

Another possibility is to find the slope of the boundary and change the filter shape according to this slope, but this would require an extremely complex and large-scale device configuration, making it difficult to put it into practical use. .

Furthermore, in the arithmetic processing process for creating a display image, it is possible to take into account image parts that are boundaries and filter those parts before creating the display image, but this would complicate the processing and require a device configuration. There was a problem that it became large and complicated.

The present invention has been made in consideration of the above points, and attempts to propose an image quality improvement device that can further improve image quality by reducing the step-shaped jaggedness that appears at the boundaries of image parts in a displayed image. It is something.

E Means for Solving the Problem In order to solve the problem, the present invention includes a boundary detection circuit 11 that detects the horizontal or vertical boundary of the image portion of the raster input image information 1DIN, and a boundary detection circuit 11 that detects the boundary in the horizontal or vertical direction of the image portion of the raster input image information 1DIN. An inclination detection circuit 12 that obtains information DSP of the boundary line in the horizontal or vertical direction at the boundary point from the boundary information of each point in a block consisting of a plurality of pixels including the boundary point based on
and a correction circuit 14 that corrects the jaggedness of the staircase shape along the boundary line based on the slope f+'JflaDsp.

The F-action boundary detection circuit 11 detects the boundaries of the image portion of the input image information DIN, and based on the detection results, the tilt detection circuit 12 calculates each tilt information in the horizontal or vertical direction for each pixel at each boundary point constituting the boundary. Get DSP.

The correction circuit 12 performs interpolation calculations on image information of pixels in the horizontal or vertical direction near each boundary point according to the tilt information DSP.
Correct the jaggedness of the staircase shape along the boundary line.

In this way, since it is possible to apply correction only to the step-shaped jagged portion along the boundary line according to the image quality, it is possible to obtain an image quality improving device that does not change the image quality of other portions.

Embodiment G With reference to the drawings below, an embodiment in which the present invention is applied to improve the horizontal image quality of a raster image signal in a special effects device for broadcasting will be described in detail.

In FIG. 1, lO indicates the image quality improvement device as a whole, and input image information DIN consisting of a raster image signal is input to a boundary detection circuit 11.

The boundary detection circuit 11 has a background flag memory 17, a front/back flag memory 18, and an image address memory 19. Each of the memories 17 to 19 has a memory area having the same number of pixels in the horizontal and vertical directions as the number of pixels in the vertical and horizontal directions of each pixel data of the input image information DIN. Background flag memory 1
7 and the front and back flag memories 18 are, for example, plane memories each consisting of one bit for each pixel. The image address memory 19 is, for example, a plain memory composed of 8 bits for each pixel.

Here, for example, as described above with reference to FIG. 13, image information of a converted image consisting of image portion 1 of the background portion, image portions 2 and 4 consisting of the front side of the original image, and image portion 3 consisting of the back side of the original image. When DIN is input, the boundary detection circuit 11 identifies a background image portion (hereinafter simply referred to as a background portion) 1 and other image portions 2 to 4 for each pixel data of the input image information DIN.

If the pixel data represents the background part 1, as shown in FIG. When representing parts 2 to 4, background flag data at the logical rlJ level is similarly stored in the corresponding memory area.

The background flag data is read out in correspondence with the input image 1?1 report DIN and is output to the differentiating circuit 20.

The differentiating circuit 20 determines whether the logic level of the background flag data that is sequentially read out is from "0" to "l" or from "1" to "0".
”, a detection output of logic “1” level is sent out. (As shown in FIG. 3, the input image information DIN
For each scan line of , the background part l and the other image part 2
Boundary detection data DSL that becomes logic level "1" is obtained at a timing corresponding to the horizontal boundary portion between 4 and 4.

On the other hand, in the front/back flag memory 18, when the normal vector on the curved surface of the image part constituting the input image information DIN points toward the front surface of the display image, the front/back flag memory 18 stores a logical level of "1" in the memory area corresponding to the pixel. Flag data is stored, and when the back side is facing the opposite side, a front/back flag data of logic level "0" is stored in the corresponding memory area. Thus,
As shown in FIG. 4, front and back flag data representing image portions 2 and 4 on the front side, image portion 3 and background portion 1 on the back side of the input image are obtained in the front and back flag data memory 18.

The differentiating circuit 21 operates in the same way as the differentiating circuit 20,
Boundary data DS2 that is logical rlJ is sent out at a timing corresponding to the horizontal boundary between the back side image parts 2 and 4, the back side image part 3, and the background part 1.

On the other hand, the image address memory 19 sequentially stores, for each pixel of input image information, the block address to which each pixel belongs.

In the case of this embodiment, the original image of the input image information DIN before image conversion is a predetermined number, for example, 16
The block is divided into 16 blocks, and each block is assigned a block address that gradually increments from one end to the other.

The image address data is read out in correspondence with the input image information DrN and output to the comparison circuit 22.

The comparison circuit 22 detects the pixel position where the content of the address data is extremely different from among the adjacent pixels, determines that it is a silhouette part, and sets the logic "1" at that timing.
” level is sent out.

Thus, the comparator circuit 22 outputs the logic r corresponding to the horizontal boundaries of the image portions 2.3 and 4, as shown in FIG.
Boundary data DS3 which becomes lJ is obtained.

The boundary detection circuit 11 outputs the logical sum of the boundary data DSL to DS3 via the OR circuit 24 to the first detection circuit 12 as boundary information DS representing all the boundaries of the image portions 1 to 5.

The tilt detection circuit 12 detects a plurality of pixels in the predetermined vertical and horizontal directions, for example, three pixels in the vertical direction and three pixels in the horizontal direction (
For example, the window matching circuit 25 has a read-only memory configuration and has a plurality of windows WO-1 to W3-2 (FIG. 9) in a matrix configuration consisting of 3×3 pixels. for,
For example, I of a 1 kilobit random access memory configuration.
Pixel data DM is supplied from an image data extracting section 24 comprising H delay circuits 26 and 27 and one-pixel delay circuits 28 to 33 having a register configuration, for example.

The boundary information DS is sequentially applied pixel by pixel to the 1-pixel delay circuits 28 and 29 of the window section 35, and thus the currently arrived pixel data DM3-3 is directly applied to the window matching circuit 25, as shown in FIG. , data DM3-2 from one sampling period before is given from the one pixel delay circuit 28, and further pixel data DM from two sampling periods before.
3-1 is given from the one-pixel delay circuit 29.

At the same time, pixel data DM2-3 from one horizontal scanning period ago is obtained at the output end of the IH delay circuit 26, and this is given to the window matching circuit 25, and from this pixel data DM2-3, Pixel data DM2-2 and DM2-1 from one sampling period and two sampling periods ago are applied to window matching circuit 25 from one pixel delay circuits 30 and 31, respectively.

Furthermore, at the same time, pixel data DMI-3 from two horizontal scanning periods ago is obtained at the output end of the IH delay circuit 27, and this is given to the window matching circuit 25, and from this pixel data DM1-3, respectively. Pixel data DMI-2 and DM1-1 from one sampling period and two sampling periods ago are applied to the window matching circuit 25 from one pixel delay circuits 32 and 33, respectively.

In this way, the slope detection circuit receives the boundary information DS that sequentially arrives.
The pixel data of 3×3 pixels are extracted by the pixel data extraction section 24 and simultaneously supplied to the window matching circuit 25 as pixel data.

The window matching circuit 25 converts the contents of the sequentially input pixel data DMI-1 to DM3-3 into the pixel data DM2-
Window WO-1-W3-2 for testing the inclination of boundary pixels with respect to the horizontal direction with 1 (Fig. 8) as the center.
(Figure 9), the window WO- whose contents match
Tilt information DPS corresponding to W1 to W3-2 is obtained.

As shown in FIG. 9(A), window WO-1 includes pixel data DM2 of pixel data DMI-1 to DM3-3.
When -1 is logic "0" (other pixel data is not determined), it is determined that the pixel data DM2-1 and the boundary line pixels do not match, and the slope information DSP of pattern "0" is output.

Moreover, as shown in FIG. 9(B), the window WO-2 is
When pixel data DMI-1, DM2-1, and DM3-1 are logic "1", it is determined that the boundary line is vertical with pixel data DM2-1 as the center, and the slope information DSP of pattern "0" is output. .

Furthermore, as shown in FIG. 9(C), the window Wl-1 is divided into the pixel data DM2-1 when the pixel data DMI-1 is the logic rOJ, and the pixel data DMI-2 and DM2-1 are the logic rlJ. It is determined that the pixels of the boundary line extend in a direction at an angle of +45° with respect to the horizontal direction, and the inclination information DSP of pattern "l" is output.

Furthermore, as shown in FIG. 9(D), the window W1-2 is a pixel when the pixel data DM3-1 is logic "0" and the pixel data DM2-1 and DM3-2 are logic "1". It is determined that the pixels of the boundary line extend in the direction of an angle of 145'' with respect to the horizontal direction with the data DM2-1 as the center, and the tilt information DSP of the pattern "l" is transmitted.

Further, in the window W2-1, as shown in FIG. 9(E), the pixel data DMI-1 and DMI-2 are logic "0".
And the pixel data DMI-3 and DM2-1 are logical "
1", it is determined that the pixels on the boundary line centering on the pixel data DM2-1 are tilted more gently with respect to the horizontal direction than in the case of FIG. 9(C), and the tilt information D of pattern "2" is determined.
Output SP.

Further, in the window W2-2, as shown in FIG. 9(F), the pixel data DM3-1 and DM3-2 are logic "0".
and pixel data DM2-1 and 0M3-3 are logical r
1J, it is determined that the pixels on the boundary line are tilted more gently than in the case of FIG. 9(D), and the tilt information DSP of pattern "2" is output.

Furthermore, as shown in FIG. 9(G), the window W3-1 is set to the ninth window when the pixel data DMI-1 to DMI-3 are logic "0" and the pixel data DM2-1 is logic rlJ.
It is determined that the slope is more favorable than in the case of FIG.

Furthermore, as shown in FIG. 9(H), the window W3-2 is opened when the pixel data DM3-1 to DM3-3 are logic "0" and the pixel data DM2-1 is logic "1". 9
It is determined that the slope is even gentler than in the case of FIG. 3(F), and the slope information DSP of pattern "3" is output.

The slope information DSP is prioritized in the order of "3" from rOJ, and the window matching circuit 25 outputs the slope information DSP of pattern "3" by the window W3-1, for example, and outputs the slope information DSP of the pattern "3" by the window W2-2. When the slope information DSP of pattern "2" is outputted by, pattern "2" is outputted as the slope information DSP.

For example, when boundary information IDs as shown in FIG. 10 are sequentially input to the slope detection circuit 12, pixel data DMI-
1 to DM3-3 are extracted while moving sequentially in the direction of arrow a.

For example, pixel data DMI-1-DM at position PA
3-3 are all logic "0" and match the window WO-1 of the window matching circuit 25. Therefore, the tilt detection circuit 12 uses the pattern "0" as the tilt emotion DSP.
Output.

Furthermore, during the period from position PA to position PB, the pixel data DM2-1 becomes logic "0" and the windows wo-i match, so the tilt detection circuit 12 continues to output the tilt information DSP of the pattern rOJ during this period.

Eventually, at position PH, pixel data DM2-1 becomes logic "1", and other pixel data DM1-1 to DM1
~3 and 0M2-2~DM3-3 are logical rOJ,
After losing the windows W3-1 and W3-2, the window matching circuit 25 sends out the slope information DSP of pattern "3".

Further, between the position PB and the position PC, the image data DM2-1 are all logic "0", and the window matching circuit 25 outputs the Ill-free information DSP of the pattern rOJ.

Furthermore, at position PC, inclination information DSP of pattern "3" is outputted in the same manner as position iPB, and subsequently, inclination information IHDSP of pattern rOJ is outputted between position PC and position iPD.

Eventually, at position PD, pixel data DM2-1 and 0M3-3 are logic "1" and other pixel data DM
When I-1 to DMI-3 and 0M2-2 to DM3-2 become logic "0", pattern "3" is output from window W3-1.
The tilt information DSP of pattern "2" is output from the window W2-2. At this time, the tilt detection circuit 12 outputs the tilt information DSP of pattern "2" based on the priority order.

Subsequently, the tilt detection circuit 12 outputs tilt information DSP of pattern "0" from position PD to position PE, and then transmits tilt information of pattern "2" at position PE.

Furthermore, after outputting the slope information DSP of pattern "0" from position PE to position iPF, at position PF, pixel data DM2-1 and 0M3-2 are logic "1", and other pixel data DMI-1 to DM1 -3.0M2-2~DM3
-1 and 0M3-3 become logical rOJ, the window W
1-2 and window W3-1. , at this time, the window W1-2 outputs the slope information ID5P of the pattern rlJ, and the window W3-1 outputs the slope information DSP of the pattern "3". At this time, the window matching circuit 12 selects the slope information 11 of pattern "1" according to the priority order.
Output DsP.

Thus, as shown in FIG. 11, patterns "0", "3", "3", "2", "2", "1
”, “1”, “1” slope information DSP is sequentially sent to the correction circuit 1.
Sent on 3rd.

The correction circuit 13 includes an interpolation coefficient generation circuit 41, a delay circuit 46 made of, for example, a random access memory, a latch circuit 42 that performs a latch operation in response to a control signal Sl sent from the interpolation coefficient generation circuit 31, and an interpolation coefficient generation circuit 41. The weighting output from the generation circuit 31 is made up of multiplier circuits 43 and 44 that perform weighting operations according to the data D and DB, respectively, and an adder circuit 45 that adds the output j of the multiplier circuits 33 and 34. Ru.

The interpolation coefficient generation circuit 41 is composed of, for example, a read-only memory, and weights the control signal si and each pixel information of the input image DIH in accordance with the slope information DSP centered on each pixel of the input image information DIN that is input sequentially. outputs to data DA and DB.

The delay circuit 46 delays the input image information IIN for a predetermined time so that each pixel information of the human image information DIN is synchronized with the weighting of the corresponding pixel in the multiplication circuits 43 and 44 with the data DA and DB.

The latch circuit 42 performs a latch operation based on the control signal Sl, and stops the latch operation in response to input of slope information DSP of the pattern rOJ to the interpolation coefficient generation circuit 41, for example.

As a result, the input image information DIN inputted via the delay circuit 46 is not inputted to the multiplication circuit 43, and the multiplication circuit 44
Is there a restriction on the state where it is only entered? 'Ill be.

On the other hand, the slope information of patterns "1", "2" and "3" II)
When SP is input to the interpolation coefficient generation circuit 41, the latch circuit 42 performs a latch operation in response.

In the case of pattern rlJ, the latch circuit 42 maintains the latch operation until pixel information delayed by one pixel from the latched pixel information is output from the delay circuit 46, and continues to output the latched pixel information to the multiplication circuit 43 during this time. .

Further, in the case of patterns "2" and "3", the latch circuit 42
maintains the latch operation until pixel information delayed by 2 pixels and 3 pixels, respectively, is output from the delay circuit 46;
During this time, the latched pixel information continues to be output to the multiplication circuit 43.

On the other hand, the multiplication circuit 44 multiplies the pixel information DIN input via the delay circuit 46 by a coefficient, and adds the multiplication output as the pixel information DN. Output to circuit 45.

Similarly, the multiplier circuit 43 multiplies the pixel information input via the latch circuit 42 by a coefficient for weighting data DA, and outputs the multiplication output to the adder circuit 45 as pixel information DM.

The adder circuit 45 adds the pixel information DM and DN and outputs the pixel information Do.

For example, as shown in FIG. 11, when a pattern "0" is input as the slope information DSP at the timing of the pixel information DrN1, the interpolation coefficient generation circuit 41 uses the data DB for weighting.
At the same time, the latch operation of the latch circuit 42 is stopped by the control signal S1.

As a result, the pixel information D input via the delay circuit 46
INI is not input to the multiplication circuit 43, but only to the multiplication circuit 44.

The multiplication circuit 44 weights the pixel information DIN at the timing of the next pixel of the pixel information DINI using the coefficient of the data DB.
1" and sends out the multiplied output as pixel information DN.

This operation is repeated at the timing of each pixel information as long as the pattern "0" continues to be input as the slope information 11DsP. As a result, the adder circuit 45 outputs the pixel information DN (=DIN1) of the multiplier circuit 44 as the pixel information flDo, and until a pattern other than the pattern "0" is obtained as the slope information DSP, the pixels of the input pixel information DIN The information DrN1 is sequentially output without being subjected to any correction.

Eventually, at the timing of pixel information DIN2, the tilt feeling! ID
When pattern "3" is input as 5P, the latch circuit 42 selects four pixels DIN2 and DIN by the control signal S1.
3. Latch operation is performed between DIN4 and DIN5. At the same time, the interpolation coefficient generation circuit 41 weights the pixel information DIN2, DIN3, DIN4, DIN as data DA.
At the timing of 5, the coefficients rOJ, r3/4J, r2/
4J, rl/4J, and the weighting is based on data D.
As B, for example, similarly, pixel ends fgDIN2 to DIN
5, coefficients “1”, rl/4J, “2/4”, r
Sends 3/4J.

Therefore, pixel information DIN2, DIN3, DIN4, DI
At the timing of N5, the coefficient "1" is output from the multiplication circuit 44.
, rl/4J, r2/4J, r3/4. J-weighted pixel information DIN2, DIN3, DIN
4. At the same time that DIN5 is output as pixel information DN, pixel information DM obtained by adding a coefficient rOJ to pixel information DIN2 latched in the latch circuit 42 is obtained from the multiplication circuit 43, and this is added in the addition circuit 45.

As a result, pixel information Do (=DM+D
N), pixel information D consisting of pixel information D02 to DO5 expressed by the following formula % formula % (1)
Output o sequentially.

Here, for example, as shown in FIG. 12(A), pixel information D
When IN2 represents black and pixel information DIN3 to DIN5 represent white, the displayed image of pixel information D02 to D05 gradually becomes white from black, as shown in FIG. 12(B). , and the border line becomes blurred.

Furthermore, as shown in FIG. 11, pixel information D! When pattern "2" is input as the slope information DSP of N6, the latch circuit 42 inputs the three pixel ends IDIN6, DIN7, DIN7.
Pixel information DIN6 is latched during IN8. At the same time, at the timing of pixel information DIN6, DIN7, and DrN8, the interpolation coefficient generation circuit 41 sequentially sends coefficients "0", r2/3J, and "1/3" as weighted data DA, and Sequential coefficients “l” and r as data DB
Send l/3J and r2/3J.

As a result, the addition circuit 45 sequentially outputs pixel information DO consisting of pixel information 006 to DO8 of the following formula % (5) in correspondence to pixel information DIN6 to DrN8.

For example, as shown in FIG. 12(A), the pixel information DIN6 represents the black part of the display image, and the pixel information DIN6
? and when representing the white part of the DIN8 display image, the first
As shown in FIG. 2(C), the displayed image of the pixel information DO6 to DO8 changes from black to white more rapidly than when the tilt information DSP is "3".

Furthermore, as shown in FIG. 11, when the pattern "1" is input as the slope information DSP of the pixel information DIN9, the latch circuit 42 latches the pixel information DIN9 between the two pixel information DIN9 and DINIO. At the same time, at the timing of pixel information DIN9 and DINlo, the interpolation coefficient generation circuit 41 weights data DA such as rOJ,
rl/2'' and weighting is done by data DB.
For example, "l" and rL/2J are sent out sequentially.

Therefore, the adder circuit 45 inputs the pixel information DIN9 and DINIO.
Corresponding to the following formula % formula % (8) Pixel II! Pixel information D consisting of DO9 and DOIO
Output O sequentially.

For example, as shown in FIG. 12(A), the pixel information DIN9 represents the black part of the display image, and the pixel information DI
When NIQ represents the white part of the displayed image, it is shown in Figure 12 (
As shown in D), the displayed image with pixel information DO9 and Dolo is more abrupt than when the tilt information DSP is "2".
It will go from black to white.

In the above configuration, for example, as shown in FIG. 13, an image portion 1 of the background portion and an image portion 3 consisting of the surface of the original image
When the pixel information DIN of the converted image composed of Data is obtained in background flag data memory 17.

Furthermore, the front and back flag data memory 18 obtains front and back flag data for identifying front side image portions 2 and 4 as shown in FIG. 4 and other image portions. In the image address memory 19, block addresses constituting each pixel as shown in FIG. 7 are obtained.

Based on the contents of these memories 17 to 19, boundary information DS for the horizontal direction in which the pixels at the boundary points of each image portion 1 to 5 are set to logic "1" is displayed in the inclination detection circuit 1 in the order of raster display.
2 is output.

In the tilt detection circuit 12, the boundary information DS is the pixel DMI-
After conversion into pixel data DM2-1 to DM3-3, a slope information II) SP representing a horizontal slope centered on pixel data DM2-1 is obtained using windows WO-1-W3-2 shown in FIG.

The tilt information DSP is sequentially outputted to the correction circuit 13, and the correction circuit 13 outputs new pixel information Do in which each pixel information of the input image information DIN is weighted based on the tilt information DSP.

For example, in the portions of positions PB and PC in FIG. 1O, the tilt information DSP is pattern "3" and
As shown in Figure 2 (B), the image quality gradually changes.

Furthermore, in the iPD part, the slope information DSP is the pattern "
2'', and as shown in FIG. 12(C), the image quality appears to change more abruptly than in the above case. Furthermore, in the portions of positions PE and PF, the tilt information DSP is pattern r.
lJ, and as shown in FIG. 12(D), weighting is applied so that the image quality changes more rapidly than in the above case.

Thus, for example, if the boundary line is continuous only in the horizontal or vertical direction, the slope information ID5P is the pattern rOJ.
Therefore, the pixel information of the input image information DIN is output without being weighted in any way. On the other hand, if the boundary line has an inclination with respect to the horizontal direction, the inclination information DSP
Weighting is performed only on pixels near the boundary line of the input image DIN according to the contents of the input image DIN, so that the step-shaped jaggedness that occurs along the boundary line can be corrected to a gentle change.

According to the above configuration, by applying correction according to the slope of the boundary line, only the jagged part of the staircase shape that occurs along the boundary line can be corrected, without affecting the image quality of other image parts. It is possible to obtain an image quality improvement device with a simple configuration that can improve image quality.

In the above-described embodiment, the image quality is improved in the horizontal direction, but instead of or at the same time, the image quality can also be improved in the vertical direction. In this case, instead of obtaining vertical tilt information and correcting the vertical pixel information based on this, the vertical pixel information may be corrected based on the horizontal tilt information.

Further, in the above embodiment, windows W〇-1 to W3
-2, which has a size of 3 pixels in the horizontal direction and 3 pixels in the vertical direction, but the window size is not limited to this and may be wider.

H Effects of the Invention As described above, according to the present invention, by determining the slope of the boundary line of an image part and performing an interpolation operation for each pixel near the boundary according to this slope, It is possible to easily obtain an image quality improvement device that corrects the jaggedness of the staircase shape into a smooth change, thereby leaving the image quality of other parts unchanged.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the image quality improvement device according to the present invention, FIGS. 2 and 3 are route maps for explaining background flag data, and FIGS. 4 and 5 are for explaining front and back flag data. Figures 6 and 7 are route maps for explaining image address data, Figure 8 is a route map for explaining matrix data, Figure 9 is a route map for explaining windows, and Figure 10 is a route map for explaining window information. The figure is a route map to explain the operation of the wind matching circuit, Figures 11 and 12 are route maps to explain the operation of the correction circuit, and Figure 13 is an explanation of the step-shaped jaggedness that occurs along the boundary line. This is a route map provided for. l, 2.3.4...Image part, 5...
Boundary line, 11... Boundary detection circuit, 12...
...Tilt detection circuit, 13...Correction circuit, 17.
...Background flag memory, 18...Front and back flag memory, 19...Image address memory, 2
0.21...differentiation circuit, 22...comparison circuit, 25...window matching circuit, 26
．． 27...IH delay circuit, 28-33...
...1 pixel delay circuit, 33.34...multiplication circuit, 35...addition circuit.

Claims (1)

[Claims] A boundary detection circuit that detects a horizontal or vertical boundary of an image portion of raster input image information, and each point in a block consisting of a plurality of pixels including a boundary point based on the boundary detection output. and a correction circuit that corrects the jaggedness of the staircase shape along the boundary line based on the slope information. Featured image quality improvement device.