JP2825927B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus configured to form a basic image corresponding to an original image and a pattern image on the periphery of the basic image. About.

[Related Art] A basic image is a reproduced image obtained by reproducing the original image or a converted image obtained by performing a conversion process on the original image to make the original image thinner or thicker. Conventionally, image processing for forming a pattern image such as a border image or a shadow image has been performed.

By this type of image processing, an image having an excellent decorative effect can be formed.

[Problems to be Solved by the Invention] In order to perform the above-described image processing, necessary pixel data is written to a frame memory each time, and data obtained by performing arithmetic processing using a CPU is taken out. The basic image and the pattern image are formed based on. For this reason,
The configuration of the apparatus is complicated, and it is not possible to form an image in real time.

Slightly, a black and white binary digital copier performs the real-time shadow shading processing in real time.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image processing apparatus which can obtain a basic image and a pattern image for a multi-valued image in real time by using a simple structure without using a frame memory and at a low manufacturing cost.

[Means for Solving the Problems] The object of the present invention is to provide a line memory in which image data of a binarized and extracted original image is stored, and
At least one of a reproduced image forming unit and a converted image forming unit, and at least one of a border image forming unit and a shadow image forming unit for forming a pattern image, a reproduced image, a converted image,
This is achieved by providing a coloring processing means for selectively performing coloring processing on the border image and the shadow image, respectively, and performing a matrix logical operation processing of these means in real time.

[Operation] Based on the image data of the binarized and extracted original image read from the line memory, a reproduced image of the original image or a converted image with the original image length changed is formed as a basic image. A border image or a shadow image is formed as a pattern image on the periphery of the basic image.

Then, coloring processing is selectively performed on the reproduced image, the converted image, the border image, and the shadow image by the coloring processing means.

Matrix logical operation processing of reproduction image formation, conversion image formation, border image formation, shadow image formation, and coloring processing is performed in real time.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration common to each embodiment of the present invention, wherein 1 is an image reading section, 2 is an image processing section,
Reference numeral denotes an image recording unit. The image processing unit 2 is connected to the image reading unit 1, and the image recording unit 3 is connected to the image processing unit 2.

A first embodiment will be described with reference to the drawings. In the first embodiment, a converted image is used as a basic image, and a border image is formed as a pattern image.

FIG. 2 is a block diagram showing the overall configuration of the first embodiment. Reference numeral 4 denotes a line memory, 5 denotes an image processing unit, and 6 denotes a color processing unit. Binary data) is input to the line memory 4 and the line memory 4
Is connected to the image processing unit 5, the color processing unit 6 is connected to the image processing unit 5, and the image data is input to the color processing unit 6.

FIG. 3 shows a line memory 4 commonly used in each embodiment.
In the embodiment, the NPD42 made by NEC is used as the memory 4 in the embodiment.
505C is used.

As shown in the figure, binary data 1bit is input to pin D _0in, pin D _1out pin D _0Out is connected to pin D _1in is connected to pin D _2in. Hereinafter, the same connection is made,
Pin D _n-2out is connected to pin D _n-1in .

In this way, the output of the line memory 4 includes data for n-1 lines.

FIG. 4 is a circuit diagram showing the configuration of the image processing unit according to the first embodiment, in which 8-1 to 8-n are AND circuits, 9
Is a selector, 10 is a shift register, 11 is a selector, 12 is a mode selector, 13 is a selector, 14 is a shift register,
15 is a selector, 16 is a mode selector, 17 is an inverting circuit, 18
Is an AND circuit, and 20 is a control register.

As shown in FIG. 4, the output terminal of the line memory is connected to the selector 13, and is connected to the selector 9 via the AND circuits 8-1 to 8-n.

The output terminal of the selector 9 is a shift register 10 and an AND
Connected to the input terminal of the selector 11 via the circuit section 10A,
Output terminals of the selector 11 are connected to the mode selectors 12 and 16, respectively, and are also connected to the mode selectors 12 and 16 via the inverting circuit 17 and the AND circuit 18.

The output terminal of the selector 13 is connected to the input terminal of the selector 15 via the shift register 14, and the output terminal of the selector 15 is connected to the input terminal of the AND circuit 18 and the mode selectors 12 and 16, respectively. ing.

The output terminal of the control register 20 is connected to the selector 9, the selector 11, the selector 13, the selector 15, and the mode selectors 12, 16.

The AND circuits 8-1 to 8 -n input signals corresponding to the data thinning amount in the sub-scanning direction to the selector 9, and the control register 20 sets the data thinning amount. Selects the set thinning amount and inputs it to the shift register 10.

The output of the shift register 10 is composed of a plurality of AND circuits corresponding to the amount of narrowing in the main scanning direction in the same manner as described above.
The circuit unit 10A is provided, and the thinning amount set by the control register 20 is selected by the selector 11.

Data from the line memory is corrected for misalignment via the selector 13, shift register 14, and selector 15, and the output signal from the output terminal of the selector 15 is
Output in synchronization with the 11 output signals.

The signals corresponding to the mode set in the control register 20 are selected by the mode selectors 12 and 16, and MASK1, MASK2
Is output to the coloring unit.

FIG. 11 is an explanatory diagram of image processing in the image processing unit, and FIG.
Denotes an original image, and 22 to 24 denote processed images. Such a processed image is input to the mode selectors 12 and 16 described above.

FIG. 5 is a circuit diagram showing a configuration of a coloring processing unit according to the first embodiment. In FIG. 5, 25 is a data register, 26 is a data register, 27 is a control register, 28 is a color conversion selector,
29 is a contour selector, 30 is a processing selector, and 31 is an OR circuit. As shown in FIG.
And a processing selector 30, a contour selector 29 is connected to the color conversion selector 28, and a processing selector 30 is connected to the contour selector 29.

Further, a color conversion selector 28 is connected to the data register 25, a contour selector 29 is connected to the data register 26, and an output terminal of the control register 27 is connected to the color conversion selector 28 and the processing selector 30. The output terminal of the OR circuit 31 to which MASK1 is input to the contour selector 29 and to which MASK1 and MASK2 are input is connected to the processing selector 30.

According to the control register 27, the selector 28 sets MASK1 to “H”.
At this time, any one of the image data and the color data in the data register 24 is selected.

When MASK1 is “L” and MASK2 is “H”, the contour selector 29
Selects the data from the data register 26.
When MASK1 is "L" and MASK2 is also "L", erase data is selected.

When the circuit is ON, the data selected by the selector 28 or the data or erase data selected by the contour selector 29 is output from the processing selector 30, and when the circuit is OFF, the image data is processed. Selector 30
Output from

FIG. 6 is an explanatory diagram showing an original image in the first embodiment, and FIGS. 7 to 10 are explanatory diagrams showing images processed and formed in the first embodiment. In these figures, 35 is the original image,
36 is a basic image formed corresponding to the original image, 36a is a basic image subjected to color processing, 37 is a pattern image subjected to color processing, and in the first embodiment, a bag character is used as the pattern image. A pattern image is formed. Reference numerals 38 and 39 denote erase processing areas, and stains existing in the background of the original image have been removed by the erase processing.

The images shown in FIGS. 7 and 8 are formed when MASK1 is a thinning signal and MASK2 is a signal other than the thinning signal, and the images shown in FIGS. 9 and 10 are both MASK1 and MASK2. It is formed in the case of a thinning signal. When both MASK1 and MASK2 are contour signals, the basic image 36a in FIG. 8 is an erased image.

Next, a second embodiment will be described with reference to the drawings. In the second embodiment, a reproduced image is used as a basic image, and a shadow image is formed as a pattern image.

FIG. 12 is a block diagram showing the overall configuration of the second embodiment. 4 is a line memory, 5 is an image processing unit, 6 is a color processing unit, and binary data is input to the image processing unit 5. The image processing unit 5 and the line memory 4 are connected to each other, a color processing unit 6 is connected to the image processing unit 5, image data is input to the color processing unit 6, and processing data is output from the color processing unit 6. It has become to be.

The same line memory as that of the third embodiment shown in FIG. 23 is used.

FIG. 13 is a circuit diagram showing the configuration of an image processing unit according to the second embodiment, where 41 is a shaded width selector, 42 is a mode selector,
43 is a data register, 44 is a decrement calculator, 45 is a data shift, 46 is a selector, 47 is a shadow detection comparator, 48 is a selector, 49 is a selector, 50 is a selector, 51 is a delay register, 52 is an inverting circuit, 53 Is an AND circuit.

As shown in FIG. 13, the output terminal of the line memory is input to the decrement operation unit 44, the data shifter 45, the selector 46, and the shadow detection comparator 47, and the output terminal of the shadow width selector 41 is connected to the selector 48 and the selector 48. The input 1-bit data is connected to the AND circuit 53 via the data shifter 45, the selector 48, and the inverting circuit 52.

The data register 43 and the decrement operation unit 44 are connected to the selector 48, and the output terminal of the selector 48 and the data shifter
The output terminal 45 is connected to the input terminal of the selector 50, and the output terminal of the selector 50 is connected to the input terminal of the delay register 51.

The output terminal of the selector 46 and the output terminal of the shadow detection comparator 47 are connected to the input terminal of
Is connected to the input terminal of the AND circuit 53 described above,
The output terminal of mode selector 42 is connected to selector 49 and selector
Connected to 50.

According to the select signal from the mode selector 42, the selector 49 selects the signal from the shadow detection comparator 47,
Selects the signal from the selector 48. Shadow width selector 41
Sets the shadow width value (max2 ^n-1 -1).

At the same time as the input 1-bit data is input, the data of the previous line is fetched from the line memory, and when there is input 1-bit data, the selector 48 selects the data of the shaded width selector 41 and passes through the selector 50 and the delay register 51 And input it to the line memory. This data is stored in the delay register
Since one clock is delayed at 51, the address is shifted by one address with respect to the memory, and is shifted 45 degrees to the lower right.

At this time, the signal supplied to the coloring processor is MASK1
The state becomes “H” and MASK2 “L”.

When the data of the previous line is fetched from the line memory and there is no input 1 bit, the data of the line memory is decremented by 1 by the decrement calculator 44. In this case, if the data in the line memory is not zero, the selector 48,
Data is input to the line memory via the selector 50 and the delay register 51. When the data in the line memory is zero, all0 data in the data register 42 is input to the line memory.

At this time, since the input 1-bit data is "L" in the signal output to the coloring processing unit, MASK1 becomes "L" and the shadow detection comparator 47
When non-zero data is output from, MASK2 becomes "H".

FIG. 15 is an explanatory diagram showing an original image in the second embodiment.
FIG. 16 to FIG. 19 are explanatory diagrams showing images processed and formed in the second embodiment. In these figures, 35 is an original image, 36 is a basic image formed corresponding to the original image, 36a is a basic image subjected to coloring processing, 37 is a pattern image subjected to coloring processing, In the second embodiment, a shadow image is formed as a pattern image.

In the operation of the image processing unit 5 of the second embodiment described above, the above-described image formation of FIGS. 16 and 17 is performed.

FIG. 20 is an explanatory diagram showing the state of the memory when performing the image formation shown in FIGS. 18 and 19.

The image formation in FIG. 18 and FIG. 19 is performed as follows.

The selector 49 selects the signal from the selector 46 and the selector 50 selects the signal from the data shifter 445 according to the select signal from the mode selector 42. The input of the selector 46 is selected by the shadow width selector 41.

The data from the line memory is selected by the selector 46, and the data is shifted and the input 1-bit data is input to the LSB. The data of the data shifter 45 is supplied to the line memory via the selector 50 and the delay register 51.

Since this data is delayed by one clock in the delay register 51, it is delayed by one data with respect to the memory.
Off by 45 degrees. The content of the data is line data for n-1 minutes. If input 1-bit data exists, MASK1 becomes "H" and MASK2 becomes "L".

If there is no input 1-bit data, MASK2 becomes "H" if the selected data in the line memory is not zero, and MASK2 becomes "L" if the data in the line memory is zero and MAS
K1 also becomes “L”.

By repeating the above processing, the images shown in FIGS. 18 and 19 are formed.

FIG. 21 is an explanatory diagram showing the state of the memory when performing the image formation shown in FIGS. 18 and 19.

FIG. 14 is a circuit diagram showing the configuration of a color processing unit according to the second embodiment. In FIG. 14, reference numeral 55 denotes a color conversion data register;
Is a shaded data register, 57 is a control register, 58 is a color conversion selector, 59 is a shaded selector, and 60 is a processing selector. As shown in the figure, a color conversion selector 58 is connected to the color conversion data register 55, a shadow selector 59 is connected to the color conversion selector 58, a processing selector 60 is connected to the shadow selector 59, and a color conversion selector 58 is connected. And the image data is input to the processing selector 60.

The shaded data register 56 is connected to a shaded selector 59, and the control register 57 is a color conversion selector 58 and an AND circuit 62.
, And the output terminal of the AND circuit 62 is connected to the processing selector 60. Then, MASK2 is input to the shaded selector 59 and the OR circuit 61, MASK1 is input to the OR circuit 61, and the output terminal of the OR circuit 61 is input to the AND circuit 62 described above.

The image coloring process shown in FIGS. 16 and 18 is performed as follows.

According to the control register 57, the color conversion selector 58 operates to select the image data, and when MASK1 is in the “H” state,
The color data set in the color conversion data register 55 is overwritten. In addition, the color data set in the shadowing data register 56 is overwritten while MASK2 is "H".

The coloring process of the images shown in FIGS. 17 and 19 is performed as follows.

By the control register 57, the color conversion selector 58 operates to select the color conversion data register 55, and overwrites the color data set in the color conversion data register 55 with MASK1 being "H". When MASK2 is "H", the color data set in the shaded data register 56 is overwritten.

Next, a third embodiment will be described with reference to the drawings. In the third embodiment, a reproduced image and a converted image are used as basic images, and a shadow image is formed as a pattern image.

FIG. 22 is a block diagram showing the overall configuration of the third embodiment, wherein 4a and 4b are line memories, 5a and 5b are image processing units, 6 is a color processing unit, and an original image which has been binarized and extracted. Is input to the line memory 4a, the line memory 4a is connected to the image processing unit 5a, and the image processing unit 5a is connected to the image processing unit 5b.

The image processing unit 5b and the line memory 4b are connected to each other,
The image processing unit 5b is connected to the coloring processing unit 6, and the image processing unit 5a is connected to the coloring processing unit 6, to which the image data is input. The line memory 4a is
The same one as in the first embodiment shown in the figure is used.

FIG. 23 is an explanatory view showing a line memory (4b) used in the third and fourth embodiments, in which NECP D42050C is used.
Input data of 1bit is input to each of the pin D _0in until pin D _n-1in, and summer as the output of the memory comprises n-1 line of data. The data format changes according to the processing content.

FIG. 24 is a circuit diagram showing the configuration of the image processing unit 5a of the third embodiment. The mode selectors 65 and 66 are added to the image processing unit M of the first embodiment already described. That is,
The mode selectors 65 and 6 are arranged in parallel with the selector 15 of the image processing unit M.
The mode selectors 65 and 66 are connected in parallel to the output terminal of the AND circuit 18 and the output terminal of the selector 11. Then, 1bi is assigned to the mode selectors 12, 16, 65 and 66.
t Input data is supplied.

The image processing unit 5a of the third embodiment is the same as the first
Operates in the same manner as the image processing unit of
MASK1, MASK2, MASK4, and MASK5 are supplied to the coloring process 6 from 12, 16, 65, and 66, respectively. In this case, mode selector 1
The processed images shown in FIG. 11 described above are input to 2, 16, 65, and 66.

FIG. 25 is a circuit diagram showing the configuration of the image processing unit 5b of the third embodiment. In the image processing unit of the second embodiment described above, MASK2 is used in place of the 1-bit data of the data shifter 45 and the selector 48. Is input, and the output terminal of the mode selector 42 is connected to the input terminal of the AND circuit 53. Further, a NAND circuit 68 is provided instead of the inverting circuit 52 of the second embodiment. The mode selector 42 is connected to one input terminal of the NAND circuit 68, and MASK1 is input to the other input terminal. The output terminal of the NAND circuit 68 is connected to the input terminal of the AND circuit 53, and the AND circuit 53 outputs MASK3.

FIG. 27 is an explanatory view showing an original image in the third embodiment.
FIGS. 28 to 51 are explanatory diagrams showing images processed and formed in the third embodiment. In these figures, 35 is the original image,
36 is a basic image formed corresponding to the original image, 36a is a pattern image subjected to a coloring process, and in the third embodiment, a shadow image is formed as a pattern image.

In the image processing unit 5b of the third embodiment, FIG. 28, FIG.
FIG. 32, FIG. 33, FIG. 38, FIG. 42, FIG. 43, FIG.
Processing of the image (first-class image) shown in FIGS. 47 and 50 and the image (second-class image) shown in the other drawings are performed by different algorithms.

In forming the first type image, the mode selector 49 is set to select the output signal of the shadow detection comparator 47, and the mode selector 50 is set to select and operate the output signal of the selector 48 by the mode selector 42. The shadow width selector 41 sets the shadow width value (max2 ^n-1 -1).

Simultaneously with the input of MASK2, the data of the previous line is fetched from the line memory, and if MASK2 is "H", the selector 48
Selects the data of the shaded width selector 41, and loads this data into the line memory via the mode selector 50 and the delay register 51. Since the data is delayed by one clock in the delay register 51, the data is shifted by one address with respect to the memory. At this time, the signal supplied to the coloring processing unit is MASK3 if MASK2 is “H”.
Becomes “L”.

When MASK2 is "L" at the time of taking in data from the line memory, the data in the line memory is decremented by 1 by the decrement calculator 44. If the data in the line memory is not zero, the data is input to the line memory via the selector 48, the mode selector 50, and the delay register 51. If the data in the line memory is zero, all0 data in the data register 43 is input to the line memory.

At this time, if it is confirmed by the shadow detection comparator 47 that the signal output to the coloring processing unit is data other than zero, if MASK1 is "L", MASK3 becomes "H". .

By repeating the above-described processing, a first type image is formed.

The memory for performing the first type image formation is in a state as shown in FIG. 20, as already described in the second embodiment.

When forming a second type image, the mode selector 49 is set to select the output signal of the selector 46, and the mode selector 50 is set to select and operate the output signal of the data shifter 45 by the mode selector 42. The input of the selector 46 is selected by the shadow width selector 41.

The data from the line memory is shifted by the data shifter 45, and the data of MASK2 is input to the LSB. The data of the data shifter 45 is supplied to the line memory via the mode selector 50 and the delay register 51.

In this case, since one clock is delayed by the delay register 51, the address is shifted by one address with respect to the memory.
Entered 45 degrees apart. This data is line data of n-1 minutes.

When MASK2 is “H”, MASK3 becomes “L”. When MASK2 is “L” and the selected data in the line memory is “H”, MASK3 becomes “H”, and when the selected data in the line memory is “L”, MASK3 is “L”
Becomes

By repeating the above-described processing, a second type image is formed.

The memory for performing the second type image formation is in a state as shown in FIG. 21, as already described in the second embodiment.

FIG. 26 is a circuit diagram showing the configuration of the color processing section of the third embodiment. An AND circuit 70 is added to the previously described color processing section of the second embodiment shown in FIG. Then, the output terminal of the control register 57 is connected to one input terminal of the AND circuit 70, and MASK4 is input to the other input terminal of the AND circuit 70,
The output terminal of the D circuit 70 is connected to the color conversion selector 58. The OR circuit 61 has MASK3, MSK instead of MASK1 and MASK2.
ASK5 has been entered.

With the control register 57, the color conversion selector 58 selects whether to always output image data or to output the color data set in the data register 55 under the control of MASK4. When MASK3 is “H”, the shadowing selector 59 selects either the output signal of the color conversion selector 58 or the color data set in the data register 55.

When both MASK3 and MASK2 are “L”, the erase area is selected, and thus all0 or all1 is selected. When the circuit is OFF, image data is output. When the circuit is ON and MASK3 is “H”, output data of the color conversion selector 58 is output.

When the circuit is ON and MASK3 is “L”, MASK5 is “H”
, Data from the shaded data register 56 is output, and if MASK5 is “L”, erase data is output.

The states of the signals shown in FIGS. 25 and 26 will be described with reference to the image to be formed.In the image formation shown in FIGS. 28 to 31, MASKs 1, 2, 4, and 5 are input 1-bit data, MASK3 is shadowed data, and in the image formation shown in FIGS.
SK1, 4, 2, and 5 are thinning data, and MASK3 is shadowed data.

In the image formation shown in FIGS. 36 and 37, MASK1 is misalignment correction data, MASK2 and 5 are contour data, MASK3 is shadow data, MASK4 is misalignment correction data, and in the image formation shown in FIGS. 38 and 39, , MASK1,2,5 are offset correction data, MASK3 is shadow data, MASK4 is contour data, MASK1,2,4,5 are thinning data, MASK3 is In the image formation shown in FIG. 42 to FIG.
Is deviation correction data, MASK3 is shadowed data, and MASK4 and 5 are thinning data.

In the image formation shown in FIGS. 46 to 49, MASK1 is misalignment correction data, MASK2 and 5 are thinning data, MASK3 is shadow data, MASK4 is misalignment correction data or thinning data, and FIGS. In the image formation shown in FIG. 51, MASK1 is misalignment correction data, MASK2 and 5 are thinning data, MASK3 is shadowed data,
4 is contour data.

A fourth embodiment will be described with reference to the drawings. In the fourth embodiment, a reproduced image and a converted image are used as basic images, and a shadow image and a border image are formed as pattern images.

The overall configuration of the fourth embodiment is the same as that of the third embodiment already described with reference to FIG. The line memories 4a and 4b of the fourth embodiment are the same as those of the third embodiment.

FIG. 52 is a circuit diagram showing the configuration of the image processing unit 5a of the fourth embodiment. The mode selector 16 is removed from the image processing unit of the first embodiment already described with reference to FIG. Is configured to output MASK3.

In the image processing unit 5a, the same operation as that of the image processing unit of the first embodiment is performed.

As the image processing unit 5b of the fourth embodiment, the same one as the image processing unit b of the third embodiment already described with reference to FIG. 25 is used. The same coloring processing unit as that of the first embodiment described with reference to FIG. 5 is used as the coloring processing unit of the fourth embodiment.

Here, FIG. 52, FIG. 25 and FIG.
It looks like a table.

FIG. 53 is an explanatory view showing an original image in the fourth embodiment.
54 to 61 are explanatory views showing images processed and formed in the fourth embodiment. In these figures, 35 is an original image, 36 is a basic image formed corresponding to the original image, and 36a is It is a pattern image on which coloring processing has been performed.

The process forming operations of these images by the image processing units 5a and 5b and the coloring unit are the same as those described in the other embodiments, and the description thereof will not be repeated.

As described in detail above, each embodiment does not use a frame memory, so that the structure is simplified, and it can be manufactured at low manufacturing cost. In addition, real-time processing is performed, and a reproduced image and a converted image are used as basic images, and a border image and a shadow image are formed as pattern images, so that various images can be formed.

That is, in the first embodiment, the converted image can be emphasized by combining and coloring the converted image with the border image, and in the second embodiment, the reproduced images can be added to the shadow images ( By applying a combination of (2 ⁿ -1 -1 in FIGS. 16 and 17 and ^{n-1 in} FIGS. 18 and 19), an image with a large decorative effect can be obtained.

Further, in the fourth embodiment, a variety of images having extremely large decorative effects can be obtained by combining and coloring the reproduced image or the converted image with the shadow image. In the third embodiment, the first to fourth embodiments are described. All the images obtained in the embodiment of the present invention are formed.

[Effects of the Invention] As described above, according to the present invention, an image that is manufactured at a low manufacturing cost with a simple structure that is not used for a frame memory and that operates in real time to form various images with a large decorative effect. A processing device is provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.
FIG. 2 is a block diagram showing the overall configuration of the first embodiment, FIG. 3 is an explanatory diagram of a line memory used in the embodiment of the present invention, and FIGS. 4 to 10 illustrate the first embodiment. In the figure
FIG. 4 is a circuit diagram of an image processing unit, FIG. 5 is a circuit diagram of a coloring processing unit, FIG. 6 is an explanatory diagram of an original image, FIGS. FIG. 11 is a diagram for explaining image processing in each embodiment, FIGS. 12 to 19 are diagrams for explaining the second embodiment, and FIG. 12 is a block diagram showing the overall configuration.
13 is a circuit diagram of an image processing unit, FIG. 14 is a circuit diagram of a coloring processing unit, FIG. 15 is an explanatory diagram of an original image, FIGS. 16 to 19 are explanatory diagrams of an image to be processed and formed, 20 and 21 are explanatory views showing the state of the memory at the time of image formation in each embodiment.
FIG. 23 is a block diagram showing the entire configuration of the third embodiment, FIG. 23 is an explanatory diagram of a line memory used in the second, third and fourth embodiments, and FIG. 24 is a diagram of the third embodiment. FIG. 25 is a circuit diagram of an image processing unit of the third and fourth embodiments, FIG. 26 is a circuit diagram of a coloring processing unit of the third and fourth embodiments, FIG. FIGS. To 51 are diagrams for explaining images of the third embodiment, FIG. 27 is a diagram for explaining an original image, FIGS. 28 to 51 are diagrams for explaining an image to be formed, and FIGS. FIG. 61 is a diagram for explaining the fourth embodiment, FIG. 52 is a circuit diagram of an image processing unit,
FIG. 53 is an explanatory diagram of an original image, and FIGS. 54 to 61 are explanatory diagrams of an image to be formed. 1 image reading unit, 2 image processing unit, 3 image recording unit, 4, 4a, 4b line memory, 5, 5a, 5b image processing unit, 6 color processing unit 9,11 ... selector, 10 ... shift register, 12,16 ... mode selector, 13,15 ... selector, 14 ... shift register, 20 ... control register,
25,26 …… Data register, 27 …… Control register, 28…
... Color conversion selector, 29 ... Contour selector, 30 ... Processing selector, 41 ... Shadow width selector, 42 ... Mode selector, 44 ... Decrement calculator, 47 ... Shadow detection comparator,
55 ... Color conversion data register, 56 ... Shadow data register, 57 ... Control register, 58 ... Color conversion register, 59 ...
... shading selector, 60 ... processing selector.

Claims (4)

(57) [Claims] 1. A line memory for storing image data of an original image that has been binarized and extracted, and an image length in at least one of a main scanning direction and a sub-scanning direction based on the image data read from the line memory. A conversion image forming unit that forms a conversion image by performing a conversion process that changes a border image forming unit that forms a border image around the periphery of the conversion image,
Coloring processing means for selectively performing a coloring process on the converted image and the border image, respectively, and performs a matrix logical operation process of the conversion image formation, the border image formation, and the coloring process in real time. An image processing apparatus characterized in that the processing is performed by: 2. A line memory for storing binarized and extracted image data of an original image, and reproduced image forming means for forming a reproduced image of the original image based on the image data read from the line memory. A shadow image forming unit that forms a shadow image by moving the reproduction image in a predetermined angle direction, and a coloring processing unit that selectively performs a coloring process on the reproduction image and the shadow image, respectively. An image processing apparatus configured to perform a matrix logical operation process of the reproduction image formation, the shadow image formation, and the coloring process in real time. 3. A line memory for storing image data of an original image that has been binarized and extracted, and reproduced image forming means for forming a reproduced image of the original image based on the image data read from the line memory. A conversion image forming means for performing a conversion process for changing an image length in at least one of the main scanning direction and the sub-scanning direction based on the image data to form a conversion image; Shadow image forming means for forming a shadow image moved to, the reproduction image, the conversion image and the shadow image, each having a coloring processing means for selectively performing a coloring process,
An image processing apparatus configured to perform a matrix logical operation process of the reproduction image formation, the conversion image formation, and the coloring process in real time. 4. A line memory for storing binarized and extracted original image data, reproduced image forming means for forming a reproduced image of the original image based on image data read from the line memory, Based on the image data, in at least one of the main scanning direction and the sub-scanning direction, a conversion image forming unit that performs a conversion process of changing an image length to form a conversion image, and a border image on the periphery of the reproduction image or the conversion image A border image forming unit for forming, a shadow image forming unit for forming a shadow image obtained by moving the reproduced image or the converted image in a predetermined angle direction, the reproduced image, the converted image,
The border image and the shadow image, each having a coloring processing means for selectively performing a coloring process, the reproduction image formation,
An image processing apparatus configured to perform matrix logical operation processing of the conversion image formation, the border image formation, the shadow image formation, and the coloring processing in real time.