JPS62126368A - Lsi testing system - Google Patents

Lsi testing system

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Publication number
JPS62126368A
JPS62126368A JP60264814A JP26481485A JPS62126368A JP S62126368 A JPS62126368 A JP S62126368A JP 60264814 A JP60264814 A JP 60264814A JP 26481485 A JP26481485 A JP 26481485A JP S62126368 A JPS62126368 A JP S62126368A
Authority
JP
Japan
Prior art keywords
lsi
output
test
functional test
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60264814A
Other languages
Japanese (ja)
Inventor
Toshihiko Kurino
栗野 利彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60264814A priority Critical patent/JPS62126368A/en
Publication of JPS62126368A publication Critical patent/JPS62126368A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To make it possible to simultaneously carry out the functional test of LSI and the measurement of a DC characteristic, by changing the values of low level and high level threshold value voltages according to the judge result of the functional test. CONSTITUTION:Prior to a functional test, a test pattern is set to a pattern memory 1 and the information of the input and output pins of LSI to be tested is set to a pin information register 2 and information necessary for the generation of an input wave form is set to an input signal timing generator 5 and the generation timing of an output judge strobe is set to an output judging timing generator 8. Next, high and low level threshold values and change voltage during testing are set to an output judging threshold value voltage setting part 4. The functional test is carried out under this condition and repeated until comes to fail. The value obtained by subtracting change voltage from the threshold value at the time of fail comes to the DC characteristic of LSI to be tested.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、機能試験の結果に従い、出力判定用閾値電圧
設定値を可変とするLSI試験方式に関するものである
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an LSI test method in which a threshold voltage setting value for output determination is made variable according to the results of a functional test.

〔発明の背景〕[Background of the invention]

従来のLSI試験方式は、機能試験において、■oL、
sr:r 、Vott、sx:r(LOWレベル、 H
IGHレベル閾値電圧)の値を一義的に定める必要があ
ったため、例えばLSIの出力′4圧Vor、、Van
の測定等を機能試験と同時に行なう際に、■or、、s
r:r VoH,sgr。
In the conventional LSI test method, ■oL,
sr:r, Vott, sx:r (LOW level, H
Since it was necessary to uniquely determine the value of the IGH level threshold voltage, for example, the LSI output '4 voltage Vor, , Van
When performing measurements etc. at the same time as functional tests, ■or,,s
r:r VoH, sgr.

値を再設定しなければならないという欠点があった。The disadvantage was that the values had to be reset.

特開昭55−27907号公報においては、VOL、5
ETvoII、SETを固定として出力判定ストローブ
について論じている。
In Japanese Patent Application Laid-Open No. 55-27907, VOL, 5
ETvoII discusses the output determination strobe with SET fixed.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、機能試験の判定結果に従いVat、、
5tar 、 Van、sr;rの値を変化させ、LS
Iの機能試験と@流行性(Vot、、VoH)の測定と
が同時に実行可能なLSI試験方式を提供することにあ
る。
The purpose of the present invention is to
5tar, Van, sr; change the value of r, LS
The purpose of this invention is to provide an LSI test method that can simultaneously perform a functional test of I and a measurement of @prevalence (Vot, VoH).

〔発明の概要〕[Summary of the invention]

本発明の特徴は、機能試験の判定結果に従い、VOL、
SET 、 VOH,SET ノ(iヲ’f化’l−セ
ルコトK Lつ、LSIの機能試験と直流特性(■OL
、VQH)の測定を同時に実行可能とし、LSI試験の
能率を向上させるものである。
The feature of the present invention is that the VOL,
SET, VOH, SET ノ(iwo'f conversion'l-Serukoto K L) LSI functional test and DC characteristics (■OL
, VQH) can be measured simultaneously, improving the efficiency of LSI testing.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を(2)に基づいて説明する。 Examples of the present invention will be described below based on (2).

第1図は、本発明に係るLSI試験方式によるLSI試
験装前の一実梅例のブロック図、第2図は、そのフロー
チャート、第5図は、同実施例の動作説明用タイムチャ
ートである。
FIG. 1 is a block diagram of an example of an LSI test before being tested by the LSI test method according to the present invention, FIG. 2 is a flowchart thereof, and FIG. 5 is a time chart for explaining the operation of the same embodiment. .

ここで1は、試験パターンを格納しておくパターンメモ
リ、2は入力ピンや出力判定ピンの指定など仮試・謙L
SIの各ビン毎の・情報を記憶しておくピンi情報レジ
スタ、5は出力判定結果を格納する判定結果レジスタ、
4はVOL、SET 。
Here, 1 is a pattern memory that stores test patterns, and 2 is a temporary test/controller that specifies input pins and output judgment pins.
5 is a pin i information register that stores information for each bin of SI; 5 is a determination result register that stores output determination results;
4 is VOL, SET.

VO// 、 SETを設定する出力判定用量li′I
【′αα圧設肺部54人力信号の波形を決める入力信号
用タイミング発生器、6は入力パターンにより人力ビン
に入力信号を倶給する入力信号用ドライツク、7はとり
こまれた出力信号レベルと出力期待値とを比・戒する出
力判定部、8は出力判定ストローブの出力判定用タイミ
ング発生器、9は被試験LSIである。
VO//, output judgment dose li'I for setting SET
['αα Pressure lung part 54 is an input signal timing generator that determines the waveform of the human power signal, 6 is an input signal driver that supplies input signals to the human power bin according to the input pattern, and 7 is the captured output signal level and output. 8 is an output judgment timing generator for an output judgment strobe, and 9 is an LSI under test.

まず、機能X、験に先立ち、パターンメモリ1に試験パ
ターンを、ピン情報レジスタ2に、被試験LSIの入力
ピン、出力判定ピン等必安なr情報をセットし、また、
入力信号用タイミング発生器5に入力ピンに印加したい
入力波形?発生させるのに必要な情報を、出力判定用タ
イミング発生器8に出力判定ストローブの発生タイミン
グを設定し℃おく(第2図の処理21.22 )。
First, prior to testing Function
What input waveform do you want to apply to the input pin of the input signal timing generator 5? The generation timing of the output determination strobe is set in the output determination timing generator 8 and the information necessary for generating the output determination strobe is set at 0.degree. C. (processes 21 and 22 in FIG. 2).

次に、出力利足用1−値4圧設定部4にVoL、sr:
rvQH,SETおよび試験中の変化屈出ttvを設定
しておく(同感425) 上記設定粂件(Vog、sgrの初期匝は第S図への様
に、機能試験がパスとなるに十分な領域にセットしてお
()により、機能試験を実行しく同処理24)、これが
フェイルとなるまでくり返す(同処理26,25.24
 )。機能試験がフェイルとなり@2図のループから抜
は出した場合(第5図B)、そのとぎのvQH,SET
からcLVを差し引いた値が、該被試験LSIピンのv
OHとなる。
Next, VoL, sr:
Set rvQH, SET and the change output ttv during the test. Set () to execute the function test (process 24), and repeat until it fails (process 26, 25, 24).
). If the function test fails and the loop in Figure 2 is removed (Figure 5 B), the next vQH, SET
The value obtained by subtracting cLV from is the v of the LSI pin under test.
It becomes OH.

尚、VOL ノalll 定1c ツいテ&X VOL
、Sli:T カT;) cLvりは差し引さながら機
能試験を(り返す。
In addition, VOL no all fixed 1c Tsuite&X VOL
, Sli:T かT;) Repeat the functional test while subtracting cLv.

〔発明の効果〕〔Effect of the invention〕

本’duAK1.tLrff、、v□r、、sgr 、
 VOH,SIf:T ノ(W’を機能試験の判定結果
によって可変とすることができ、磯北試炊により、LS
Iの動作を確塔しながら直流特性(Vor、、von 
)の測定ができるので、LSI試1検の効率が向上し、
正価な直流特性測定に効果がある。
Hon'duAK1. tLrff,,v□r,,sgr,
VOH, SIf: T ノ (W' can be made variable depending on the judgment result of the function test, and the LS
DC characteristics (Vor, von
) can be measured, improving the efficiency of the first LSI exam.
Effective for measuring direct current characteristics.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(工、本発明の一実施例のLSI試1.!A方式
によるLSI試験装置道のブロック図、第2図はそのフ
ローチャート、第5図は、同実施例の動作説明用タイム
チャートである。 1・・・パターンメモリ 2・・・ピン情報レジスタ 5・・・判定結果レジスタ 5・・・入力信号用タイミング発生器 6・・・入力信号用ドライバ 7・・・出力判定部 8・・・出力判定用タイミング発生器 9・・・被試@LSI 〜 ( 喚 代理人弁理士 小 川 勝 男ゝ ′ 第 1 凶 第2 図
FIG. 1 is a block diagram of an LSI test device according to the A method, LSI test 1 according to an embodiment of the present invention, FIG. 2 is a flowchart thereof, and FIG. 5 is a time chart for explaining the operation of the same embodiment. 1... Pattern memory 2... Pin information register 5... Judgment result register 5... Input signal timing generator 6... Input signal driver 7... Output judgment section 8. ... Timing generator for output judgment 9 ... Tested @ LSI ~ (Patent attorney Katsutoshi Ogawa)' Part 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1、パターンメモリに試験パターンを格納し、被試験L
SIの入力端子に入力パターンを印加し、該LSIの出
力端子の出力波形を出力判定用タイミング発生器により
定められるタイミングで比較用コンパレータのゲートを
開くことによりとりこみ、その信号レベルが、あらかじ
め設定されている出力HIGHレベル閾値電圧以上か、
出力LOWレベル閾値電圧以下かによって、前記パター
ンメモリに格納されている出力期待値との比較を該比較
用コンパレータにおいて比較し、その一致、不一致によ
りパス、フェイルを判定するLSIの機能試験を行なう
LSI試験装置において、機能試験の判定結果に従って
前記両レベル閾値電圧の値を変化させることを特徴とす
るLSI試験方式。
1. Store the test pattern in the pattern memory, and
An input pattern is applied to the input terminal of the SI, and the output waveform of the output terminal of the LSI is captured by opening the gate of the comparison comparator at the timing determined by the output judgment timing generator, and the signal level is set in advance. Is the output HIGH level threshold voltage or higher?
An LSI that performs a functional test of an LSI in which a comparison is made with an expected output value stored in the pattern memory in the comparison comparator depending on whether the output LOW level is below a threshold voltage, and pass or fail is determined based on the match or mismatch. An LSI test method, characterized in that, in a test apparatus, the values of the two-level threshold voltages are changed according to the determination result of a functional test.
JP60264814A 1985-11-27 1985-11-27 Lsi testing system Pending JPS62126368A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60264814A JPS62126368A (en) 1985-11-27 1985-11-27 Lsi testing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60264814A JPS62126368A (en) 1985-11-27 1985-11-27 Lsi testing system

Publications (1)

Publication Number Publication Date
JPS62126368A true JPS62126368A (en) 1987-06-08

Family

ID=17408582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60264814A Pending JPS62126368A (en) 1985-11-27 1985-11-27 Lsi testing system

Country Status (1)

Country Link
JP (1) JPS62126368A (en)

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