JPS6212586B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information signal reproducing device including a search signal.

Conventionally, the information signal reproducing device used as this type of device records a large number of information signals on one recording medium, automatically selects a desired information signal from the recording medium, and reproduces it. A structure was adopted that would allow for this. In this way, in order to automatically select and reproduce information signals, it is necessary to match each information signal and its corresponding address signal and record them. However, there are various types of address signals, and in order to match them, a device is used that handles the address signal as a binary signal, which will be explained in more detail.

In other words, when simultaneously recording a television signal and an address signal corresponding to each frame, the address signal is recorded in vertical blocks of the television signal (hereinafter referred to as TV signal) in order to make effective use of the recording medium. It is recorded as a superimposed signal inserted into the ranking section. This inserted address signal records a plurality of exactly the same address signals in the blanking section, and the same address signal is repeatedly inserted and superimposed during the horizontal scanning period consisting of the plurality of blanking sections, and is recorded.
Information signals are searched based on these reproduced signals.

The reason for inserting multiple signals of the same address as mentioned above is that the signal reproduction may not be correct due to the influence of noise or other defects such as scratches on the recording medium, dust attached to the recording medium, unevenness, etc. not done,
This is to reduce search malfunctions when a so-called dropout occurs. Regarding the above search operation, the search operation is performed until the address signal selected by the operator matches, and when the desired address is reached, the above information signal is reproduced on the television signal and displayed on the television monitor. Served.

However, even in this case, if an even number of bits with the same level, for example two bits of "1" level, included in the read address signal are accidentally missing, it is not possible to use a validity check circuit. There was a flaw that caused people to misjudge the correct signal.

The present invention has been made to eliminate the above-mentioned drawbacks, and aims to further reduce the effects of dropouts, noise, etc., and to enable accurate address signal detection.

First, before describing the embodiments of the present invention, the waveforms of horizontal and vertical synchronizing signals and address signals, which are the premise thereof, will be explained using FIGS. 1 and 2. FIG. 1 is a diagram showing an address signal inserted into the horizontal scanning period of a TV signal, where A indicates an address signal based on a binary signal using 16 bits as an example, and "1" indicates the white level of the TV signal; “0” is set to the black level,
H is a horizontal synchronization signal. In this figure, the least significant bit is set to be "1", the second and third bits are each "0", and so on, and so on, and the most significant bit is set to be "0". As shown in FIG. 2, the address signal A is repeatedly inserted from A ₁ to A _o times into a plurality of scanning periods located in blanking after the vertical synchronizing signal V. The above address signal corresponds to the image signal P that follows these.

Therefore, for example, an address signal is assigned to one frame of image, and corresponding addresses are assigned to different frames in sequence. The superimposed signals configured as described above are sequentially recorded on a recording medium after being subjected to signal processing such as FM modulation.

In order to reproduce a desired image from such a recording medium, only the address signal part is extracted using the vertical and horizontal synchronization signals contained in the reproduction signal as clues, and
If this and the set desired address signal match, image signals corresponding to both of the above signals can be displayed on the monitor television. VTR as playback device
If this is used, the address specified by the operator is compared with the detected address, and if they match, tape running is stopped and the screen corresponding to the specified address is played back.
As mentioned above, the detected address signal is supplied to a conventional search circuit to control a reproduction device to reproduce the corresponding image.

Embodiments of the present invention will be described below with reference to FIGS. 3 and 4 based on the above-mentioned underlying technology.

In Fig. 3, 1 is a vertical and horizontal synchronizing signal separation circuit, 2 and 3 are vertical synchronizing signal delay pulse generation circuits that set the front and rear of the address signal, and 4 is set by the delay pulses of these circuits 2 and 3. Flip-flop; 5 is an AND gate that receives the set side output of flip-flop 4; 6 is an analog switch; 7 is an inverter; 8 is a flip-flop that receives a horizontal synchronization signal; 9 is an address signal level adjustment circuit; 10 is a clock generator. vessel, 11 is AND
12 is a clock counter, 13 is a pulse generator, 14 is an output signal of the level adjustment circuit 9,
An AND gate that inputs the output of the pulse generator 13, 15 an accumulation counter that inputs the signal of the AND circuit 14, 16 an analog switch, 17 an amplitude comparator, 18 a pulse shaping circuit, and 19 an AND gate.
20 is a counter, 21 is a flip-flop, 22 is an AND gate, 23 is a clock counter, 24 is a pulse generator, 25 is an OR gate, 2
6 is an address designation circuit, 27 is a verification circuit, A is a terminal for inputting an information signal, B is a terminal for inputting a reference voltage, and C is an output terminal for an address signal.

In the above configuration, first, a superimposed signal of an address signal reproduced from a recording medium and an image signal is applied to input terminal A, and this superimposed signal is input to synchronization separation circuit 1 and analog switch 6. In the synchronization separation circuit 1, a vertical synchronization signal V and a horizontal synchronization signal H are separated from the above-mentioned superimposed signal. Of these, the vertical synchronization signal V is inputted to the first delay pulse generation circuit 2, which generates a delay pulse V _D1 . The delay pulse V D2 is generated and further inputted to the second delay pulse generation circuit 3 to generate the delay pulse V _D2 . The time relationship between the delay pulses V _D1 and V _D2 is set so that their delay amounts are before and after the address signal period, respectively, as shown in FIGS. 4b and 4c. The delay pulse V _D1 sets the flip-flop 4 shown in FIG. 3, and outputs the set side output to the next AND gate 5. Also, one of the delayed pulses V _D2 is connected to the flip-flop 4.
Reset. Therefore, the set side output of the flip-flop 4 becomes "1" during the period including the address signal, as shown in FIG. 4d.

On the other hand, the horizontal synchronizing signal H is applied to the flip-flop 8.
However, the set side input is applied to the inverter 7.
The reset side input is applied directly. As a result, the flip-flop 8 is set at the trailing edge of the horizontal synchronizing signal H and reset at the leading edge. This set output becomes one input of the AND gate 5, and FIG. 4e shows the output pulse of the AND gate 5. Furthermore, this output is applied to the next analog switch 6, and is used as a switching pulse to turn ON/OFF the reproduced superimposed signal input directly from input terminal A, that is, to gate and extract the period of the address signal portion from the reproduced superimposed signal. It acts as a gate pulse for the address signals A ₁ to A ₄ to pass through. The output of this analog switch 6 is appropriately level-adjusted by the next level adjustment circuit, and the address signal shown in FIG. 4f is obtained. This address signal consists of the following 16 (14-1 to 14-16)
It is input to the AND gate 14.

The horizontal synchronizing signal H is further applied to a clock generator 10, which generates a clock signal synchronized with a certain phase difference and in a time relationship such that the timing coincides with each bit of the address signal. Figure 4g shows the clock signal obtained in this way,
Also, this clock signal is applied to the AND gate 11,
This is one input of 22. The output of the AND gate 5 is applied to the other input terminal of the AND gate 11, and the output of the AND gate 11 is applied to the next clock counter 12. As for the output of the clock counter 12, after the output of the AND gate 5 is input, only C1 becomes "1" for the first clock, and only C2 becomes "1" for the second clock. 1'', and in the same way C3
From C17, the value becomes "1" in sequence, and at C17, the contents of the clock counter 12 are incremented. Since the output of the AND gate 5 has the waveform shown in FIG. 4e, the operation of the clock counter 12 described above is repeated four times. The outputs of C1 to C16 are respectively applied to the next pulse generator 13, and at the moment this output becomes "1", pulses with approximately the same time width as the clock are sequentially generated, and the output of 13-1 is The output corresponding to the first clock, 1, as shown in FIG.
The output of 3-2 corresponds to the second clock as shown in Figure i, and the output of 13-3
Outputs corresponding to the clocks 13-16 are generated respectively from the clocks 13-16, and FIG. 4j shows the outputs of the clocks 13-16.

The outputs of these pulse generators 13 are
It is input to one side of the AND gate 14, and its output is "1" only when the bit output of the address signal is "1".
A bit pulse is generated, and this bit pulse is applied to the next storage type counter 15. This storage type counter 15 generates voltage E for one bit pulse input, generates voltage 2E for two bit pulse inputs, and similarly generates voltage nE for n bit pulse inputs. is configured to do so. Therefore, AND gate 14-1
The output of the storage type counter 15-1 increases to voltage 4E as shown in FIG. 4k. Furthermore, since the output of the AND gate 14-2 is "0", the output of the storage type counter 15-2 remains at voltage 0 as shown in FIG. 4l. In the same manner, outputs corresponding to the bits of the address signal are sequentially obtained from each storage type counter 15-3 to 15-16.
FIG. 4m shows the outputs of the storage type counters 15-16. The outputs of these storage type counters 15 are simultaneously incremented by the outputs of the delayed pulse generating circuit 3, as shown in FIG.

The switching pulse for the analog switch 16 is obtained as follows. That is, the above
The output of AND gate 5 is applied to AND gate 19 as well as AND gate 11 . This AND
A pulse generator 13 is connected to one input of the gate 19.
-1 output is applied, and the output is applied to counter 2.
0, the output pulses of the pulse generator 13-1 are counted, and when the fourth pulse is input, a pulse is generated at the output terminal and the next flip-flop 21 is inputted.
is set, and an output "1" is obtained on this set side.
Furthermore, this set side output is the AND gate 22
The output of the clock generator 10 is applied to the other input of the AND gate 22, and the output of the AND gate 22 is input to the clock counter 23. This clock counter 23
is the clock pulse n as shown in FIG. 4 after the set side output of the flip-flop 21 is generated.
For the first clock, only d1 of the clock counter 23 becomes "1", and for the second clock, only d2 becomes "1", and in the same way, from d3 to d17. sequentially becomes "1", and the contents of the clock counter 23 are incremented by the output of d17. In addition, d
The output of 17 resets flip-flop 21 and stops the input operation to clock counter 23. Each output of this clock counter 23 is applied to a pulse generator 24 which operates in the same manner as the pulse generator 13 described above, 24-1, 24-2, . . .
..., 24-16 are sequentially applied as switching pulses to analog switches 16-1, 16-2, ..., 16-16. For this reason, the output of the analog switch 16-1 is 4E as shown in FIG. 4k, the output of the analog switch 16-2 is 0 as shown in FIG. An output corresponding to is generated, and the output of the analog switch 16-16 becomes 4E shown in FIG.

The reference voltages of the comparators 17-1 to 17-16 are all applied from the input terminal B, and the reference voltages here are set to about 2E. Therefore,
The amplitude comparator 17 outputs an output for an input exceeding the reference voltage 2E, and does not output an output for an input less than 2E.

Each of these outputs is applied to the next pulse shaping circuit 18, and when an output from the amplitude comparator 17 occurs, an output of "1" is obtained, and when no output occurs, an output of "0" is obtained. Each output obtained in this way is
The signal is applied to the OR gate 25, and an address signal as shown in FIG. 4o is obtained at its output terminal C.

With the configuration described above, address signals _A1 to
Even if a bit included in _A4 is missing or noise is mixed in, the output obtained from the amplitude comparator 17 will have these effects reduced.
For example, due to dropout, the lowest bit "1" of address signal _A1 is missing, the third bit "1" of _A2 is missing, the bit "1" at a certain position of _A3 is missing, and the most significant bit of _A4 is missing. If bit "1" is missing, according to the conventional method, _A1 to _A4 all have missing bits, so these cannot be accurate address signals, and the search operation will not work. Stop.

However, if the above case is operated according to this embodiment, bit "1" of analog switch 16
The output corresponding to the bit "1" is simply the voltage 3E, and the output of the amplitude comparator 17 corresponds to the bit "1", and the correct address signal can be obtained at the output terminal C of the OR gate 25.

In the above description, the synchronization separation circuit may be a conventional circuit as is, or a phase lock loop (PLL) may be added to generate more stable vertical and horizontal synchronization signals. In addition, the address signals to be inserted into the vertical blanking section have been explained using an example of four address signals A ₁ to A ₄ , but if this number is to be increased, slight changes such as the number of output terminals shown in Figure 3 may be necessary. It is clear that the reference voltage can be set to approximately 1/2·nE by inserting n address signals.

As described above, according to the present invention, it is possible to provide an information signal reproducing apparatus in which read number signals are not affected by dropouts, noise, etc., and accurately detect address signals.

[Brief explanation of the drawing]

Figure 1 is a waveform diagram showing an address signal inserted into the vertical blanking part of a television signal and a superimposed signal including a horizontal synchronizing signal. FIG. 3 is a waveform diagram showing an inserted superimposed signal, FIG. 3 is a block diagram showing an embodiment of the apparatus of the present invention, and FIG. 4 is a diagram showing waveforms generated in each part of the embodiment of FIG. 1... Vertical and horizontal synchronization separation circuit, 2, 3... Delay pulse generation circuit, 4... Flip-flop, 5...
AND gate, 6...Analog switch, 7...Inverter, 8...Flip-flop, 9...Level adjustment circuit, 10...Clock generator, 11...AND gate, 12...Clock counter, 13...Pulse generator, 14...AND gate, 15...accumulation counter,
16...Analog switch, 17...Amplitude comparator, 1
8...Pulse shaping circuit, 19...AND gate, 20
...Counter, 21...Flip-flop, 22...
AND gate, 23...clock counter, 24...
Pulse generator, 25...OR gate, 26...address designation circuit, 27...verification circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. Detecting the address signal through a medium on which a plurality of address signals consisting of a plurality of bits assigned corresponding to the information signal to be detected are repeatedly recorded in a predetermined time relationship with a synchronization signal, and detecting the desired address signal. In an information reproducing device that searches for an information signal and reproduces the information signal, a switching device for passing the address signal having a pulse width corresponding to the period in which the address signal was recorded based on the reproduced synchronization signal. means for generating a pulse; means for passing only a plurality of address signals from the reproduced signal based on the switching pulse; and means for timing matching each bit of the address signal based on the reproduced synchronization signal. means for distributing the clock pulse while the switching pulse output is present to sequentially generate a plurality of pulse outputs at timings corresponding to each bit of the address signal; means for passing each bit of the passed address signal with each of the pulse outputs to generate a bit pulse for each bit, and inputting the bit pulse for each bit;
A means for generating a voltage according to the number of inputs for each of the above, and a means for generating a comparison output by comparing the output voltage generated for each of the above with a reference voltage, and generating a comparison output based on the comparison output. 1. An information signal reproducing apparatus comprising means for generating an address signal, and detecting an address signal by synthesizing bits corresponding to each position generated from the means.