JPS62125730A - Signal detection circuit - Google Patents

Abstract

PURPOSE:To recognize accurately and quickly the start of a frame and the frame itself by dividing information into front information and rear information, forming an information part of the rear information as the start of an SPL data frame and a part for the identification as an NRZ data and sending the front information and the rear information while being synchronized. CONSTITUTION:A reception serial signal l11 where the front information P1 and the rear information P2 are multiplexed is separated into the front information P1 and the rear information P2 by a reception information separation relay circuit 1. Although the phase of the information part of the front and rear information P1, P2 is coincident completely, the information P2 takes preceding over the information P1 by bit number of the frame part and he frame identification part. Since the information part of the information P2 is expressed by SPL data and the frame part and the frame identification part are expressed by NRZ data, the presence of the frame part is detected by using the NRZ data of the information P2. Further, the type of the frame is understood by the frame identification section succeeding to the frame part. Then in detecting the frame and the frame identification, the information P1, P2 is extracted at the next timing.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention arranges a plurality of wireless base stations under one control station, and transmits control channel information from the control station to any wireless base station. In a mobile communication system that transmits information, the signal detection circuit that receives information and detects the signal is involved.In particular, the information section detects a frame indicating the start of a signal and identifies the frame between two or more pieces of synchronized information. The present invention relates to a signal detection circuit that attempts to detect signals using different signal formats.

[Conventional technology]

In conventional mobile communication systems of this type, when receiving information and detecting signals, a method is generally adopted in which a specific pattern preceding the information part is detected and the signal after that timing is converted into information. There is.

[Problem that the invention seeks to solve]

In the conventional signal detection method described above, a specific pattern that precedes the information part is detected, and the signal after that timing is treated as information, so there is a possibility that the original signal may be mistakenly detected as a detection pattern. Unfortunately, in order to reduce this false detection, a special long pattern that is difficult to appear as a signal is required, which makes the configuration of the pattern detection circuit complex and large, and at the same time increases the time it takes to detect the pattern. There is a drawback.

[Means for solving problems]

When the signal detection circuit of the present invention multiplexes and transmits the front information transmitted from the control station to the mobile station via the radio base station and the back information transmitted to the radio base station, this multiplexed information is transmitted at an information transmission rate. A means for dividing the front information into front information which is not allowed to change, back information including information indicating the beginning of the frame and frame identification of the front information, and supplementary information of the front information, and a means for dividing the front information into back information including information indicating the beginning of the frame and frame identification, and supplementary information of the front information, and converting the information part of the back information into SPL data to form the frame. It is equipped with a means for transmitting the beginning and a part indicating the frame identification as NRZ data, and the receiving side is equipped with a detection means for detecting the start of frame υ and the 7th frame identification from the NRZ data of the above-mentioned secret information, and from the timing of this detection means. The above-mentioned front information and back information can be received.

[Effect]

In the present invention, information is divided into front information and back information, the information part of the back information is SPL data, the beginning of the frame and the part indicating identification are NRZ data, and the front information and "A back information are synchronized and transmitted. Especially υ, reception t11], when the data is ``V1'', the data is ``V''01'', and the data is ``0''.
Detects an NRZ data part that violates the regularity of SPL data that becomes +V10" data [Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, 1 receives a received serial signal t1□, which is a data signal in which front information (Pl) and back information (P) are multiplexed, separates it into front information (Pl) and back information (P2), and relays it. This is a received information separation and relay circuit. Here, the back information (P's data part is in SPL format, the frame and frame identification part are NRZ data, and the back information (P2)
The frame part of is NRZf of (0, O, 0, 1, l, 1)
4 types of frames can be determined from the data in the frame identification section following the 7+/- periods. Here, the information is in SPL format, and there are no consecutive three or more '0's and '1's.

2 is a shift register circuit that inputs the background information (P2) of the received information separation relay circuit 1 to the input terminal IN and latches it using the clock CLK, and output terminal 9 to Q? When the data of the frame part is latched up to and the data of the frame identification part is latched to the output terminals Qa and QH, the gate circuit 3
All inputs are 11", meaning frame detection is 10"
“ is configured to be output.

4 is a decoder circuit which inputs the output terminals Qa and Qg of the shift register circuit 2 to input terminals B and A, respectively, the output of the gate circuit 3 is supplied to the terminal S, and classifies the data of the frame identification section at the time of frame detection; Reference numeral 5 denotes a gate circuit which receives the outputs from the output terminals 1, 2, . Output 11
It is configured to output “.

6 inputs the output of this gate circuit 5 to the clock input terminal CK and latches the frame detection and the detection of frame & other, and at the same time transmits the state to the interrupt signal t,
When the flip-flop circuit 7 receives the detection signal (interrupt signal) ts from the flip-flop circuit 6, it identifies the frame and at the same time outputs the table information (
This is a control circuit that extracts data from the data (tl) and the background information (t2), and performs controls such as resetting the interrupt signal t9 of the flip-flop circuit 6 when the data extraction is completed.

tl is table information that is one of the pieces of information obtained by dividing the received serial signal 111 by the received information separation and relay circuit 1), and this table information 1. The information passes through the control circuit γ while the transmission speed remains constant, and is essential information for processing, and is referred to as table information (PI). T! is back information divided by the other divided information, and this back information 4 includes supplementary front information (Pl) and frame detection data. And behind the scenes information (P2
), the information part is SPL data, and the frame part and frame identification part are NRZ data.

Here, the pattern of NRZ data with (o, o.

0.1.1.1) is the SPL that becomes 101# data when the data is '1' and '&''10'' when the data is 10/f.
This does not occur due to the regularity of the data.

ts is a clock for creating information latch and detection timing, t4 is frame detection data for frame detection, and when all are %lI, frame detection is detected. t5 is frame identification data indicating frame identification;
L6 is the pattern of the NRZ data part of the back information (0, 0, 0
. or an identification data detection signal indicating that identification data has been detected when a specific frame identification is performed, t is an interrupt signal that notifies the control circuit 7 that frame detection and frame identification have been performed, and ZIO is the above-mentioned This is an interrupt reset signal that resets the interrupt signal t9, and is executed to receive arbitrary data from frame detection and wait for the next frame detection at the end of frame detection. And, tll is the received 7 real signal.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to the time chart shown in FIG.

In this Figure 2, (a) shows the clock, (b) the P2 signal (back I/N signal), (c) the frame detection, (d) the frame identification data, and (e) the P.I.
This shows the signal (table information). A indicates a frame section, an opening indicates a frame identification section, and C indicates information.

First, a received serial signal 1.in which front information CP+) and back information (P2) are multiplexed. □ is separated into front information (Pl) and back information (P2] by the received information separation relay circuit 1. Then, the P1 signal of this front information (see Fig. 2 (, ))
The phases of the information part of the P2 code (see Figure 2 (b)) and the back information are completely in agreement, but the waveform P! of the waveform shown in Figure 2 (b)! The format is preceded by the number of bits in the double signal frame section and frame identification section. This P! Since the double signal information section is SPL data and the frame section and frame identification section are NRZ data, the NRZ data (0
0.0, 1, 1.1), it can be detected that it is a frame portion. The detection code at that time is the frame detection shown in Figure 2 (c). Also, the type of frame can be understood by the frame identification part following the frame part. It is the frame identification shown in Figure 2 (d). It is data.

If this frame and frame identification are all detected, information on the P+G+ signal and P2 signal can be extracted at the next timing.

〔Effect of the invention〕

As explained above, according to the present invention, information is divided into front information and back information, and the information part of the back information is made into the beginning of seven frames of SPL data and the part indicating identification is NRZ data, and the front information and back information are divided into front information and back information. By transmitting information in a synchronized manner, the receiving side can accurately and quickly identify the beginning of a frame and the frame by detecting the NRZ data part that violates the regularity of the SPL data of the background information. The practical effects are extremely low.

In addition, there is no need to add extra frame detection data to the front information, and data can be extracted from the front information and back information from the timing of frame detection.
This is extremely effective in that it does not affect the transmission speed of tables and information.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a time chart used to explain the operation of FIG. 1. DESCRIPTION OF SYMBOLS 1... Reception information separation relay circuit, 2... Shift register circuit, 3, 5... Gate circuit, 4... Dispute decoder circuit, 6ψ... Flip-flop circuit, 7. Meeting...・Control circuit.

Claims (1)

[Claims] In a mobile communication system in which a plurality of radio base stations are arranged under one control station and information on a control channel from the control station is transmitted to an arbitrary radio base station, the mobile communication system is configured to move from the control station via the radio base station. When multiplexing and transmitting the front information transmitted to the station and the back information transmitted to the wireless base station, this multiplexed information is combined with the front information whose information transmission speed is not allowed to change, and the beginning of the frame and frame identification of this front information. and means for dividing the back information into back information including information meaning information and supplementary information of the front information, and means for transmitting the information part of the back information as SPL data and the beginning of the frame and a part indicating frame identification as NRZ data, The receiving side is equipped with a detection means for detecting the start of a frame and frame identification from the NRZ data of the back information, and the front information and the back information can be received from the timing of the detection means. Signal detection circuit.