JPS6212478B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece, and more particularly to a drive system for a pulse motor as an electromechanical conversion mechanism thereof.

Since the so-called quartz wristwatch, which uses a quartz oscillator as the standard oscillator, was put into practical use, it has become widely popular due to its high precision and reliability. During that time, technological innovations in crystal wristwatches have been remarkable, and their power consumption, which initially required more than 20 microwatts, can now be achieved at around 5 microwatts. However, if we look at the breakdown of the current power consumption of 5μW, it is 1.5 to 2μW due to the oscillation of the crystal oscillator, frequency division, etc.
The power consumption of the pulse motor is 3 to 3.5μW, which is quite unbalanced.In other words, the power consumption of the electromechanical conversion mechanism accounts for 60 to 70% of the total power consumption.In order to further reduce power consumption in the future, Reducing the power consumption of this pulse motor seems to be effective. However, the conversion efficiency of current pulse motors is quite high, and it is quite difficult to increase the efficiency further. However, conventional pulse motors have been designed to operate satisfactorily even under the worst conditions due to requirements such as an load-resistant mechanism such as a calendar mechanism, resistance to environments such as temperature and magnetism, and resistance to external disturbances such as vibration and shock. For this reason, the motor was required to have the ability to withstand a certain load under certain driving conditions, but in reality, a watch body is under such load only for about 4 to 5 hours a day, and for the other 20 hours. is almost under no load.

In other words, if the watch body is always in an unloaded state, the motor mechanism does not need to be designed to withstand such a large load, and in that case, power consumption can be reduced considerably. Since the environment is harsh, in order to guarantee this, it was necessary to use a pulse motor that can supply a large amount of power and obtain a large drive output.

The present invention corrects the above-mentioned irrationality by driving the pulse motor with less power when the load is small, and with high power when the load is large, and significantly reduces the power consumed by the pulse motor. It is something to do. Moreover, such a drive system is constructed using reliable all-electronic means without including mechanical contacts, and achieves stable drive that can cope with variations due to motor type and mass production.

The present invention will be explained below.

Fig. 1 shows an example of a pulse motor for an electronic wristwatch. In the figure, 1 is a permanent magnet rotor magnetized to two poles, and stators 2 and 3 are arranged facing each other with rotor 1 in between. However, these stators 2 and 3 are each connected to a yoke 5 around which a coil 4 is wound to form a set of stators.
The stators 2 and 3 are connected to the center of the rotor 1 so that the rotor 1 can rotate in a fixed direction.
The circular arc portions 2a and 3a of the rotor 1 are made eccentric, and the positions of the magnetic poles (N and S) when the rotor 1 is at rest are set to the positions of the stators 2 and 3.
It is shifted to one side of 3. This type of pulse motor has been in practical use for some time and was driven by a circuit block as shown in FIG. 10 is a crystal oscillator, which is driven by an oscillation circuit 11, whose frequency is divided by a frequency divider 12, and a waveform shaper 13.
Two pulses with an appropriate time width and a 180° phase difference are formed at an appropriate time interval.

As an example, let's consider a pulse of 7.8 seconds every 2" and explain this below.
Driver 1 consisting of CMOS inverter
4 and 15, and the output is sent to terminal 4 of coil 4.
FIG. 3 is a detailed diagram of this driver section. When a signal 18 is applied to the input terminal 16 of one inverter 14, a current flows as shown by an arrow 19, and conversely, a current flows to the input terminal 15 of the other inverter 15.
When a similar signal is applied to the input terminal 17 of the arrow 1
Current flows in a route symmetrical to 9. That is, by alternately applying signals to the input terminals 16 and 17 of both inverters, the current flowing through the coil 4 can be alternately reversed. Specifically, the current flowing through the coil 4 can be reversed alternately at 7.8 msec every second. can be passed to. With such a drive circuit, N and S poles are alternately generated in the stators 2 and 3 of the step motor shown in Figure 1, and the rotor 1 can be rotated 180 degrees by repulsion and attraction from the magnetic poles of the rotor 1. . The rotation of the rotor 1 is transmitted to the fourth wheel 7 via the intermediate wheel 6, and further transmitted to the third wheel 8, second wheel 9, and further to the cylinder pinion, hour wheel, and calendar mechanism (not shown), and the hour hand. , operates an indicating mechanism consisting of a minute hand, second hand, calendar, etc.

The pulse motor shown in FIG. 1 operates in principle as explained above, and has been used as a conversion mechanism for electronic wristwatches.

In the drive circuit shown in FIG. 3, when a high level signal is applied to the terminal 17 and a signal 18 is applied to the terminal 16, and a current is caused to flow as shown by an arrow 19, a voltage drop based on the drive current occurs in the MOS transistor 15 due to the channel impedance. A signal waveform corresponding to this current can be detected at the generating terminal 4b.
The current waveform is as shown in FIG. 4, for example. In FIG. 4, section A is a drive section, in this case 7.8 msec, and the current flowing in this section A is the current consumed by motor drive. The reason why the current waveform in section A shows a complicated shape as shown in the figure is that the current generated based on the voltage applied by the drive circuit causes an induced current in the coil due to the rotation of the driven rotor. This is because they are superimposed. Section B is a period after the drive pulse is applied, and the rotor rotates due to inertia and vibrates until it stops at a stable position. At this time, in this section, the P-channel MOS transistors of the drive inverters 14 and 15 shown in FIG. flows. This is why the waveform in section B in FIG. 4 is pulsating. Therefore, the shape of this driving current waveform and the induced current waveform after driving can almost correspond to the rotational position of the rotor.

Now, waveform 20 and waveform 20' in FIG. 4 are a series of waveforms, and this is when the load on the rotor is very small. Waveform 22 and waveform 22' are also a series of waveforms, and in this case, the load on the rotor is large and the rotor is close to its operating limit, while waveform 21 and waveform 21' represent a load that is approximately 1/2 of the maximum allowable load. This is the case when it is multiplied. If you carefully observe the current waveform when the load is changed in this way, you will see that the waveform extends to the right as the load increases. This is because the rotation of the rotor slows down as the load increases, and it has been experimentally confirmed that the rotor vibration frequency and amplitude become lower until it stops at a stable position. Considering this decrease in reverse, it can be understood that if the load on the rotor is always in a no-load state, the drive pulse width can be shortened to 7.8 msec.

In fact, even if the pulse width is shortened, the motor still operates and the driving force, or output torque, decreases. This situation is shown in FIG. Figure 5 shows the output torque characteristic T and power consumption characteristic I when changing the drive pulse width.
It represents. The driving pulse width mentioned above is 7.8
msec corresponds to P ₂ in this diagram. That is, the pulse width P ₂
The output torque is T ₂ and the power consumption is I ₂ .
As mentioned above, this output torque T ₂ is set so as to be able to sufficiently withstand the load encountered by the watch body.

However, if the load on the rotor is small or negligible, the output torque can be small, the drive pulse width can be shortened, and the power consumption can be reduced. For example, if driven with a pulse width of P ₁ , the output torque is T ₁ and the power consumption is only I _1.The present invention focuses on this point, and by detecting the load on the rotor, When the load is small, it is driven with a narrow pulse width, and when a large load is applied, it is driven with a wide pulse width, which is a rational and low power attempt. As mentioned earlier, the overwhelming majority of devices are in a no-load state, so the effect of reducing power consumption is extremely large. For example, as shown in Figure 5, when driving with a pulse width of P ₁ during no load (20 hours) and with a pulse width of P ₂ during load (4 hours), and assuming that I ₁ /I ₂ = 1/2. The average power consumption is I=I ₁ ×20+I ₂ ×4/24=14/24I ₂ ≒
0.58I ₂ , which means less than 60% of the power required compared to the conventional method that constantly drives with a pulse width of P ₂ , resulting in a significant reduction in power consumption.

By the way, although it was briefly mentioned above that "load is detected...", it goes without saying that this method of detecting load is a major point of the present invention. Next, this load detection method will be described. Looking at the current waveform flowing through the coil in FIG. 4, it can be seen that the current waveform changes as the load increases. That is, in drive section A, the positions of maximum and minimum shift to the right as the load increases. The magnitude of the load can be determined by focusing on this point, but the amount of change in this waveform is extremely small and it is difficult to absorb variations in mass production, and extremely delicate control is required.

Therefore, the present invention focused on section B after application of the drive pulse. Also in this section B, as the load increases, for example, the point at which the first minimum value is taken shifts to the right. Moreover, compared to the amount of change in the waveform in section A,
You can get several times the amount of change. Therefore, it is easier to detect the magnitude of the load based on the induced current waveform in this section B than in the above-mentioned section A, and the reliability is also higher. This decrease is the same when the drive pulse width is shortened, and the situation is shown in FIG. The drive shown in Fig. 6 has a narrow drive pulse width compared to Fig. 4, so it can withstand only a small load, but the drive current waveform 23 at no load and the induced current waveform 23' after driving are similar. Drive current waveform 2 at limit load
4. Similarly, the relationship with the induced current waveform 24' after driving is the same as that shown in FIG. The load is detected by the method described above, but the configuration of the present invention normally drives the motor with a narrow drive pulse assuming no load, and always detects the size of the load from the induced current waveform after driving.
When the load is small, driving with the initial narrow driving pulse width is continued. When the load increases and approaches the limit of driving with a narrow driving pulse width,
From the next drive, drive is performed with a wide drive pulse width for a certain period of time, and then the drive is returned to the initial narrow drive pulse width. The present invention generally has such a configuration, but the seventh
This will be explained in more detail with reference to the block diagram in the figure.

FIG. 7 is a block diagram showing the configuration of the present invention, in which 25 is an oscillation circuit including a time standard oscillator, 26
27 is a circuit including a frequency dividing circuit, etc., and a pulse motor drive circuit. 28 is a pulse motor, and the configuration up to this point is the same as a conventional electronic wristwatch. Reference numeral 29 denotes a load detection circuit that detects the load based on the induced current waveform after application of the drive pulse, as explained in FIGS. 4 and 6. Reference numeral 30 denotes a control circuit which controls the drive of the pulse motor 28 according to the load condition detected by the load detection circuit 29. Normally, the control circuit supplies a narrow drive pulse when there is no load and a wide drive pulse when the load is on. . This control system will be explained with reference to FIG. Figure 8 shows the state of the drive pulse.
This state is shown as pulses 31 and 32, which are supplied as described above in the pulse motor section. Pulses 31 and 32 are narrow pulse widths under no-load conditions. After applying pulses 31 and 32. The detection circuit of FIG. 7 detects a load condition, which is either no load or a small load condition. That is, since the load detection after pulse 31 was determined to be no load, the next pulse 32 has a narrow pulse width, and since the load detection after pulse 32 was also determined to be no load, the next pulse 33 also has a narrow pulse width. In load detection after pulse 33, it was determined that the vehicle was in a loaded state. In this case, after pulse 33, several tens of meters
After sec, a second drive pulse 34 having a large effective value and a wide pulse width is applied with the same polarity as the pulse 33 (ie, the same current direction).

For the subsequent constant number of pulses, wide pulse width pulses 35, 36 are applied, and then the first narrow pulse width pulses 37, 38... are applied again. To explain the relationship between the pulse 33 and the pulse 34, when a large load is detected by driving the pulse 33, the pulse 34 with a wide pulse width is applied after several tens of milliseconds. This means that the load is determined to be large when the load is detected after pulse 33, but it is difficult to determine whether the rotor has operated at this time, because the induced current waveform in Figure 6 shifts to the right as the load increases. Attenuate. When the rotor does not operate, no induced current is produced, but it is difficult to distinguish this from the situation in which the rotor operates smoothly when the load is close to its limit. If the load increases gradually, even if it is determined that the load is large, the rotor is still operating at the pulse 33 at that time.
If the load suddenly becomes too large to be driven with a narrow pulse width, the rotor will not operate with pulse 33.

It is difficult to distinguish between the two. Therefore, it is easy to set the load detection after pulse application so that there is some margin. In this configuration, pulse 3
Apply 4. When the rotor is actuated by pulse 33, pulse 34 is a pulse in the same direction as pulse 33, so this pulse 34 becomes a pulse with an opposite phase, and the rotor does not rotate. Also, if the rotor does not operate with pulse 33, it will be driven with pulse 34. At this time, the rotor will be driven with a delay of several tens of milliseconds, but this will not be recognized by the eye as an operation of the second hand. There is no need to worry about unsightliness caused by this. Hereinafter, the pulse 34 will be referred to as a correction pulse. Then after detecting the load,
The reason why the wide pulse width pulses 35 and 36 are made to continue for a certain number of pulses is because the calender mechanism has the largest load on the rotor, and this continues for 3 to 4 hours, so the narrow pulse width is immediately changed. If it returns to normal, it will be determined that it is in a loaded state again, and if this is repeated, two pulses will be supplied for each operation, increasing power consumption and eliminating the significance of reducing power consumption. In addition, the load on the rotor is not only due to the calendar mechanism, but also single loads such as magnetic fields, low temperatures, and disturbances. In such a case, it is desirable that the number of continuous pulses with a wide pulse width be as small as possible. In consideration of such a phenomenon, it is desirable to set the number of continuous pulses to several tens of seconds to several tens of minutes. The configuration of the present invention has been described above. Next, specific embodiments of the present invention will be described. FIG. 9 is an example of a load detection circuit and a drive pulse control circuit of a timepiece according to the present invention. In Fig. 9, 25 is an oscillation circuit, 26 is a frequency dividing circuit, 28 is a motor, 27 is a drive circuit, 2
Reference numeral 9 represents a motor load detection circuit, and reference numeral 30 represents a control circuit, the numbers of which correspond to the block diagram of FIG. 7. Hereinafter, the circuit elements will be explained one by one.

The NAND GATE output of 39 is a clock to create a narrow pulse when driving the motor in a no-load state, for example, 5 m for a 1 second signal fall.
Generates a clock pulse delayed by sec. At this time, the delay flip-flop 42 delays the input 1 second signal by 5 msec and outputs it.
A narrow pulse of 5 msec width is generated at the output of 6.
The flip-flop 44 has a clock input of 128 Hz, and the output of the delay flip-flop 44 is delayed by 7.8 msec with respect to the input 1 second signal. Therefore, a pulse with a width of 7.8 msec is obtained at the output of the gate 47, and this is used as a wide pulse for driving when a load is applied. gate 4
0 is a lock for generating a pulse for determining the no-load state and the loaded state for the time until the minimum part of the current waveform caused by the rotor operation appears immediately after the application of the drive pulse, and 42, 44 Judgment reference pulses are obtained at outputs 43 and 48 by the same operation.

10 corresponds to the output narrow pulse of the gate 46, and 59 corresponds to the judgment reference pulse of the gate 48 output. The gate 41 is a correction pulse circuit, which is a wide pulse with a pulse width of 7.8 msec, and the generation position is relative to the pulse of the gate 46 or 47.
For example, there is a delay of 30msec. An example is shown in FIG. 1066. The input terminal 57 of the gate 41 is a correction signal to be described later, and only when the correction signal becomes HIGH, a correction pulse signal is generated at the output of the gate 41 and supplied to the subsequent stage. The input signals to the gates 39, 40, and 41 are signals for obtaining the pulses, and are sent to the frequency dividing circuit 26.
Combine the outputs appropriately. Gate 89, 49
is a circuit that separates the above-mentioned pulses to the drive inverters 14 and 15 and outputs them alternately every second. The gate 50 inputs one count input to the counter 52 when a correction pulse is issued to the output terminal 41 while the counter 52 is in the negative state. Once the counter 52 starts counting, the gate 50 remains in the OFF state until all outputs of the counter 52 return to normal. When the gate 52 enters a counting state by the output of the gate 50, the gate 51 opens and continues to send a 2 second signal as a count signal to the gate 52 until all the outputs of the gate 52 become atmosphere. As mentioned above, the counter 52 is set appropriately between several tens of seconds and several tens of minutes, and after detecting that the motor is in a loaded state, continues to output a drive signal that is wide for the above-mentioned time range. It becomes a timer for 4
Reference numeral 7 uses the output of the counter 52 as a gate input, and outputs a wide pulse to the subsequent stage while the counter 52 is in a counting state. Figure 9 Block 29
is an example of a circuit that detects a motor load from the operating state of the motor after application of a drive pulse. 5
3,54 is a transmission gate,
The outputs of the drive inverters 14 and 15 are alternately selected according to the drive signal.

The outputs of 53 and 54 are combined and input to a differential amplifier 55 via a capacitor. Of the output signals 53 and 54, waveforms in a no-load state and a waveform in a loaded state are shown in FIGS. 60 and 61, respectively. The differentiating circuit operates as a peak detector in this case, and the signal obtained by passing the differentiating circuit output through two further inverters becomes a rectangular wave that is inverted at each peak, 62 for 60, 64 for 61, etc. I get a signal.

The output of the inverter is delayed by the CR time constant circuit and becomes one input of the NAND gate 56, and by using the intermediate output of the two inverters as the other input of the NAND gate 56, the signals 63 and 65 in FIG. obtain. Signal 63 is output waveform 60
, and the signal 65 corresponds to the output waveform 61. Comparing the output waveforms 60, 61 with the signals 63, 65, it is clear that the pulses of the signals 62, 63 indicate predetermined peak positions of the output waveforms. The load state is detected by determining whether the pulse positions of the signals 63 and 65 are inside or outside the above-mentioned determination reference pulse 59, and the former case is determined to be a no-load state, and the latter case is determined to be a loaded state. judge. Therefore, signal 63 indicates a no-load condition, and signal 65 indicates a loaded condition.

Next, the correction pulse generating means will be described. The gate 104 inputs the load detection signal which is the output of the gate 56, the judgment reference pulse signal 59 which is the output of the gate 48, and the signal obtained by delaying the 1 second signal which is the output of the delay flip-flop 44 by 7.8 msec. It is said that Furthermore, delay flip-flop 4
The output signal No. 4 serves as a mask signal for determining the detectable period at gate 104, which is an inhibition gate. With the above configuration, the detection signal (63 in FIG. 10) when there is no load passes through the gate 104,
Detection signal 65 is prohibited when there is a load. Line 57 is the output of a flip-flop formed by gates 107 and 108, and the set input is formed by gates 106 and 105. The 1 second signal input to the gate 106 determines the initial set state of the flip-flop, and the output 57 is always set to H in the load detection state.
In this state, the signal that detects the no-load state is gate 1.
04, the flip-flop is reset through gates 105 and 106, and the output 57 is set to the L state.

However, when the load is heavy, no reset signal is input, so the output remains set to H. When the output 57 remains high, the gate 41 is in a state where it generates a correction pulse signal, so the correction pulse is supplied to the coil through the gate 48 or 89 for the drive circuit. Note that the other input of the gate 105 receives a signal that prohibits passage of the detection signal at the same time that the counter 52 starts operating. The correction pulse is set to have a larger pulse width than the normal drive pulse by the gate 41, and a pulse having the same polarity as the drive pulse for which the heavy load condition was detected is supplied. That is, NAND gates 90 and 91 and NAND
A 2 second signal is applied to the gates 92 and 93 as a gate signal, and in particular, since the NAND gates 90 and 91 are connected to the inverter 94, the NAND gate 9
A 2-second signal with a polarity opposite to that of 2 and 93 is applied.

As a result, the normal drive pulse signal that has passed through the OR gate 95 passes through the NAND gates 90 and 92 alternately every second and is supplied to the drive circuit. In addition, when a heavy load condition is detected from the induced current generated in the coil after applying the drive pulse, the correction pulse 66 is sent several tens of meters away from the drive pulse as described above.
Output is delayed by sec.

The correction pulse signal is input to NAND gates 91 and 93, but since NAND gates 91 and 93 share the gate signals of gates 90 and 92, respectively, the correction pulse is input to the coil as a pulse with the same polarity as the drive pulse. Supplied. As a result, for the case of waveform 61, a correction pulse 66 is subsequently applied, which completes the rotation of the rotor. However, as described above, this also includes the case where the rotation of the rotor is completed before 66 is applied. The correction pulse signal is also input to the counter 52 via the gate 50, turning on the gate 51 and putting the counter 52 in the counting state. Thereafter, the gate 47 is kept in the ON state for a certain period of time to continue supplying the wide pulse drive signal. 5 while the wide pulse is being applied.
7 is in the LOW state and no correction pulse is output. This is because the motor is considered to have sufficient output torque during wide pulse driving.

As described above, in this embodiment, the normal drive pulse waveform shaping circuit is surrounded by a frame 99 in FIG.
, a gate 46, and an inverter 96, and
A drive pulse with a pulse width of 7.8 msec is transmitted by a delay flip-flop 44 having a clock signal of 128 Hz.
, a gate 47 and an inverter 96. Further, a load detection circuit 29 shown in FIG. 9 is used as a load detection circuit. The correction pulse generation circuit is surrounded by a frame 98 in FIG. 9, and includes a gate 41 that receives the output 57 of the flip-flop as an input, and a drive circuit that outputs the output of the gate 41 so that it becomes a correction pulse with the same polarity as the drive pulse. It is formed by the gates 91 and 93 that are supplied.

In the present invention, the gate 41 is set so that the correction pulse is output with a delay of 20 msec or more after the generation of the drive pulse. The reason why the time is set to 20 msec or more is explained with reference to FIG.

Figure 20 shows the movement of the rotor after the drive pulse is applied, but the rotor movement is large up to about 20 msec, and if a correction pulse is applied at this position, there is a risk that the rotor will be reversed or driven in two steps. . Furthermore, when compared with FIG. 7, the control circuit 30 in FIG. 7 includes a correction pulse generation circuit 98, a waveform shaping circuit 99, and a counter 52.

As the peak detection circuit, various systems can be considered in addition to the 55 differential amplifier circuit. Figure 18 shows
This is a block diagram of a peak detection circuit using a delay circuit, in which 53 and 54 are transmission gates, 80 is a general amplifier in place of 55 in FIG.
1 is a delay circuit, and 82 is a comparator to which the outputs of 80 and 81 are input. An example of the amplifier 80 is shown in FIG. 13 or 14. Since the motor drive detection waveforms 23 and 24 mentioned above are signals of several mV to several tens of mV generated substantially near the power supply level, they are divided by resistors 166 and 167 and converted to the input operating level of the amplifier. A waveform shown in FIG. 16 76 appears at the terminal 168. FIG. 14 is an improved circuit of FIG. 13, in which the resistor 167 is replaced with
Block 170 is a circuit for detecting the output level, which has a feedback circuit in which a MOS transistor is inserted and controls the channel impedance of transistor 169 so that the amplifier input level becomes the operating level. FIG. 15 shows a simple embodiment of the delay circuit 81, in which 171 and 173 are transmission gates, and 172 and 174 are load capacitors.

In this case, the input signal 76 at terminal 168 is delayed as 77 at the output terminal. FIG. 17 schematically represents this waveform. Input signal 76 is transmitted to capacitor 172 by transmission gate 171, and the terminal voltage waveform of 172 becomes 79. Furthermore, transmission gate 1
73, a waveform 77 appears at the output terminal 175. Comparator 82 outputs a rectangular signal indicating 78 when waveforms 76 and 77 are input.

As the delay circuit, the one shown in FIG. 15 is suitable, but since the input signal frequency is relatively low, a bucket brigade type data transfer element is also suitable.

It has been confirmed that the load detection method of the present invention operates effectively even against magnetic fields or shocks applied to the watch body. FIG. 19 shows a detected current waveform when a DC magnetic field is applied in the direction of the coil of the pulse motor. 83 is a case where the directions of the magnetic field induced in the motor inner core by an external magnetic field and the driving magnetic field are opposite to each other, and 84 is a case where both magnetic fields are in the same direction. In 83 and 84, waveforms 85 and 86 have an external magnetic field, and can be considered to be almost the same waveform. 8
7 and 88 are waveforms when the external magnetic field is 40 Gauss. According to the waveform, the operation in the direction 83 becomes more difficult as the external magnetic field becomes stronger, and exhibits the same characteristics as the operation when the load becomes large. Therefore, the timepiece circuit according to the present invention operates effectively even under the influence of external magnetic fields, and it has been experimentally confirmed that the strength against external magnetic fields is no different from that of conventional timepieces.

In the case of 87 in FIG. 19, since the minimum position of the waveform appears after the determination reference pulse, a correction signal 87' is added. From the above explanation, it can be easily inferred that the present invention has an effective effect on impact resistance as well.

The embodiments of the present invention have been described in detail above, but in the present invention, when the load increases, the correction pulse with a large effective value is applied following the drive pulse after the rotational vibration of the rotor has stabilized, that is, the narrow pulse is applied. By applying the pulse with a delay of 20 msec or more (approximately 30 msec in the embodiment), for example, switching from a narrow pulse to a wide pulse is performed in an extremely stable operation, thereby increasing reliability. The present invention is not limited to the embodiments described here, and various improvements, changes, and applications are possible. For example, the pulse motor is not limited to the pulse motor described here. A conversion mechanism other than a motor may be used, and even a pulse motor shown in FIG. 11 among pulse motors can be used with exactly the same configuration.
In the pulse motor shown in FIG. 11, the rotor 200 is made of a permanent magnet, and the stator 201 is an integral type without a gap, unlike the one in FIG.
03 is formed. 204 is a drive coil. Such a pulse motor has a stator 20
1 is connected, the induced current after driving is the first
As shown in FIG. 2, it is slightly different from FIGS. 4 and 6. However, the waveforms 205, 20 at no load
It will be understood that the relationship between waveforms 206 and 206' under load is basically the same and can be realized using the same method.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a pulse motor for an electronic wristwatch. FIGS. 2 and 3 are diagrams showing conventional circuit configurations, and FIG. 4 is a diagram showing a current waveform of a pulse motor drive coil in a timepiece. FIG. 5 is a diagram showing the relationship between output torque and power consumption with respect to the drive pulse width of the pulse motor. Figure 6 is a coil current waveform diagram when the motor is driven with a pulse width narrower than the conventional drive pulse. FIG. 7 is a diagram showing a circuit block of a timepiece according to the present invention. FIG. 8 is a diagram showing an example of a time chart of motor drive pulses by the circuit according to the present invention. FIG. 9 is a circuit diagram showing a specific example of the block circuit of FIG. 8. FIG. 10 is a diagram showing an example of the time chart in FIG. 9. FIG. 11 is a diagram showing an example of a pulse motor of an electronic wristwatch according to the present invention. FIG. 12 is a coil current waveform diagram during narrow pulse driving in the pulse motor of FIG. 11. FIGS. 13 to 18 are diagrams showing other examples of the load detection section in FIG. 9. FIG. 19 is a diagram showing changes in the coil current waveform when a DC magnetic field is applied to the electronic wristwatch according to the present invention. FIG. 20 shows a measurement graph. 25... Oscillation circuit, 26... Frequency dividing circuit, 27...
... Drive circuit, 28 ... Motor, 29 ... Motor load detection circuit, 30 ... Control circuit, 31 to 33
... Narrow pulse drive signal, 34 ... Correction signal, 35
... Wide pulse drive signal, 59 ... Load judgment reference pulse, 60 ... No-load detection signal, 61 ... Load detection signal, 98 ... Correction pulse generation circuit, 9
9... Waveform shaping circuit.

Claims (1)

[Claims] 1. An oscillation circuit 25, a frequency division circuit 26 that frequency divides the output signal of the oscillation circuit, a drive circuit 27 that operates based on the output signal of the frequency division circuit, and the drive circuit consisting of a coil, a permanent magnet rotor, and a stator. In the electronic timepiece, the electronic watch has a pulse motor driven by a load detection circuit 29 that detects an induced current generated in the coil, and a load detection circuit connected between the frequency dividing circuit 26 and the drive circuit 27. a control circuit 30 that controls driving of the pulse motor based on an output signal of the circuit;
When the load detection circuit detects a heavy load state, a correction pulse is formed following the drive pulse, which has a larger effective value than the drive pulse, has the same polarity as the drive pulse, and is output at least 20 msec later than the drive pulse. An electronic timepiece characterized by comprising a correction pulse generation circuit 98.