JPH023152B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic timepiece, and particularly to a drive system for a pulse motor as an electromechanical conversion function thereof. An object of the present invention is to reduce the power consumption of such a pulse motor. Another object of the present invention is to detect or anticipate and instantly correct malfunctions that may occur during low power consumption driving, and to provide a control system in which malfunctions or corrections are not detected in the external operation of the watch, such as the operation of the second hand. Our goal is to provide the following.

Since the so-called quartz wristwatch, which uses a quartz oscillator as the standard oscillator, was put into practical use, it has become widely popular due to its high precision and reliability. During that time, technological innovations in crystal wristwatches have been remarkable, and their power consumption, which initially required 20-plus microwatts, can now be achieved at around 5 microwatts. However, if we look at the breakdown of the current power consumption μW, it is 1.5 to 2 μW due to the oscillation of the crystal oscillator, frequency division, etc.
The power consumption of a pulse motor is 3 to 3.5 μW, which is quite unbalanced. In other words, the power consumption of the electromechanical conversion mechanism accounts for 60 to 70% of the total power consumption. In order to further reduce power consumption in the future, Reducing the power consumption of this pulse motor seems to be effective.
However, the conversion efficiency of current pulse motors is quite high, and it is quite difficult to increase the efficiency further. However, conventional pulse motors have been designed to operate satisfactorily even under the worst conditions due to requirements such as an load-resistant mechanism such as a calendar mechanism, resistance to environments such as temperature and magnetism, and resistance to disturbances such as vibration and shock. For this reason, the motor was required to have the ability to withstand a certain load under certain driving conditions, but in reality, a watch body under such a load requires only 4 to 5 hours in a day to withstand a certain load.
Most of the time there is no load. In other words, if the watch body is always in a no-load state, the motor mechanism does not need to be designed to withstand such a large load, and in that case, power consumption can be reduced considerably. Since the environment is harsh, in order to guarantee this, it was necessary to use a pulse motor that can supply a large amount of power and obtain a large drive output.

The present invention corrects the above-mentioned irrationality by driving the pulse motor with less power when the load is small, and with high power when the load is large, and greatly reduces the power consumed by the pulse motor. It is intended to reduce Moreover, such a drive system is constructed using reliable all-electronic means without including mechanical contacts, and achieves stable drive that can cope with variations due to motor type and mass production.

The present invention will be explained below.

Figure 1 shows an example of a pulse motor for an electronic wristwatch. In the figure, 1 is a permanent magnet rotor magnetized to two poles, and stators 2 and 3 are arranged facing each other with rotor 1 in between. However, these stators 2 and 3 are each connected to a yoke 5 around which a coil 4 is wound to form a set of stators. The stators 2 and 3 have circular arc portions 2a and 3a eccentric to the center of the rotor 1 so that the rotor 1 can rotate in a fixed direction, and the positions of the magnetic poles (N and S) when the rotor 1 is at rest are adjusted. The stators 2 and 3 are shifted to one side. This type of parallel motor has been in practical use for some time, and was driven by a circuit block as shown in FIG. A crystal oscillator 10 is driven by an oscillation circuit 11, its frequency is divided by a frequency divider 12, and a waveform shaper 13 generates two pulses having an appropriate time width and a 180° phase difference at an appropriate time interval. is formed.

As an example, let's consider a pulse of 7.8 msec every 2" and explain this below.
Driver 1 consisting of CMOS inverter
4 and 15, and the output is sent to terminal 4 of coil 4.
a, 4b. FIG. 3 is a detailed diagram of this driver section. When a signal 18 is applied to the input terminal 16 of one inverter 14, a current flows as indicated by an arrow 19, and conversely, a current flows to the input terminal 16 of one inverter 14.
When a similar signal is applied to the input terminal 17 of 5, a current flows in a route symmetrical to arrow 19. This is the transistor 1 that connects both ends of the coil and the positive electrode.
4a and 15a are formed by P-channel MOS transistors, and transistors 14b and 15b connecting between both ends of the coil and the negative electrode are N-channel MOS transistors.
This is because it is formed from MOS transistors. That is, by alternately applying signals to the input terminals 16 and 17 of both inverters, the current flowing through the coil 4 can be alternately reversed. Specifically, the current flowing through the coil 4 can be reversed alternately at 7.8 msec every second. can be passed to. With such a drive circuit, N is applied to the stators 2 and 3 of the sputter motor shown in FIG.
Pole and S pole are generated alternately, and the rotor 1 can be rotated 180 degrees by repulsion and attraction between the rotor 1 and the magnetic pole. The rotation of the rotor 1 is transmitted to the fourth wheel 7 via the intermediate wheel 6, and further transmitted to the third wheel 8, second wheel 9, and further to the cylinder pinion, hour wheel, and calendar mechanism (not shown), and the hour hand. ,minute hand,
Operates an indicating mechanism consisting of hands, calendar, etc.

The pulse motor shown in FIG. 1 operates in principle as explained above, and has been used as a conversion mechanism for electronic wristwatches.

In the drive circuit shown in FIG. 3, when a high level signal is applied to the terminal 17 and a signal 18 is applied to the terminal 16, and a current is caused to flow as shown by an arrow 19, a voltage drop based on the drive current occurs in the MOS transistor 15 due to the channel impedance. A signal waveform corresponding to this current can be detected at the generating terminal 4b.
The current waveform is as shown in FIG. 4, for example. In FIG. 4, section A is a drive section, in this case 7.8 msec, and the current flowing in this section A is the current consumed by motor drive. The reason why the current waveform in section A shows a complicated shape as shown in the figure is that in addition to the current generated based on the voltage applied by the drive circuit, there is also an induced current in the coil due to the rotation of the driven rotor. This is because they are superimposed. Section B is the section after the application of a pulsed drive signal (hereinafter referred to as drive pulse), in which the rotor rotates due to inertia and freely damps vibration until it stops at a stable position.At this time, this section is used for driving as shown in Fig. 3. P channel of inverters 14 and 15
Since the MOS transistor is turned on, an induced current flows to the coil 4 in accordance with the movement of the rotor in a loop between the coil 4 and the transistors 14a and 15a. This is why the waveform in section B in FIG. 4 is pulsating. Therefore, the shape of this driving current waveform and the induced current waveform after driving can almost correspond to the rotational position of the rotor.

Now, waveform 20 and waveform 20' in FIG. 4 are a series of waveforms, and this is when the load on the rotor is very small. Waveform 22 and waveform 22' are also a series of waveforms, and in this case, the load on the rotor is large and the rotor is close to its operating limit, while waveform 21 and waveform 21' represent a load that is approximately 1/2 of the maximum allowable load. This is the case when it is multiplied. If you carefully observe the current waveform when the load is changed in this way, you will see that the waveform extends to the right as the load increases.
This is because the rotation of the rotor slows down as the load increases, and it has been experimentally confirmed that the rotor vibration frequency and amplitude become smaller until it stops at a stable position. Considering this phenomenon in reverse, it can be understood that if the load on the rotor is always in a no-load state, the rotor can be driven with a short pulse width of 7.8 msec. In fact, even if the pulse width is shortened, the motor still operates and the driving force, or output torque, decreases. This situation is shown in FIG. FIG. 5 shows the output torque characteristic T and the power consumption characteristic I when the drive pulse width is changed. The aforementioned driving pulse width of 7.8 msec corresponds to P ₂ in this figure. That is, the output torque is T ₂ with a pulse width of P ₂ and the power consumption is I ₂ . As mentioned above, this output torque T ₂ is set so as to be able to sufficiently withstand the load encountered by the watch body. However, if the load on the rotor is small or negligible, the output torque can be small, the drive pulse width can be shortened, and the power consumption can be kept small. For example, if driven with a pulse width of P ₁ , the output torque T ₁
The present invention focuses on this _point , and by detecting the load on the rotor, the rotor is driven with a narrow pulse width when there is no load or when the load is small, and when a large load is applied, the rotor is driven with a narrow pulse width. In some cases, it is attempted to drive with a wide pulse width, which is rational and aims to reduce power consumption. As mentioned before, the overwhelming majority of people are in a no-load state, so the effect of reducing power consumption is very large. For example, as shown in Figure 5, when there is no load (20 hours), the pulse width is P ₁ and when the load is applied (4 hours).
time) is driven with a pulse width of P ₂ , I ₁ /I ₂ = 1/2
Assuming that, the average power consumption is I = I ₁ × 20 + I ₂ × 4/24 = 14/24 = I ₂ ≒ 0.58 _{I 2} , which is 60 % or less electricity is required. Also, in FIG. 5, for example, the point that first takes the minimum value is shifted to the right. Moreover, compared to the amount of change in the waveform in section A,
A change several times larger can be obtained. Therefore, it is easier to detect the magnitude of the load based on the induced current waveform in this section B than in the above-mentioned section A, and the reliability is also higher. This phenomenon also occurs when the driving pulse width is shortened, and the situation is shown in FIG. The drive shown in Fig. 6 has a narrower drive pulse width than the one shown in Fig. 4, so it can withstand only a small load, but the drive current waveform 23 at no load and the induced current waveform 23' after driving also operate. Drive current waveform 2 at limit load
4. Similarly, the relationship with the induced current waveform 24' after driving is the same as that shown in FIG. The load is detected by the method described above, but the configuration of the present invention normally drives the motor with a narrow drive pulse assuming no load, and always detects the size of the load from the induced current waveform after driving. When is small, driving continues with the initial narrow driving pulse width. If the load increases and approaches the limit of driving with a narrow driving pulse width, the next drive will be driven with a wide driving pulse width for a certain period of time.
Thereafter, the drive is returned to the original narrow drive pulse width. The present invention is generally constructed as described above, and will be explained in more detail with reference to the block diagram of FIG.

FIG. 7 is a block diagram showing the configuration of the present invention, in which 25 is an oscillation circuit, 26 is a circuit including a frequency dividing circuit, 27 is a pulse motor drive circuit, and 28 is a pulse motor. It's the same as an electronic watch. Reference numeral 29 denotes a load detection circuit that detects the load based on the induced current waveform after application of the drive pulse, as explained in FIGS. 4 and 6. Reference numeral 30 denotes a control circuit that controls the drive of the pulse motor 28 according to the load condition detected by the load detection circuit 29. Normally, the control circuit supplies narrow drive pulses when there is no load and wide drive pulses when there is load. . This control method is used in the eighth
This will be explained with reference to the diagram. FIG. 8 shows the state of the drive pulses, and the states supplied as described in the section regarding the pulse motor are shown as pulses 31 and 32. Pulses 31 and 32 are narrow pulse widths under no-load conditions. After applying the pulses 31 and 32, the detection circuit of FIG. 7 detects a load condition, which is either no load or a small load condition. In other words, since the load detection after pulse 31 was determined to be no load, the next pulse 3
2 has a narrow pulse width, and since the load detection after pulse 32 also determined that there is no load, the next pulse 33 also has a narrow pulse width. In load detection after pulse 33, it was determined that the vehicle was in a loaded state. In this case pulse 3
3, several tens of milliseconds later, a second drive pulse 34 with a wide pulse width is applied with the same polarity as the pulse 33 (that is, the same current direction). For a certain number of subsequent pulses, wide pulse width pulses 35, 36 are applied, and then the initial narrow pulse width pulses 37, 38, . . . are applied again. To explain the relationship between the pulse 33 and the pulse 34, when a large load is detected by driving the pulse 33, the pulse 34 with a wide pulse width is applied after several tens of milliseconds. This is because the load is detected after pulse 33 and it is determined that the load is large, but it is difficult to determine whether the rotor has operated at this time because the induced current waveform in Figure 6 shifts to the right as the load increases. Attenuate.
When the rotor does not operate, no induced current is produced, but it is difficult to distinguish this from the situation in which the rotor operates smoothly when the load is close to its limit. If the load increases gradually, even if the load is determined to be large, the rotor will still be operating at the pulse 33 at that time, and if the load suddenly becomes too large to be driven by a narrow pulse width, the rotor will not operate at the pulse 33. It doesn't work. It is difficult to distinguish between the two. Therefore, it is easy to set the load detection after pulse application so that there is some margin. In this configuration, pulse 34 is applied. When the rotor is actuated by the pulse 33, the pulse 34 is in the same direction as the pulse 33, so this pulse 34 becomes a pulse with an opposite phase, and the rotor does not rotate. or,
When the rotor is not activated by pulse 33, it is driven by pulse 34. At this time, the rotor is driven with a 10 msec delay, but this is not visible to the eye as an operation of the second hand, and there is no need to worry about unsightliness caused by this.
Next, after detecting the load, a pulse 35 with a wide pulse width,
The reason why 36 was configured to continue for a certain number of pulses is that the largest load on the rotor is the calendar mechanism, and this continues for 3 to 4 hours, so if the pulse width is immediately returned to a narrow pulse width, it will be judged as being under load again. However, if this is repeated, two pulses will be supplied for each operation, increasing power consumption and eliminating the significance of reducing power consumption. In addition, the load on the rotor is not only due to the calendar mechanism, but also single loads such as magnetic fields, low temperatures, and disturbances. In such a case, it is desirable that the number of continuous pulses with a wide pulse width be as small as possible. In consideration of such a phenomenon, it is desirable to set the number of continuous pulses to several tens of seconds to several tens of minutes. The above is the configuration of the present invention,
Next, specific examples of the present invention will be described. 9th
The figure shows an example of a load detection circuit and a drive pulse control circuit of a timepiece according to the present invention. In Fig. 9, 25 is an oscillation circuit, 26 is a frequency dividing circuit, 28 is a motor (only the coil is shown), 27 is a drive circuit,
29 is a motor load state detection circuit;
This corresponds to the block in the figure. The drive circuit shown in FIG. 3 is used. Hereinafter, the circuit elements will be explained one by one. 39 NAND GATE
The output is a clock for creating narrow pulses when driving the motor in a no-load state, and for example, generates a clock pulse delayed by 5 msec with respect to the falling edge of a 1 second signal. At this time, the delay flip-flop 4
2, the input 1 second signal is delayed by 5 msec and output, and a narrow pulse with a width of 5 msec is generated at the output of the gate 46. Flipflop 44 is 128
A delay flip-flop with Hz as the clock input, the output of 44 is delayed by 7.8 msec with respect to the input 1 second signal. Therefore, a pulse with a width of 7.8 msec is obtained at the output of the gate 47, and this is used as a wide pulse for driving when a load is applied. The gate 40 is a clock for generating a pulse for determining the no-load state and the loaded state for the time period until the minimum portion of the current waveform generated by the rotor operation appears immediately after the application of the drive pulse, 42, A criterion gate is obtained at the output of gate 48 by using the delay flip-flop 43 in the same manner as 44.

10 corresponds to the output narrow pulse of the gate 46, and 59 corresponds to the determination reference pulse of the output of the gate 48. Gate 41 is a circuit for a pulse-like correction signal (hereinafter referred to as correction pulse), and the pulse width is a wide pulse of 7.8 msec, and the generation position is gate 4.
For example 30msec for 6 or 47 pulses
I'll be late. An example is shown in pulse 66 of FIG.
The input terminal 57 of the gate 41 is a correction signal to be described later, and only when the correction signal becomes HIGH, a correction pulse is generated at the output of the gate 41 and supplied to the subsequent stage. The input signals to the gates 39, 40, and 41 are signals for obtaining the above-mentioned pulses, and are appropriately combined with the outputs of the frequency dividing circuit 26. The gates 89 and 49 are circuits that separate the pulses to the drive inverters 14 and 15 and output them alternately every second.
The gate 50 inputs one count input to the counter 52 when a correction pulse is issued to the output terminal 41 while the counter 52 is at zero. After the counter 52 starts counting, the gate 50 continues until all outputs of the counter 52 return to zero.
It becomes OFF state. 5 by the output of gate 50
2 enters a counting state, the gate of 51 opens and thereafter continues to send a 2 second signal to 52 as a count signal until all outputs of 52 become zero. As mentioned above, the counter 52 is set appropriately between several tens of seconds and several tens of minutes, and after detecting that the motor is in a loaded state, outputs a wide pulse drive signal for the above-mentioned time width. A timer to keep you going. 47
uses the output of the counter 52 as a gate input, and outputs a wide pulse to the subsequent stage while the counter 52 is in the counting state. Figure 9 Block 29
is an example of a load detection circuit that detects a motor load from the operating state of the motor after application of a drive pulse.
The specific configuration of the inverters 14 and 15 is as shown in FIG. 3, and after the drive signal is applied, the transistors 14a and 15a in FIG. 3 are turned on.
This serves as a means to short-circuit both ends of the coil to form a loop. 53, 54
is a transmission gate that alternately selects the outputs of the driving inverters 14 and 15 according to the driving signal.

The outputs of 53 and 54 are combined and input to a differential amplifier 55 via a capacitor. Of the output signals 53 and 54, the waveforms in the no-load state and in the loaded state are shown in FIGS. 10, 60 and 61, respectively. The differentiating circuit operates as a peak detector in this case, and the signal obtained by passing the differentiating circuit output through two further inverters becomes a short waveform that is inverted at each peak, 62 for 60, 64 for 61, etc. I get a signal.

The output of the inverter is delayed by the CR time constant circuit and becomes one input of the NAND gate 56.
Also, by using the intermediate output of the two inverters as the other input of the NAND gate 56, the 10th
Signals 63 and 65 in the figure are obtained. Signal 63 corresponds to output waveform 60 and signal 65 corresponds to output waveform 61. Comparing the output waveforms 60, 61 with the signals 63, 65, it is clear that the pulses of the signals 62, 63 indicate predetermined peak positions of the output waveforms.
The load state is detected by determining whether the pulse positions of the signals 63 and 65 are inside or outside the above-mentioned determination reference pulse 59, and the former case is determined to be a no-load state, and the latter case is determined to be a loaded state. judge. Therefore, signal 63 indicates a no-load condition, and signal 65 indicates a loaded condition. Note that the output signals 63 and 65 of the NAND gate output pulses in the negative direction.

Next, the correction pulse generating means will be described. The gate 104 inputs the load detection signal which is the output of the gate 56, the judgment reference pulse signal 59 which is the output of the gate 48, and the signal obtained by delaying the 1 second signal which is the output of the delay flip-flop 44 by 7.8 msec. It is said that Furthermore, delay flip-flop 4
The output signal of No. 4 serves as a mask signal for determining the detectable period at gate 104. With the above configuration, the detection signal when there is no load (Fig. 10 63)
passes through the gate 104, but the detection signal 65 when there is no load is prohibited. Line 57 is gate 1
The output of the flip-flop formed by 07 and 108 and the input set by gates 106 and 105 are formed. The 1 second signal input to the gate 106 determines the desired set state of the flip-flop, and the output 57 is always set to H in the load detection state. When a signal detecting a no-load state passes through gate 104 in this state, it passes through gates 105 and 106, resets the flip-flop, and sets output 57 to the L state.
However, when the load is heavy, the reset signal is not input, so the output 57 remains set to H. If the output 57 remains high, the correction pulse is passed through the gate 41 that generates the correction pulse, so the correction pulse is supplied to the coil through the drive circuit gate 48 or 49. Nao gate 10
The other input of the counter 52 receives a signal that prohibits passage of the detection signal at the same time the counter 52 starts operating. Note that the correction pulse is set to have a pulse width larger than the normal drive pulse by the gate 41, and a pulse having the same polarity as the drive pulse for which the positive load state was detected is supplied. That is, NAND gate 9
A 2 second signal is applied as a gate signal to 0 and 91 and NAND gates 92 and 93, especially NAND gates 92 and 93.
Since the gates 90 and 91 are connected through an inverter 94, a 2-second signal having a polarity opposite to that of the NAND gates 92 and 93 is applied.

As a result, the normal drive pulse that has passed through the OR gate 95 passes through the NAND gates 90 and 92 alternately every second and is supplied to the drive circuit. In addition, when a heavy load condition is detected from the induced current generated in the coil after the drive pulse is applied, the correction pulse 66 is activated several tens of milliseconds after the drive pulse as described above.
Output is delayed.

The correction pulse signal output from the gate 41 is
It is input to NAND gates 91 and 93,
NAND gates 91 and 93 are gates 90 and 9, respectively.
Since the two gate signals are shared, the correction pulse is supplied from the drive circuit as a pulse having the same polarity as the drive pulse. As a result, for the case of waveform 61, correction pulse 66 is continuously applied,
66 completes the rotation of the rotor. however,
This also includes the case where the rotation of the rotor is completed before 66 is applied as described above. gate 4
1, 90, 91, 92, 93 and inverter 9
4 is referred to as a correction pulse generation circuit 98.

The signal from gate 41 that generates correction pulse 66 also passes through gate 50 to counter 52.
is input, the gate 51 is turned ON, and the gate 52 is inputted.
to count state. After that, gate 4 for a certain period of time
7 is kept in the ON state and continues to supply the wide pulse drive signal. While the wide pulse is being supplied, 57 is
It is in the LOW state and no correction pulse is output.
This is because the motor is considered to have sufficient output torque during wide pulse driving.

As described above, in this embodiment, the normal drive pulse waveform shaping circuit is surrounded by the frame 99 in FIG. For the driving pulse formed by the gate 46 and the inverter 96 and having a pulse width of 7.8 msec,
Delay flip-flop 44 with 128Hz clock signal, gate 47 and inverter 96
is formed. Further, the load detection circuit 29 shown in FIG. 9 is used as the load detection circuit, and the correction pulse generation circuit is surrounded by the frame 98 in FIG. 9 as described above. Furthermore, when compared with FIG. 7, the control circuit 30 in FIG.
8. Contains a waveform shaping circuit 99, and a detection circuit 2
According to the output signal of No. 9, drive signals having different drive powers including correction pulses are selectively output.

As the peak detection circuit, various systems can be considered in addition to the 55 differential amplifier circuit. An example of the amplifier is shown in FIG. 13 or FIG. 14. Since the motor drive detection waveforms 23, 24, etc. mentioned above are signals of several mV to several tens of mV substantially generated near the power supply level, they are divided by resistors 166, 167 and converted to the input operating level of the amplifier. The terminal 168 has
The waveform shown in FIG. 16 76 appears. Figure 14 shows the first
This is an improved circuit of Figure 3, in which a MOS transistor is inserted in place of the resistor 167, and the transistor 169 is inserted so that the amplifier input level becomes the operating level.
Block 170 is a circuit for detecting the output level and has a return circuit for controlling the channel impedance of the circuit.

As described above, according to the present invention, the load detection circuit short-circuits both ends of the coil after the application of the drive pulse ends and detects the induced current generated in the coil due to the free damping vibration of the rotor. The rotor load can be accurately and stably detected by short-circuiting the This makes it possible to incorporate a load detection device with excellent performance into a watch, ensuring stable pulse motor operation over a long period of time.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a pulse motor of an electronic wristwatch according to the present invention. 2 and 3 are diagrams showing a conventional circuit configuration, and FIG. 4 is a diagram showing a current waveform of a pulse motor drive coil in a conventional timepiece. FIG. 5 is a diagram showing the relationship between output torque and power consumption with respect to the drive pulse width of the pulse motor. FIG. 6 is a coil current waveform diagram when the motor is driven with a pulse width narrower than the conventional drive pulse. FIG. 7 is a diagram showing a circuit block of a timepiece according to the present invention. FIG. 8 is a diagram showing an example of a time chart of motor drive pulses by the circuit according to the present invention. FIG. 9 is a diagram showing a specific example of the block circuit of FIG. 8. FIG. 10 is a diagram showing an example of a time chart of the load detection section in FIG. 9.
FIG. 11 is a diagram showing an example of a pulse motor of an electronic wristwatch according to the present invention. FIG. 12 is a coil current waveform diagram during narrow pulse driving in the pulse motor of FIG. 11. 13 to 17 are diagrams showing other examples of the load detection section in FIG. 9. 25... Oscillation circuit, 26... Frequency dividing circuit, 27...
... Drive circuit, 28 ... Motor, 29 ... Motor load detection judgment circuit, 30 ... Control circuit, 31 to 33
... Narrow pulse drive signal, 34 ... Correction signal, 35
...Wide pulse drive signal, 59...Load judgment reference pulse, 60...No load detection signal, 61...Load detection signal.

Claims (1)

[Claims] 1. An oscillation circuit 25, a frequency division circuit 26 that frequency divides the output signal of the oscillation circuit, a drive circuit 27 that operates based on the output signal of the frequency division circuit, and a coil, a rotor, and a stator, and is driven by the drive circuit 27. In an electronic watch equipped with a pulse motor 28, means 14a, 1 short-circuit both ends of the coil after application of a drive signal to the pulse motor is completed.
5a, a load detection circuit 29 connected to the coil end and detecting an induced current generated in the coil due to free damping vibration of the rotor when both ends of the coil are short-circuited; the frequency dividing circuit 25 and the drive; It is connected between the circuits 27 and is controlled by the load detection circuit 29, and outputs the drive signal under normal conditions, and outputs the drive signal following the drive signal when the load detection circuit detects a heavy load state. An electronic timepiece characterized by comprising a control circuit 30 that outputs a correction signal having a larger driving force and the same polarity as the driving signal.