JPS62123749A - Cooling fin - Google Patents
Cooling finInfo
- Publication number
- JPS62123749A JPS62123749A JP26242885A JP26242885A JPS62123749A JP S62123749 A JPS62123749 A JP S62123749A JP 26242885 A JP26242885 A JP 26242885A JP 26242885 A JP26242885 A JP 26242885A JP S62123749 A JPS62123749 A JP S62123749A
- Authority
- JP
- Japan
- Prior art keywords
- fin
- shape
- memory alloy
- cooling fin
- fins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
不発明は形状記憶合金による冷却フィンに関し、特に半
導体チップの発熱量に対応してその表面積を変化させる
ことのできる冷却フィンに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a cooling fin made of a shape memory alloy, and particularly to a cooling fin whose surface area can be changed in accordance with the amount of heat generated by a semiconductor chip.
し背景技術〕
電子装置、部品におげろ熱設計の問題は重要であり、特
に、電子計算機の主要部分である論理素子、主記憶装置
などにおいては、その高速化、高性能化に対する請求か
ら熱設計の良否がシステムの性能を左右する項目の一つ
とまでいわれている。[Background Art] Thermal design issues are important for electronic devices and components, and in particular, the problem of thermal design, which is the main part of electronic computers such as logic elements and main memory devices, is increasing due to demands for higher speeds and higher performance. It is said that the quality of the design is one of the factors that determines the performance of the system.
一般に、論理索子の集積度が上るとそれに件ない発熱量
が増加する。Generally, as the degree of integration of logic elements increases, the amount of heat generated increases accordingly.
論理素子を基板に実装（搭載）する場合、その発熱ｉな
考慮する必戟があり、その実装に際しては、空冷による
エアーの流れ方向のエアーのよく当る場所に集積度の高
いＬＳＩを搭載シ１、一方比較的工７−が当る必要のな
い集積度の低いＬＳＩについては手前に搭載するという
ような、いちいちその発ｇ量ケ考慮した実装を行わねば
ならない。When mounting (mounting) a logic element on a board, it is necessary to take into consideration the heat generated by it, and when mounting it, it is necessary to mount a highly integrated LSI in a place where it is often exposed to air in the direction of air flow due to air cooling. On the other hand, for low-integration LSIs that require relatively little effort, the amount of gas generated must be taken into account when mounting them, such as mounting them in the front.
かかる実装は人手により行うことになり、煩雑であり、
また、上記のようにした場合にはそれに応じた信号配線
もいちいち考慮しなければならない。Such implementation must be done manually and is cumbersome.
In addition, in the case of doing as described above, the corresponding signal wiring must be considered one by one.
また、冷却フィンの設計に際しても、発熱量の異なる半
導体索子のごとに最適フィンの個別設計が必要となる。Furthermore, when designing cooling fins, it is necessary to individually design optimal fins for each semiconductor cord having a different amount of heat generated.
一方、いったん、合金にある形状を記憶させると、これ
を変形しても、一定温度以上に加熱すると、記憶したも
との形に戻ってしまう現象を示す形状記憶合金が各種の
用途に用いられ、温度スイ、クチや人工衛生のアンテナ
や継手などに使用され、ｊ
ている。On the other hand, shape-memory alloys are used in a variety of applications.Once an alloy is made to memorize a certain shape, even if it is deformed, it returns to its original shape when heated above a certain temperature. It is used for temperature switches, mouthpieces, artificial hygiene antennas and fittings, etc.
なお、上記熱設計について記載した文献の例として１９
８０年１月１５日（株）工業調査会発行ｒＩＣ化実装技
術ＪＰ２１１〜２４０があり、また、形状記憶合金につ
いて記載した文献の例として、（株）工業調査会発行［
電子材料Ｊ １９８２年９月号Ｐ４１〜４４がある。In addition, as an example of a document describing the above thermal design, 19
There are rIC implementation technology JP211-240 published by Industrial Research Institute Co., Ltd. on January 15, 1980;
Electronic Materials J September 1982 issue P41-44.
本発明は集積度に応じていちいちその半導体素子の実装
位置などを変える必要がない技術を提供することを目的
とする。An object of the present invention is to provide a technology that does not require changing the mounting position of semiconductor elements depending on the degree of integration.
また、本発明は発熱量の異なる半導体素子ごとに最適フ
ィンの個別設計を要しない技術を提供することを目的と
する。Another object of the present invention is to provide a technique that does not require individual designing of optimum fins for each semiconductor element having a different amount of heat generation.
不発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of non-invention are:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明では、形状記憶合金によるフィンを形
成することにより、当該フィンはその熱量に応じて変化
することができ、したがって、実装に際していちいち集
積度の相異を考慮する必裟がなく、また、半導体素子ご
とにいちいち最適のフィンを設計する手間を省くことが
できる。That is, in the present invention, by forming the fins using a shape memory alloy, the fins can change according to the amount of heat. Therefore, there is no need to consider differences in the degree of integration each time when mounting. , it is possible to save the effort of designing the optimal fin for each semiconductor element.
次に、本発明の詳細な説明する。 Next, the present invention will be explained in detail.
本発明は、第２図〜第６図に例示するような各種のフィ
ンに適用されるが、第１図に示すようなフィンに適用す
ることが好ましい。The present invention is applied to various types of fins as illustrated in FIGS. 2 to 6, but is preferably applied to fins as shown in FIG. 1.
このフィン１は、フィン高さＨとフィンピッチＰとの比
であるトング比（Ｈ／Ｐ）が５以下で、２２Ｘ１４ｍｍ
以下の空間中の放熱面積が３０００ｍｍ以上の、空気冷
却下の熱抵抗が６ ’Ｏ／ ｗ以下のものである。This fin 1 has a tongue ratio (H/P), which is the ratio of fin height H to fin pitch P, of 5 or less, and is 22 x 14 mm.
The heat dissipation area in the following space is 3000 mm or more, and the thermal resistance under air cooling is 6'O/w or less.
なお、第１図にて、Ｘはフィン間隔を示し、このＸは、
２．５ ｍ ｍ以上とするのがよい。In addition, in Fig. 1, X indicates the fin spacing, and this X is
It is preferable to set it to 2.5 mm or more.
本発明に使用される形状記憶合金としては、例えばＮ
ｉ −Ｃｒ系合金ＪＰＡｕ−Ｃｄ 、 Ｉ ｎ−Ｔ １
． 。As the shape memory alloy used in the present invention, for example, N
i-Cr-based alloy JPAu-Cd, I n-T 1
．． .
Ｃｕ−Ｚｎ、Ｃｕ−３ｎ、Ｎｉ −ＡＡ系合金などが例
示される。Examples include Cu-Zn, Cu-3n, and Ni-AA alloy.
形状記憶合金としては、Ｎ１−ｃｒ系合金であって、−
２０℃〜−１５０℃の範囲内で変化するのが好ましく、
特に、半導体素子における、ＰＮ接合温度のＴｊが８５
〜９０℃の状態で動作すること？考慮すると８５〜９０
℃のものが好ましい。The shape memory alloy is an N1-cr alloy, and -
It is preferable to change within the range of 20°C to -150°C,
In particular, when the PN junction temperature Tj in a semiconductor element is 85
Can it operate at ~90℃? 85-90 considering
℃ is preferred.
かかる形状ｎｃ ｔｉｔ合金により構成したフィンは例
えば、第６図Ｎ 、 ［１３＋に示すように、発熱量率
の時（低消費電力の時）〔第６図囚〕から、発熱最大の
時（高（ｆ’ｒ費電力の時）〔第６図１Ｊ３Ｄに、相互
に、半導体テップ（図示せず）の動作状況（消費電力）
により変化する発熱量に対応してフィン１の表面積が変
わるようにな−っている。For example, a fin constructed of an nc tit alloy having such a shape can vary from the time of heat generation rate (at low power consumption) [Figure 6] to the time of maximum heat generation (high (At the time of f'r power consumption) [Figure 6 1J3D shows the operating status (power consumption) of the semiconductor chip (not shown)
The surface area of the fin 1 changes in response to the amount of heat generated.
次に、第１図に図示したフィンを使用して成る半導体装
置の好ましい一例を第７図に示す。Next, FIG. 7 shows a preferred example of a semiconductor device using the fin shown in FIG. 1.
この装置は、ＳｉＣを放熱板として使用した高出力ロジ
ックＬＳＩパッケージの例で、ＳｉＣベース２の裏面に
、半導体素子３をＡｕ−３ｉ共晶４などにより固着し、
該素子３とリードフレーム５とをコネクタワイヤ６によ
り結線し、シールガラス７によりキャップ８？：取付け
し、さらに、ＳＩＣベース２０表面に接着剤９により形
状記憶合金より成る放熱フィン１を取付して成る。This device is an example of a high-power logic LSI package that uses SiC as a heat sink, and a semiconductor element 3 is fixed to the back surface of a SiC base 2 using Au-3i eutectic 4 or the like.
The element 3 and the lead frame 5 are connected by a connector wire 6, and a cap 8? is connected by a sealing glass 7. : attached, and furthermore, a heat radiation fin 1 made of a shape memory alloy is attached to the surface of the SIC base 20 with an adhesive 9.
半導体素子３は、例えばシリコン単結晶基板からなり、
周知の技術によってこのチップ内には多数の回路素子が
形成され、１つの回路機能が与えられている。回路素子
の具体例は、例えばＭＯＳトランジスタから成り、これ
らの回路素子によって例えばメモリや論理回路の回路機
能が形成され℃いる。The semiconductor element 3 is made of, for example, a silicon single crystal substrate,
A large number of circuit elements are formed within this chip using well-known techniques to provide a single circuit function. A specific example of the circuit element is, for example, a MOS transistor, and these circuit elements form a circuit function such as a memory or a logic circuit.
キャップ８は、例えばＳＩＣにより構成される。The cap 8 is made of, for example, SIC.
コネクタワイヤ６は、例えばＡｕ！やＡＬ線により構成
される。The connector wire 6 is made of, for example, Au! and AL wires.
シールガラス７に代えて、ムライトセラミックを使用し
てもよい。Mullite ceramic may be used instead of the seal glass 7.
し効 果〕
本発明によれば冷却フィンを形状記憶合金により構成し
たので、半導体素子の動作状況（消費電力）により変化
する発熱量に対応してその表面積が変化することができ
、マルチチップモジュールなどの実装において集積度の
高低を比較的汚えなくても済み、また、発熱量に応じた
フィンの個々の設計をしなくても済み、フィンの標準化
が可能である。Effect] According to the present invention, since the cooling fin is made of a shape memory alloy, its surface area can be changed in response to the amount of heat generated depending on the operating status (power consumption) of the semiconductor element. There is no need to worry about the degree of integration in implementation, and there is no need to design each fin according to the amount of heat generated, making it possible to standardize the fins.
本発明においては特に、フィンを第１図に示すような形
態とすることにより、放熱効果が高く、かつ、自在にフ
ィン形状を状況に応じて変化させ得ろ冷却フィンを得る
ことができ、さらに、前記実施例で示したＳ＋ｏｎＳｉ
方式のマルチチップモジュールにおいて同様に放熱
効果と自在にフィン形状を状況に応じて変化させ得る半
導体装置を得ることが可能となった。In particular, in the present invention, by forming the fins in the form shown in FIG. 1, it is possible to obtain cooling fins that have a high heat dissipation effect and whose fin shape can be freely changed according to the situation, and further, S+onSi shown in the above example
In the multi-chip module of this method, it has become possible to obtain a semiconductor device that has similar heat dissipation effects and can freely change the fin shape depending on the situation.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、不発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で拙々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on the examples, it should be noted that the invention is not limited to the above examples and can be modified without departing from the gist of the invention. Not even.
本発明は半導体装置のみならず、その他冷却フィンを必
要とする各種の電子装置部品に適用することができる。The present invention can be applied not only to semiconductor devices but also to various electronic device parts that require cooling fins.
第１図は本発明の実施例を示す冷却フィンの断面図、
第２図〜第５図は本発明の他の実施例を示すフィンの斜
視図、
第６図（Ａｌ 、 ［Ｂｌはそれぞれ本発明のフィンの
形状変化例を示す説明図、
第７図は本発明の実施例を示す半導体装置の断面図であ
る。
１・・・冷却フィン、２・・・ＳｉＣペース、３・・・
半導体素子、４・・・Ａｕ、５・・・リードフレーム、
６・・・コネクタワイヤ、７・・・シールガラス、８・
・・キャンプ、９・・・接着剤。
代理人 弁理士 小 川 勝 男
第 １ 図
第 ２ 図 第 ３ 図第
４ 図 第 ５ 図
第 ６ 図
第 ７ 図
〈FIG. 1 is a sectional view of a cooling fin showing an embodiment of the present invention, FIGS. 2 to 5 are perspective views of fins showing other embodiments of the present invention, and FIG. An explanatory diagram showing an example of shape change of the fin of the invention. Fig. 7 is a sectional view of a semiconductor device showing an embodiment of the invention. 1... Cooling fin, 2... SiC paste, 3...
Semiconductor element, 4...Au, 5...lead frame,
6... Connector wire, 7... Seal glass, 8...
...camping, 9...adhesive. Agent Patent Attorney Katsuo Ogawa Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7
Claims (1)
る電子装置用冷却フィン。 ２、フィンが、半導体装置用フィンで、温度８５〜９０
℃下で変化する特許請求の範囲第１項記載のフィン。[Claims] 1. A cooling fin for an electronic device, characterized in that it is made of a shape memory alloy. 2. The fin is a semiconductor device fin, and the temperature is 85 to 90.
The fin according to claim 1, which changes under temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26242885A JPS62123749A (en) | 1985-11-25 | 1985-11-25 | Cooling fin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26242885A JPS62123749A (en) | 1985-11-25 | 1985-11-25 | Cooling fin |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62123749A true JPS62123749A (en) | 1987-06-05 |
Family
ID=17375645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26242885A Pending JPS62123749A (en) | 1985-11-25 | 1985-11-25 | Cooling fin |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62123749A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7443683B2 (en) * | 2004-11-19 | 2008-10-28 | Hewlett-Packard Development Company, L.P. | Cooling apparatus for electronic devices |
-
1985
- 1985-11-25 JP JP26242885A patent/JPS62123749A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7443683B2 (en) * | 2004-11-19 | 2008-10-28 | Hewlett-Packard Development Company, L.P. | Cooling apparatus for electronic devices |
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