JPS62123715A - Formation of contact electrode - Google Patents

Formation of contact electrode

Info

Publication number
JPS62123715A
JPS62123715A JP26351085A JP26351085A JPS62123715A JP S62123715 A JPS62123715 A JP S62123715A JP 26351085 A JP26351085 A JP 26351085A JP 26351085 A JP26351085 A JP 26351085A JP S62123715 A JPS62123715 A JP S62123715A
Authority
JP
Japan
Prior art keywords
contact hole
wiring
insulating film
contact
alloy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26351085A
Other languages
Japanese (ja)
Inventor
Shuichi Matsuda
修一 松田
Hideaki Arima
有馬 秀明
Kiyoto Watabe
毅代登 渡部
Takeshi Yamano
剛 山野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP26351085A priority Critical patent/JPS62123715A/en
Publication of JPS62123715A publication Critical patent/JPS62123715A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To properly execute the embedding of the contact hole formed in the insulating film on the Si substrate, to flatly form the surface of the titled contact electrode and to prevent the disconnection of the wiring by a method wherein the contact hole is filled with a metal layer generating no alloy spike by a plating method in the interface between the Si substrate and the wiring layer. CONSTITUTION:An oxide film 2 is formed on a substrate 1 and a photo resist film 5 is coat-formed thereon. A dry etching is performed on the insulating film 2 with a CHF3 plasma to form a contact hole 3. An Ag layer 6 is precipitated in the hole 3 by plating in a thickness equal to that of the insulating film 2. Lastly, an Al or AlSi alloy layer is formed thereon by a sputtering method and a mask of the desired wiring pattern is formed thereon using the photo resist. A dry etching is performed through the mask to obtain an Al or AlSi alloy wiring layer 4. Thus, the embedding of the contact hole is properly executed, the surface of this contact electrode is flatly formed and the disconnection of the wiring is prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置のコンタクト電極の形成方法に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of forming contact electrodes for semiconductor devices.

〔従来の技術〕[Conventional technology]

第3図は、従来のコンタクト電極の一例を示す断面図で
、シリコン基板(1)上に酸化膜(2)を厚さ1μm程
度デポジションし、コンタクトホール(3)を形成しi たのら、MまたはM−合金配線(4)をスノくツタ形成
したものである。
FIG. 3 is a cross-sectional view showing an example of a conventional contact electrode, in which an oxide film (2) is deposited to a thickness of about 1 μm on a silicon substrate (1), and a contact hole (3) is formed. , M or M-alloy wiring (4) is formed in a vine pattern.

次に形成方法について説明する。すでにソース・ドレイ
ン領域(図示せず)の形成工程を終えたシリコン基板(
1)上に酸化膜(2)を1μmの厚さに形成する。次に
ホトレジストを前記酸化膜(2)の上に塗布し、紫外線
でマスクを用いて露光・現像し、22mX2μmのコン
タクトパターンをレジスル瘉成する。そして、これをマ
スクとして酸化膜(2)をCHF3ガスでトライエツチ
ングすることによりコンタクトホール(3)を形成する
。その後に全面にMまたはi 、す斜合金を全面にスパッタ蒸着し、更にホトリヤグラ
フィー及びエツチングで電極、配線(4)を形成したも
のが第3図断面になる。
Next, the formation method will be explained. A silicon substrate (
1) Form an oxide film (2) on top to a thickness of 1 μm. Next, a photoresist is applied on the oxide film (2), exposed to ultraviolet light using a mask, and developed to form a resist pattern of 22 m x 2 μm. Then, using this as a mask, the oxide film (2) is tri-etched with CHF3 gas to form a contact hole (3). Thereafter, M or i diagonal alloy was sputter-deposited on the entire surface, and electrodes and wiring (4) were further formed by photolithography and etching, as shown in the cross section of FIG.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところで、従来の形成方法では、第3図に示すようにコ
ンタクトホール(3)をテーパーエツチングする必要が
あり、また、コンタクトホール(3)の寸法が小さくな
り、12mX1μm程itこもfSると、異方性エツチ
ングで形成することになり、第4図に示すよう基こ、A
看またはA−合金配線(4)かコンタクトホール(3)
内にデポジションしにくくなり、配線(4)の膜厚が不
十分になって断線を生じるおそれがジ あるという問題点がある0ソた、AAVた(まA−g−
合金配線(4)かシリコン基板(1)iこ直接接するの
で、アロイ・スパイクの発生などの問題点かあった。
By the way, in the conventional forming method, it is necessary to taper-etch the contact hole (3) as shown in FIG. It will be formed by directional etching, and as shown in FIG.
A-alloy wiring (4) or contact hole (3)
There is a problem that the film thickness of the wiring (4) becomes insufficient and there is a risk of disconnection.
Since the alloy wiring (4) was in direct contact with the silicon substrate (1), there were problems such as the occurrence of alloy spikes.

この発明は以上のようrj問題点を解消するためにナサ
れたもので、コンタクトホールのテーパーエツチングを
する必要がな(、コンタクトホールの寸法が小さく−C
も配線の断限のない、しかも、アロイ・スパイクの発生
のないコンタクト電極の形成方法5:提供することを目
的とする。
This invention was developed in order to solve the RJ problem as described above, and there is no need to taper-etch the contact hole (the size of the contact hole is small -C).
Another object of the present invention is to provide a method 5 for forming a contact electrode, which has no disconnection in wiring and does not generate alloy spikes.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係るコンタクト電極の形成方法では、7リコ
ン基板上の絶縁膜に形成されたコンタクトホール内にメ
ッキ法によって、ノリコンとの界面でアロイ・スパーク
を生じない金属で埋め込んだ後i に、その上に、すまたはり一合金配線を形成する。
In the method for forming a contact electrode according to the present invention, a contact hole formed in an insulating film on a 7-recon board is filled with a metal that does not cause alloy sparks at the interface with the 7-recon board by plating, and then i. On top of this, Sari-alloy wiring is formed.

〔作 用〕[For production]

この発明では上述のようにコンタクトホール同にシリコ
ンとの界面でアロイ・スパイクを生じない金属で埋め込
むので、シリコン基体が直接Ag系の配線に接すること
がなく fAAJロイ・スパイクの問題は解消し、しか
も絶縁膜の表面は平坦になi るので、MまたはAAm合金配線は均一の厚さに形成さ
れ、断@などのおそれはr工< rzる。
In this invention, as mentioned above, the contact hole is filled with a metal that does not cause alloy spikes at the interface with silicon, so the silicon substrate does not come into direct contact with Ag-based wiring, and the fAAJ alloy spike problem is solved. Moreover, since the surface of the insulating film is flat, the M or AAm alloy wiring can be formed to have a uniform thickness, reducing the risk of breakage.

〔実施例〕〔Example〕

第1図A〜Dはこの発明の一実施例方法の主要工程段階
での状態を示す断面図で、従来例と同一符号は同等部分
を示す。ます、ソース・ドレインのような拡散領域(図
示せず)の形成工程を終えたシリコン基板(1)の上に
厚さIPn程度の酸化膜(2)を形成し、その上にホト
レジスト膜〔5)を0.7μmの厚さに塗布形成し、所
望パターンのマスクを介して紫外線によって露光・現像
をして1μmX1μm程度のコンタクトパターンを得る
(第1図A)。
FIGS. 1A to 1D are cross-sectional views showing the main process steps of a method according to an embodiment of the present invention, in which the same reference numerals as in the conventional example indicate equivalent parts. First, an oxide film (2) with a thickness of approximately IPn is formed on the silicon substrate (1) after the process of forming diffusion regions (not shown) such as sources and drains, and a photoresist film [5] is formed on it. ) is coated to a thickness of 0.7 μm, exposed to ultraviolet light through a mask with a desired pattern, and developed to obtain a contact pattern of approximately 1 μm×1 μm (FIG. 1A).

次に、このホトレジストマスク(4)を介して酸化膜(
2)にCHF3プラズマでドライエツチングを施してコ
ンタクトホール(3)を形成する(第1図B)0次に後
に説明する方法で、メッキによって、コンタクトホール
(3)内に絶縁膜(2)と等しい厚さ憂こA11層(6
)を析出させる(第1図C)。そして、最後にその上S
し 鴫こ騒ま1こはAe針金合金層スパッタ法で形成し、そ
の上≦こホトレジストで所望の配線パターンのマスク(
図示せず)を形成し、これを介してトライエl ッチ/グ施して、MまたはAn!FF合金配線層(4)
を得る(第1図D)。
Next, the oxide film (
2) is dry-etched with CHF3 plasma to form a contact hole (3) (Fig. 1B). Next, an insulating film (2) is formed in the contact hole (3) by plating using the method described later. Equal thickness Yuko A11 layer (6
) is precipitated (Fig. 1C). And finally S
The first layer is formed by sputtering an Ae wire alloy layer, and then a mask of the desired wiring pattern is formed using photoresist (
M or An! FF alloy wiring layer (4)
(Figure 1D).

第2図はこの実施例工程でA、9メツキに用いるメッキ
装置を示す断面図で、(7)は容器、(8)は容器(7
)内4こ収容されたンアン化銀カリウム〔KA!9(C
N)2〕の水溶液力)らするメッキ液、(9)は絶@物
からなる保持具、Qlは保持具(9)1こまってコンタ
クトホール側か露出するようにメッキ液(8)内に保持
されたシリコン基板、αηはメッキi (8)内6Cシ
リコン基板(10と対向して設けられたAJ ?!極、
(6)はU電極0η2正。
Figure 2 is a sectional view showing the plating equipment used for A and 9 plating in this example process, where (7) is a container and (8) is a container (7).
) contained 4 potassium silver oxides [KA! 9 (C
N) 2) Aqueous solution), (9) is a holder made of an absolute material, Ql is a holder (9), and the contact hole side is exposed in the plating solution (8). The held silicon substrate, αη is plated i (8) 6C silicon substrate (AJ?! pole provided opposite to 10,
(6) is U electrode 0η2 positive.

シリコン基板四セ負の電位を与える電源、(2)は容器
(7)の下に設けられメッキ液(8)をメッキの進行に
適した55〜65℃の温度薔こ保持する電熱器である。
A power source that provides a negative potential to the silicon substrate (2) is an electric heater installed under the container (7) to maintain the plating solution (8) at a temperature of 55 to 65 degrees Celsius, which is suitable for the progress of plating. .

以上のような状態で電源(6)から直流1流10A/d
m2程度を流すことによって、シリコン基板αQのコン
タクトホール内に0.1μmル程度の速度でAgが析出
する。
Under the above conditions, a single DC current of 10A/d is applied from the power supply (6).
By flowing approximately 0.1 μm of Ag into the contact hole of the silicon substrate αQ, Ag is deposited at a rate of approximately 0.1 μm.

以上実施例ではコンタクトホールを埋めるのにAjjを
用いたが、その他の貴金属は勿論、シリコンとの界面で
アロイ・スパイクを生じない金属であればよい。
Although Ajj was used to fill the contact holes in the above embodiments, other noble metals may be used as long as they do not cause alloy spikes at the interface with silicon.

〔発明の効果〕〔Effect of the invention〕

以上説明したようにこの発明では、7ソコン基板の上の
絶縁膜5こ形成しrこコンタクトホールをメッキ法によ
って、シリコンとの界面でアロイ・スパイクを生じない
金属で埋めるので、コンタクトホールが微細な場合でも
埋め込みは正しく行なわれ表面は平坦とt;す、その上
に形成する配線は断線を生じることtく確実に形成でき
る。配線はM系金属を用いてもシリコン基板に直接接し
ないのでアロイ・スパイクの問題が生じない。
As explained above, in this invention, the insulating film 5 is formed on the PC board and the contact holes are filled by plating with a metal that does not produce alloy spikes at the interface with silicon, so that the contact holes are fine. Even in such a case, if the embedding is performed correctly and the surface is flat, the wiring formed thereon can be reliably formed without causing disconnection. Even if an M-based metal is used for the wiring, the problem of alloy spikes does not occur because the wiring does not come into direct contact with the silicon substrate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例方法の主要段階での状聾を
示す断面図、第2図はこの実施例に用いるメッキ装置の
構成を示す断面図、第3図は従来のコンタクト電極の一
例を示す断面図、第4図は従来のコンタクト電極の微細
寸法の場合の他の例を示す断面図で5る。 図において、(1)はノリコン基板、(2)は絶縁膜(
酸化膜) 、 +3Jはコンタクトホール、(4)はA
看または、唄 A35−A合雀配線、(6)は埋込金属層である。 t2、図中同一符号は同一、または相当部分を示す0 代理人   早  瀬  憲  − ”<             (@        
    u電 心 \電 如
Fig. 1 is a sectional view showing the state of deafness at the main stages of the method according to an embodiment of the present invention, Fig. 2 is a sectional view showing the configuration of a plating apparatus used in this embodiment, and Fig. 3 is a sectional view of a conventional contact electrode FIG. 4 is a cross-sectional view showing one example, and FIG. 4 is a cross-sectional view showing another example of a conventional contact electrode with fine dimensions. In the figure, (1) is a Noricon substrate, (2) is an insulating film (
oxide film), +3J is a contact hole, (4) is A
In the A35-A playback wiring, (6) is a buried metal layer. t2, The same symbols in the diagram indicate the same or corresponding parts 0 Agent Ken Hayase − ”< (@
udenshin\dennyo

Claims (2)

【特許請求の範囲】[Claims] (1)シリコン基板の上に絶縁膜を形成する工程、上記
絶縁膜にその底面に上記シリコン基体が露出するコンタ
クトホールを形成する工程、シリコンと直接接してもそ
の界面部にアロイ・スパイクを発生しない金属でメッキ
法で、上記コンタクトホールを埋める工程、及び上記絶
縁膜の上に上記コンタクトホールを埋めた上記金属の上
を通りこれに電気的に接続されるようにアルミニウム、
またはアルミニウム・シリコン合金の配線を形成する工
程を備えたコンタクト電極の形成方法。
(1) A step of forming an insulating film on a silicon substrate, a step of forming a contact hole in the insulating film through which the silicon substrate is exposed on the bottom surface, and even if it comes into direct contact with silicon, alloy spikes will occur at the interface. a step of filling the contact hole with a metal that does not contain aluminum by a plating method;
Or a method for forming a contact electrode, which includes a step of forming an aluminum-silicon alloy wiring.
(2)コンタクトホールを埋める金属に銀などの貴金属
を用いることを特徴とする特許請求の範囲第1項記載の
コンタクト電極の形成方法。
(2) The method for forming a contact electrode according to claim 1, wherein a noble metal such as silver is used as the metal filling the contact hole.
JP26351085A 1985-11-22 1985-11-22 Formation of contact electrode Pending JPS62123715A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26351085A JPS62123715A (en) 1985-11-22 1985-11-22 Formation of contact electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26351085A JPS62123715A (en) 1985-11-22 1985-11-22 Formation of contact electrode

Publications (1)

Publication Number Publication Date
JPS62123715A true JPS62123715A (en) 1987-06-05

Family

ID=17390528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26351085A Pending JPS62123715A (en) 1985-11-22 1985-11-22 Formation of contact electrode

Country Status (1)

Country Link
JP (1) JPS62123715A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1271566A2 (en) * 2001-06-20 2003-01-02 Alps Electric Co., Ltd. Thin-film resistor and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1271566A2 (en) * 2001-06-20 2003-01-02 Alps Electric Co., Ltd. Thin-film resistor and method for manufacturing the same
EP1271566A3 (en) * 2001-06-20 2004-10-13 Alps Electric Co., Ltd. Thin-film resistor and method for manufacturing the same

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