JPS62122313A - Distortion compensating circuit of vcr of fet - Google Patents

Abstract

PURPOSE:To compensate the distortion of a signal caused when an input signal of a VCR of an FET is large by supervising a signal inputted to a drain of the FET on a control voltage inputted to the gate of the FET. CONSTITUTION:The titled circuit is a voltage controlled variable attenuator comprising a resistor 1 and a VCR of the FET 2 connected in series and controlling the attenuation of an output signal Vo to an input signal V1 by using a control voltage Vc applied between the gate and source of the FET 5. Since the input voltage V1 is superimposed on the control voltage Vc by a capacitor 3 and resistors 4, 5, a drain-gate resistance (gammaDS) fluctuation waveform 7 is obtained corresponding to a VGS waveform 6 as the gate-source voltage based on the superimposed input signal voltage V1. In selecting the resistors 5, 4 to bring the signal level of the input signal voltage V1 superimposed on the control voltage Vc to a proper value, the VGS waveform 6 and the gammaDS fluctuation waveform 7 are operated oppositely mutually and cancelled together, its gammaDS synthesis waveform 10 is made flat to compensate the distortion of the output signal voltage Vo.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a distortion compensation circuit for a CRC (voltage controlled resistor) that utilizes the linear region of an FETC field effect transistor (FETC field effect transistor), particularly when the input signal has a large analog signal. The present invention relates to a FET VCR distortion compensation circuit suitable for compensating for signal distortion that occurs when the signal is distorted.

[Background of the invention]

A well-known method of using a VCR that utilizes the linear region of a conventional FET is to control the drain-source resistance rns of the FET into which a signal is input using the gate-source voltage Vas. However, when the drain-source voltage yns of the input signal to the VCR of this FET is large, high-order distortion of the signal occurs due to the VDS dependence of rns, but sufficient consideration has not been given to this point.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a distortion compensation circuit for a FET VCR that compensates for signal distortion that occurs when an input signal is large in a FET VCR.

[Summary of the invention]

The present invention provides an FET that produces a distortion improvement effect by superimposing a signal input to the drain of the FET on a control voltage input to the gate of the FET in order to compensate for signal distortion caused by the VCR of the FET. This is a distortion compensation circuit for a VCR.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of an FET VCR distortion compensation circuit according to the present invention. In FIG. 1, 1 is a resistor, 2 is an FET (VCR), 3 is a capacitor, 4 is a resistor, and 5 is a resistor.

V is the input signal voltage, and Vo is the output signal voltage.

FIG. 2 is a circuit diagram (conventional circuit) without the capacitor 3 and resistor 4.5 shown in FIG. 1. Note that the same reference numerals or symbols indicate the same or corresponding parts throughout the drawings.

The circuit of Fig. 1 (Fig. 2) connects a resistor 1 and a VCR of FET 2 in series, and receives an input signal (voltage) VzVc from a control voltage VCVC applied between the gate and source of FET 5.
This is a voltage-controlled variable attenuator that controls the amount of attenuation of the output signal.

Now capacitor 3 and resistor 3.・When there is no 5 (Figure 2)
If the resistance value R1 of resistor 1 is R1, the drain-source resistance rns is FE75, then the following equation holds true.

Vo = Vt-rns/(R+rrrs)
111 FIG. 3 is a Vos rns characteristic diagram of FET5.

Figure 3 shows the drain-source Mt pressure V of FET5.
The characteristics of the drain-source resistance rns with respect to the gate-source voltage VOj with DS as a parameter are illustrated, and the fluctuation waveform 7 of 'rrrs with respect to the waveform 6 of VGj with VDS constant is illustrated.

In the circuit of FIG. 2, from the control voltage FEVc, that is, the gate-source voltage sVc, the input signal voltage V,
The amount of attenuation of the output signal voltage ro relative to the output signal voltage ro can be controlled.

Figure 4 is the VDI bus% characteristic diagram of FET5.
In the figure, the drain-source current ID with respect to the drain-source voltage VD5 with VO5 as a parameter.
The characteristics of E are exemplified, and the VDS of rns ``δVns /δIns (tangent line) when rns is large.
Dependencies are explained.

FIG. 5 is a VD:l''j)3 characteristic diagram of FET 5.

In FIG. 5, the characteristics of rns with respect to Vl)S with the VaS of FET 5 as a parameter are illustrated, and
An rns fluctuation waveform 9 with respect to a VDI waveform 8 with a constant VQS is illustrated. Also shown is an rns composite waveform 10 obtained by combining the rnx fluctuation waveform 7 and the rns deformation waveform 9ns fluctuation waveform 7 for the VGs waveform 6 in FIG. 3.

In the circuit shown in FIG. 2, when the input signal voltage V is large, VW dependence of rns causes V
Since the D1 waveform 8 becomes the rns'R11b waveform 9, high-order distortion occurs in the output signal voltage ro.

On the other hand, in the circuit shown in Fig. 1, the input signal voltage V is exclusively used by the capacitor 3 and the resistor 4.5 in addition to the control voltage, so that the input signal voltage V, which is superimposed on Since the ls fluctuation waveform 7 shown in FIG. 3 is obtained corresponding to the Vas waveform 6, the resistance 5, as shown in FIG.
Select the value of 4 and set the control voltage rc! /c By setting the signal level of the superimposed input signal voltage rI to an appropriate value,
Based on the input signal voltage superimposed on the rns fluctuation waveform 9 due to the Vl)g dependence of rxrs, the rkaS fluctuation waveform 7 due to the Vas waveform 6 act in opposite directions and cancel each other out, and their rns The composite waveform 10 becomes flat and compensates for the distortion of the output signal voltage 4.

As described above, according to this embodiment, in a voltage-controlled variable attenuator using a VCR of an FET, by providing a simple circuit for superimposing an input signal on a control voltage,
Distortion of the output signal due to CR can be compensated for.

In the above embodiment, a distortion compensation circuit of a variable attenuator using the VCR characteristics of an FET has been described, but the present invention is not limited thereto and can be similarly applied to, for example, an AGC amplifier.

〔Effect of the invention〕

As described above, according to the present invention, the signal level range of the input signal to the VCR can be expanded due to the distortion improvement effect of the FET on the VCR, and the distortion compensation circuit can be used to input the VCR control voltage (gate voltage). It is economical because it is a simple circuit that only superimposes signals.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the FET VCR distortion compensation circuit according to the present invention, FIG. 2 & FIG.
CH circuit (conventional circuit) diagram, Figure 6 shows P'ET's V
as rns characteristic diagram, Figure 4 is the same < Ins I
The ns% characteristic diagram and FIG. 5 are the same <Vns-τDS characteristic diagrams. 1...Resistor 2...FET3...Capacitor 4.5...Outside resistance...Control voltage
V,...Input signal voltage V,...Output signal voltage 'p, 1 Figure Force 2 Figure 37
5th □ DS

Claims (1)

[Claims] In the VCR circuit of the FET where the signal is input, the FET
A distortion compensation circuit for an FET VCR, which includes a circuit for superimposing a VCR input signal input from the drain of the FET onto a VCR control voltage applied to the gate of the FET.