JPS62122227A - Method for evaluation of impurity doped layer - Google Patents

Method for evaluation of impurity doped layer

Info

Publication number
JPS62122227A
JPS62122227A JP26111485A JP26111485A JPS62122227A JP S62122227 A JPS62122227 A JP S62122227A JP 26111485 A JP26111485 A JP 26111485A JP 26111485 A JP26111485 A JP 26111485A JP S62122227 A JPS62122227 A JP S62122227A
Authority
JP
Japan
Prior art keywords
layer
impurity
ion implantation
substrate
measurement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26111485A
Other languages
Japanese (ja)
Inventor
Tadashi Suzuki
匡 鈴木
Nobuyoshi Kashu
夏秋 信義
Shizunori Oyu
大湯 静憲
Yasuo Wada
恭雄 和田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP26111485A priority Critical patent/JPS62122227A/en
Publication of JPS62122227A publication Critical patent/JPS62122227A/en
Pending legal-status Critical Current

Links

Landscapes

  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To make it possible to evaluate an impurity doped layer formed by use of high-energy ion implantation easily and accurately by forming a layer made of the material which enables it to selectively remove only that layer easily on a substrate of a semiconductor device. CONSTITUTION:On a substrate 12, a film 1 made of the material which can be removed selectively and easily is formed and after high-energy ion implantation into that substrate, only the upper layer is selectively removed by etching. For that, a conventional method can be applied to the evaluation of an impurity layer. In this case, the thickness of a deposited layer can be determined on the basis of the LSS theory. For example, when B (boron) is implanted is Si(silicon) with 1 MeV energy, a projection range Rp is 1.76mum and a standard deviation DELTARp is 0.136mum. A range within which an impurity concentration (CI) is seemed to be significant is + or -3DELTARp. Accordingly, it becomes enough to remove 1.35mum of Si. By converting this by an inhibition performance of the material of the deposited layer, the thickness of the deposited layer can be obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置における不純物分布の評価方法に
係り、特に、高エネルギーイオン打込みを用いて形成し
た不純物ドープ層の評価に好適な方法に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for evaluating impurity distribution in a semiconductor device, and particularly relates to a method suitable for evaluating an impurity doped layer formed using high-energy ion implantation. .

〔従来の技術〕[Conventional technology]

半導体装置における、イオン打込みや熱拡散などの方法
を用いて形成した不純物ドープ層の評価は1通常以下の
ような方法を用いてなされる。即ち、1)陽極酸化など
による表面層のエツチングと四探針法による層抵抗測定
のくり返しを用いた深さ方向キャリヤ濃度分布の測定、
2)二次イオン質量分析法(SIMS)やオージェ電子
分光分析法(AES)とイオンビームによるスパッタエ
ツチングの併用による深さ方向不純物濃度分布の測定、
3)ニゲフォー下後方散乱光(RBS)による深さ方向
不純物濃度分布の測定、などである。
Evaluation of impurity-doped layers formed using methods such as ion implantation and thermal diffusion in semiconductor devices is usually performed using the following methods. That is, 1) measurement of the carrier concentration distribution in the depth direction by repeatedly etching the surface layer by anodic oxidation etc. and measuring the layer resistance by the four-probe method;
2) Measurement of depthwise impurity concentration distribution by a combination of secondary ion mass spectrometry (SIMS) or Auger electron spectroscopy (AES) and sputter etching using an ion beam;
3) Measurement of impurity concentration distribution in the depth direction using RBS (lower backscattered light).

この中で、特に、方法1)は、測定精度および簡便さの
点で、最も一般的な方法である。
Among these, method 1) is the most common method in terms of measurement accuracy and simplicity.

イオン打込み法の1つの領域として、打込みエネルギー
がM e V程度の高エネルギーイオン打込みが、近年
盛んに研究されている。高エネルギーイオン打込みは、
例えば、ソリッド・ステート・テクノロジー、 198
4年、5月号、第211頁から第216頁(Solid
 5tate Technology、 pp211−
216 、 May (1984))に記載のように、
深い領域の不純物分布の正確な制御や、該方式ではじめ
て実現できるような新構造デバイスの作製などを可能と
するという利点を有している。イオン打込みを行なった
場合、イオンは、深さ方向にLSS理論に従って、第2
図のように、投影飛程Rp、標準偏差ΔRPで分布する
。高エネルギーイオン打込みの領域では1例えば、シリ
コン(以下Siと記す)中にほう素(以下Bと記す)を
打込みエネルギーI M e Vで打込む場合、Rpは
1.76μm、ΔRpは0.136μm  となる。
As one area of ion implantation methods, high-energy ion implantation in which the implantation energy is on the order of M e V has been actively researched in recent years. High energy ion implantation
For example, solid state technology, 198
4, May issue, pages 211 to 216 (Solid
5tate Technology, pp211-
216, May (1984)),
This method has the advantage of allowing precise control of impurity distribution in deep regions and the creation of devices with new structures that can only be realized using this method. When ion implantation is performed, the ions are deposited in the second direction in the depth direction according to the LSS theory.
As shown in the figure, the projected range Rp and the standard deviation ΔRP are distributed. In the area of high-energy ion implantation, 1. For example, when boron (hereinafter referred to as B) is implanted into silicon (hereinafter referred to as Si) with implantation energy IMeV, Rp is 1.76 μm and ΔRp is 0.136 μm. becomes.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

高エネルギーイオン打込みを用いて形成した不純物ドー
プ層を評価する場合、上記従来方法を用いると、上記方
法1)および2)では、不純物濃度が有意な値を示す深
さまで1表面層をエツチングするのに多くの時間を要し
、方法2)および3)では、深い領域における測定精度
に難点があるため5分布が正確に求まらないという問題
があった。
When evaluating an impurity-doped layer formed using high-energy ion implantation, using the conventional method described above, in methods 1) and 2), one surface layer is etched to a depth where the impurity concentration shows a significant value. Methods 2) and 3) have a problem in that the 5-distribution cannot be accurately determined because of the difficulty in measuring accuracy in deep regions.

本発明の目的は、上記問題点を鑑み、高エネルギーイオ
ン打込みによって深い領域に形成されている不純物ドー
プ層の評価を、正確に、かつ、簡便に行なうことのでき
る方法を提供することにある。
SUMMARY OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a method that can accurately and easily evaluate an impurity-doped layer formed in a deep region by high-energy ion implantation.

〔問題点を解決するための手段〕[Means for solving problems]

高エネルギーイオン打込みを用いた場合に、その不純物
^度分布のat!I定が難しくなるのは、不純物が深い
領域にのみ分布するからである。つまり、不純物濃度の
値としては、有意でない層(21t!I定しても意味の
ないWI)が厚いために、該層の下に位置している81
11定すべき層の情報がおおい隠されてしまうのである
。従って、測定無意味な上層を簡単に除去することがで
きれば、従来方法と同様に、測定すべき層の不純物分布
を求めることができる。
When high-energy ion implantation is used, the impurity degree distribution at! The reason why I is difficult to determine is that impurities are distributed only in deep regions. In other words, since the impurity concentration value is not significant (WI, which is meaningless even if determined by 21t!I) is thick, 81
11, much of the information that should be determined is hidden. Therefore, if the upper layer, which is meaningless to measure, can be easily removed, the impurity distribution of the layer to be measured can be determined in the same manner as in the conventional method.

〔作用〕[Effect]

本発明は、イオンを打込む基板(例えば、Si)の上部
に、ウェットエッチなどを用いて容易にその層のみ選択
除去可能な材質の層を形成することにより、高エネルギ
ーイオン打込みを用いて形成した不純物ドープ層の評価
を、簡便に、かつ、正確に行なうことを可能とするもの
である。第1図にその概念図を示す。基板2上部に、容
易に選択除去可能な材質の膜1を形成し、その基板へ高
エネルギーイオン打込みした後、上層のみを選択除去す
ると、不純物層評価に従来方法をそのまま適用すること
ができるようになる。ここで、該堆積層の厚さは、既に
確立されている理論であるLSS理論を基にして決定す
ることができる。例えば、S1中にBを打込みエネルギ
ー1− M e Vで打込む場合、Rpは1.76μm
、ΔRpは0.136 pmであるから、不純物濃度が
有意と考えられる範囲は±3ΔRpであるので、S ’
iで1.35 μm分。
The present invention uses high-energy ion implantation to form a layer of a material that can be easily selectively removed using wet etching or the like on top of a substrate (e.g., Si) into which ions are to be implanted. This makes it possible to easily and accurately evaluate impurity-doped layers. Figure 1 shows its conceptual diagram. By forming a film 1 made of a material that can be easily selectively removed on top of the substrate 2, implanting high-energy ions into the substrate, and then selectively removing only the upper layer, the conventional method can be directly applied to evaluate the impurity layer. become. Here, the thickness of the deposited layer can be determined based on the LSS theory, which is an already established theory. For example, when implanting B with an energy of 1-M e V during S1, Rp is 1.76 μm.
, ΔRp is 0.136 pm, so the range in which the impurity concentration is considered significant is ±3ΔRp, so S'
i for 1.35 μm.

除去すればよいことになる。これを堆積層の材質の阻止
能で換算すれば、堆積層の厚さが求まる。
It would be best to remove it. If this is converted by the stopping power of the material of the deposited layer, the thickness of the deposited layer can be determined.

例えば、堆積層を5iOzとすれば、Siと5iOzの
I M e VのBに対する阻止能の比は、1.13で
あるから厚さは1.52μmとなる。他の基板、堆積層
、打込みイオン種の組合せに対しても、同様の手順で適
切な堆積層の厚さを求めることができる。第3図は、基
板をSi、堆積層をSiO2とした場合の、加速電圧と
適切な堆積層の膜J5の関係を示したものである。B、
リン(以下Pと記す)、ヒ素(以下Asと記す)の3種
類のイオン種に対する結果を示した。本図では、堆積層
の適切な膜厚の範囲を斜線で示しである。ここで、上限
は堆積層除去後の表面がRpの位置になる場合で、下限
は上記の表面から3ΔRPの位置がRpになる場合に相
当する。また、この堆積層は、不純物層評価の精度を確
保するために、膜質、膜厚とも均一に形成されているこ
とが必要である。
For example, if the deposited layer is 5 iOz, the ratio of the stopping power of Si and 5iOz for I M e V to B is 1.13, so the thickness is 1.52 μm. Appropriate thicknesses of the deposited layers can be determined using the same procedure for other combinations of substrates, deposited layers, and implanted ion species. FIG. 3 shows the relationship between the accelerating voltage and the appropriate deposited layer J5 when the substrate is Si and the deposited layer is SiO2. B,
The results are shown for three types of ion species: phosphorus (hereinafter referred to as P) and arsenic (hereinafter referred to as As). In this figure, the appropriate thickness range of the deposited layer is indicated by diagonal lines. Here, the upper limit corresponds to the case where the surface after removing the deposited layer is at the position Rp, and the lower limit corresponds to the case where the position 3ΔRP from the above surface is the position Rp. Further, this deposited layer needs to be formed with uniform film quality and film thickness in order to ensure accuracy of impurity layer evaluation.

〔実施例〕〔Example〕

以下1本発明を実施例を用いて詳細な説明する。 The present invention will be described in detail below using examples.

〔実施例1〕 n型、(100)面方位、10Ω−印のSi基板上に、
低圧CVD法により、5iOz ′P&0.7μm堆積
した後、Asを打込みエネルギー2.5Mev、打込み
量IX 1011Icw−”ティ、t ’:/打込ミし
、N2雰囲気中で1000℃30分のアニールで活性化
した。 HzO/ HF = 20 / 1 ノxッチ
ング液で5jOzを選択除去し、陽極酸化と層抵抗測定
のくり返しによって、活性不純物′a度分布を求めた結
果が第3図である6表面濃度は、5×10”am−8で
あり、濃度が最大となるのは表面から0.6μmの位置
で2X101G国−8であった。
[Example 1] On an n-type, (100) plane orientation, 10Ω-marked Si substrate,
After depositing 5iOz'P and 0.7μm by low-pressure CVD, As was implanted at an energy of 2.5Mev and an implantation amount of IX 1011Icw-"T,t':/, followed by annealing at 1000°C for 30 minutes in a N2 atmosphere. HzO / HF = 20 / 1 5JOz was selectively removed using a Nox etching solution, and the active impurity distribution was determined by repeating anodization and layer resistance measurements. The results are shown in Figure 3. The concentration was 5×10”am-8, and the maximum concentration was 2×101G country-8 at a position 0.6 μm from the surface.

本実施例によれば、不純物濃度が有意でない表面層を陽
極酸化の反復によって除去する必要がなく、1回のエツ
チングで簡単に除去できるため、測定時間の短縮が可能
となる。1回の陽極酸化によって除去できる81層の厚
さは、電解液: KNOa過飽和水溶液、10mA/f
f1(試料面での電流密度)定電流という通常の測定の
条件のもとで、1分間の酸化で20層m程度である。従
って、本実施例におけるSiO2(堆積層)相当のSi
を除去するのに、約50回の陽極酸化が必要となり、酸
化膜を除去する工程の時間も考慮すれば、約1.5 時
間の測定時間の短縮が本発明による得られたことになる
According to this embodiment, it is not necessary to remove the surface layer whose impurity concentration is not significant by repeated anodic oxidation, and it can be easily removed by one etching process, thereby making it possible to shorten the measurement time. The thickness of 81 layers that can be removed by one anodic oxidation is as follows: Electrolyte: KNOa supersaturated aqueous solution, 10 mA/f
f1 (current density at the sample surface) Under normal measurement conditions of constant current, oxidation for 1 minute results in approximately 20 layers m. Therefore, in this example, Si equivalent to SiO2 (deposited layer)
Approximately 50 times of anodic oxidation are required to remove the oxide film, and if the time required for the process of removing the oxide film is also considered, the measurement time can be shortened by approximately 1.5 hours by the present invention.

〔実施例2〕 実施例1と同仕様のSi基板上に、ポジ形ホトレジス1
−AZ−III(シラプレー社製)を厚さ1.7μm塗
布した後、Pを打込みエネルギーI M e V、打込
み量I X 10 ”cn−”でイオン打込みした。レ
ジスト除去液およびプラズマ酸素アッシャ−によりレジ
ストを除去した後、SIMSを用いて不純物濃度分布を
求めた結果が第4図である。本実施例における測定結果
3とともに1本発明の方法を用いずに同様のイオン打込
みを行なった場合のSIMSにより求めた不純物濃度分
布4も示しである。ここで、本発明の方法を用いない場
合の測定値では、深さ方向の位置は本実施例のレジスト
層分相当のSiの厚さを引いた値を用いである。
[Example 2] A positive photoresist 1 was placed on a Si substrate with the same specifications as in Example 1.
-AZ-III (manufactured by Silapray) was applied to a thickness of 1.7 μm, and then P ions were implanted at an implantation energy of IMeV and an implantation amount of I.times.10 "cn-". FIG. 4 shows the results of impurity concentration distribution determined using SIMS after removing the resist using a resist removal solution and a plasma oxygen asher. In addition to measurement results 3 in this example, impurity concentration distribution 4 obtained by SIMS when similar ion implantation was performed without using the method of the present invention is also shown. Here, in the measured values when the method of the present invention is not used, the position in the depth direction is a value obtained by subtracting the thickness of Si equivalent to the resist layer of this example.

従来法による測定では1本実施例の値よりも全体に大き
めであり、よりテイルを引いて分布となっている。これ
は、SIMSでは深い領域の不純物濃度を測定する場合
、スパッタ用イオンによるノックオン効果やスパッタし
た表面が皿型になると表面層の不純物も同時に検出され
てしまうなどの影響のために、真の不純物濃度より高め
に測定される傾向があるためである。従って1本実施例
においては、これらの影響を軽減できるため、測定結果
の信頼性は、従来法に比較して大幅に高くなる。
When measured using the conventional method, the values are generally larger than those of this embodiment, and the distribution is more tailed. This is because when SIMS measures impurity concentrations in deep regions, it is difficult to detect true impurities due to effects such as the knock-on effect of sputtering ions and the fact that if the sputtered surface becomes dish-shaped, impurities in the surface layer are also detected at the same time. This is because it tends to be measured higher than the concentration. Therefore, in this embodiment, since these influences can be reduced, the reliability of the measurement results is significantly higher than that of the conventional method.

〔実施例3〕 n型、(100)面方位のG a A s基板上に低圧
CVD法により5iaNaを0.3μm堆積した後、S
iを打込みエネルギーI M e V、打込み量5X1
0”■−2でイオン打込みし、煮沸リン酸により5ia
N4を選択除去した。第5図は、SIMSにより求めた
不純物濃度分布である6本実施例においても、実施例2
と同様に、従来法による測定では誤差が大きく、深部に
なるほど本発明を用いた測定値3よりも従来法の測定値
4が大きな値となっている。
[Example 3] After depositing 0.3 μm of 5iaNa on an n-type, (100)-oriented GaAs substrate by low-pressure CVD, S
i is implanted, energy I M e V, implantation amount 5X1
Ion implantation at 0"■-2 and 5ia with boiling phosphoric acid.
N4 was selectively removed. FIG. 5 shows the impurity concentration distribution obtained by SIMS in Example 6 as well as in Example 2.
Similarly, the measurement using the conventional method has a large error, and the deeper the depth, the larger the measurement value 4 using the conventional method is than the measurement value 3 using the present invention.

〔実施例4〕 これ迄の実施例では、イオン打込みされた不純物の深さ
方向分布測定について述べたが、本実施例では、不純物
のウェーハ面内分布について述べる。従来からイオン打
込み層の打込み均一性を評価するためには、四探針法に
よる層抵抗測定法が用いられていたが、高エネルギイオ
ン打込み技術により形成した不純物ドープ層の評価には
直接使用出来ない。この理由は、第1図に示した如く。
[Embodiment 4] In the previous embodiments, measurement of the depth distribution of ion-implanted impurities has been described, but in this embodiment, the distribution of impurities within the wafer surface will be described. Conventionally, the layer resistance measurement method using the four-probe method has been used to evaluate the implantation uniformity of ion implantation layers, but it cannot be used directly to evaluate impurity-doped layers formed by high-energy ion implantation technology. do not have. The reason for this is as shown in FIG.

表面に不純物のドープされない層が形成されている為で
ある。本発明によれば、基板表面に第3図に示した膜p
1の選択除去可能な層を形成する!Jtにより、層抵抗
の測定が可能になる。例えばBイオンを2 M e V
で5 X 10 ”cm−2打込んだn型(100)1
0Ω・−シリコンウェーハ上の層抵抗分布は、該選択除
去可能な層の膜厚を1.3μmとする事で測定が可能で
あった。この第3図に示した膜厚との差異の理“由は、
四探針測定法において、針圧により針が被測定基板中に
0.5−1μm貫入するためで、第3図に示した膜厚の
下限は、測定時の針の針圧により0.5−1μm程度薄
くなる。
This is because a layer not doped with impurities is formed on the surface. According to the present invention, the film p shown in FIG.
Form a selectively removable layer of 1! Jt allows measurement of layer resistance. For example, B ion is 2 M e V
5 x 10”cm-2 implanted n-type (100)1
The layer resistance distribution on the 0Ω·− silicon wafer could be measured by setting the thickness of the selectively removable layer to 1.3 μm. The reason for the difference in film thickness from that shown in Figure 3 is as follows.
In the four-probe measurement method, the needle penetrates 0.5-1 μm into the substrate to be measured due to the needle pressure, and the lower limit of the film thickness shown in Figure 3 is 0.5 μm due to the needle pressure during measurement. -It becomes thinner by about 1 μm.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、高エネルギーイオン打込みを用いて深
い領域に形成した不純物層を評価するに際して、測定精
度の向上、測定時間の短縮の効果がある。特に1本発明
においては、新しい不純物濃度測定方法を用いるのでは
なく、従来の測定技術をそのまま用いつつ、上記効果が
得られるため。
According to the present invention, when evaluating an impurity layer formed in a deep region using high-energy ion implantation, it is possible to improve measurement accuracy and shorten measurement time. In particular, one aspect of the present invention is that the above-mentioned effects can be obtained while using conventional measurement techniques as they are, rather than using a new impurity concentration measurement method.

その実施効果は大である。特にウェーハ面内の打込み量
均−性を評価する為には不可欠な手段となる。
The effects of its implementation are significant. In particular, it is an indispensable means for evaluating the implantation amount uniformity within the wafer surface.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は1本発明の詳細な説明するための曲線図、第2
図は従来方法を説明するための曲線図。 第3図乃至第6図は本発明の詳細な説明するための曲線
図である。 第1図 第 2 図 着面力・3I)距鉦 カロl電fi−(Me−シー2 kfjiaJ”; の+fllJM  (、ayt)I
 〆 図 左市η・うQ距離(〃す
Figure 1 is a curve diagram for explaining the present invention in detail;
The figure is a curve diagram for explaining the conventional method. 3 to 6 are curve diagrams for explaining the present invention in detail. Fig. 1 Fig. 2 Attachment surface force 3I) +fllJM (, ayt) I
〆 Figure left city η・UQ distance (

Claims (1)

【特許請求の範囲】[Claims] 半導体装置内部に不純物ドープ層を形成する工程の前に
、該半導体装置により選択除去可能な材質の層を、半導
体装置上部に堆積する工程を含み、かつ不純物ドープ層
を形成する工程の後に、該堆積層を除去する工程を含む
ことを特徴とする不純物ドープ層の評価方法。
Before the step of forming an impurity doped layer inside the semiconductor device, a step of depositing a layer of a material selectively removable by the semiconductor device on the semiconductor device, and after the step of forming the impurity doped layer, A method for evaluating an impurity-doped layer, the method comprising the step of removing a deposited layer.
JP26111485A 1985-11-22 1985-11-22 Method for evaluation of impurity doped layer Pending JPS62122227A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26111485A JPS62122227A (en) 1985-11-22 1985-11-22 Method for evaluation of impurity doped layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26111485A JPS62122227A (en) 1985-11-22 1985-11-22 Method for evaluation of impurity doped layer

Publications (1)

Publication Number Publication Date
JPS62122227A true JPS62122227A (en) 1987-06-03

Family

ID=17357282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26111485A Pending JPS62122227A (en) 1985-11-22 1985-11-22 Method for evaluation of impurity doped layer

Country Status (1)

Country Link
JP (1) JPS62122227A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043292A (en) * 1990-05-31 1991-08-27 National Semiconductor Corporation Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures
JPH06318560A (en) * 1993-05-07 1994-11-15 Nec Corp Measurement of thermowaves
JP2008232448A (en) * 2007-03-16 2008-10-02 Daikin Ind Ltd Fin tube-type heat exchanger and air conditioner
CN104114953A (en) * 2012-02-10 2014-10-22 大金工业株式会社 Indoor unit for air conditioner

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5043292A (en) * 1990-05-31 1991-08-27 National Semiconductor Corporation Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures
JPH06318560A (en) * 1993-05-07 1994-11-15 Nec Corp Measurement of thermowaves
JP2008232448A (en) * 2007-03-16 2008-10-02 Daikin Ind Ltd Fin tube-type heat exchanger and air conditioner
CN104114953A (en) * 2012-02-10 2014-10-22 大金工业株式会社 Indoor unit for air conditioner

Similar Documents

Publication Publication Date Title
US3808068A (en) Differential etching of garnet materials
US4151011A (en) Process of producing semiconductor thermally sensitive switching element by selective implantation of inert ions in thyristor structure
JPS62122227A (en) Method for evaluation of impurity doped layer
EP0076570A2 (en) Method of making alloyed metal contact layers on integrated circuits
JP3439584B2 (en) Method for measuring concentration distribution of element in solid and sample for measurement
US5882947A (en) Method for probing the error of energy and dosage in the high-energy ion implantation
US3635767A (en) Method of implanting impurity ions into the surface of a semiconductor
JPS58106822A (en) Impurity introducing method
US6221726B1 (en) Process for fabricating device structures for real-time process control of silicon doping
JP4083878B2 (en) Impurity measurement method
Kostka et al. Electrical properties of silicon implanted with boron ions of MeV energy
JPS5853514B2 (en) Manufacturing method of semiconductor device
JP3287317B2 (en) How to make an analysis sample
US3976377A (en) Method of obtaining the distribution profile of electrically active ions implanted in a semiconductor
JPH11126810A (en) Measurement method of crystal defect
RU1800501C (en) Process of manufacture of bipolar transistors
SU563704A1 (en) Method of manufacturing the semi-conductors
JP2917937B2 (en) Method for analyzing impurity concentration distribution of semiconductor device
JPH0645617A (en) Manufacture of single-crystal thin-film member
JPS58151027A (en) Etching method
JPH03136325A (en) Manufacture of semiconductor device
JPH08203969A (en) Crystal defect measuring method of semiconductor substrate
CN115280472A (en) Method for controlling donor concentration in single crystal silicon substrate
JP3329295B2 (en) Impurity concentration measurement method
JPS5910051B2 (en) How to measure ion implantation amount