JPS62122137A - Mounting method for ic chip - Google Patents
Mounting method for ic chipInfo
- Publication number
- JPS62122137A JPS62122137A JP60261006A JP26100685A JPS62122137A JP S62122137 A JPS62122137 A JP S62122137A JP 60261006 A JP60261006 A JP 60261006A JP 26100685 A JP26100685 A JP 26100685A JP S62122137 A JPS62122137 A JP S62122137A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- chip
- pedestal
- pressure
- wiring substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はＩＣチップの実装に係り、特にはんだバンプ型
ＩＣチップに強い熱ストレスを加えないで実装しようと
するものに好適な実装法に関するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to IC chip mounting, and particularly to a mounting method suitable for mounting solder bump type IC chips without applying strong thermal stress. be.
はんだバンプ型ＩＣチップの実装は、例えば特開昭５８
−１５７１４７号公報に示されるように、はん。Mounting of solder bump type IC chips is described, for example, in JP-A-58
As shown in Publication No.-157147, han.
だを溶融して接続している。It is connected by melting it.
類似構成の一例を図を用いて説明する。An example of a similar configuration will be explained using a diagram.
第２図に示すように、ＩＣチップ１ははんだバンプ２を
有し【成っている。そのはんだは温度サイクル・ストレ
スに強い、例えばＰｂ／５ｕ−９Ｖ５〜９Ｑ／／１ｏの
様な高融点はんだより成っている。第３図に示す配線基
板３はセラミック基板にタングステン−ニッケルよりな
る金属層のペデスタル６と絶縁およびはんだ流れ防止用
のダム４をもうける。そのペデスタル６に前述のはんだ
を迎えはんだ等によりはんだ突起５をもうける。As shown in FIG. 2, an IC chip 1 has solder bumps 2. The solder is made of a high melting point solder, such as Pb/5u-9V5-9Q//1o, which is resistant to temperature cycling stress. The wiring board 3 shown in FIG. 3 has a pedestal 6 made of a metal layer made of tungsten-nickel and a dam 4 for insulating and preventing solder flow on a ceramic board. The aforementioned solder is applied to the pedestal 6 and solder protrusions 5 are formed using solder or the like.
それらの組合せは第４図に示すようにはんだバンプ２と
はんだ突起５にフラックスを塗布して、約３３０Ｃのリ
フロー炉を通して、溶融一体化する。As shown in FIG. 4, these combinations are melted and integrated by applying flux to the solder bumps 2 and solder protrusions 5 and passing through a reflow oven at about 330C.
高温で溶融するために、焼付き等が生じるためにフラッ
クスの除去がむずかしく、接合面に５ｎ−Ｎｉ合金が成
虫されて、接続信頼性を低下させることもある。Since it is melted at a high temperature, it is difficult to remove the flux due to seizures, etc., and 5n-Ni alloy may be deposited on the joint surface, reducing connection reliability.
同一基板に共晶はんだ部品も搭載する場合にＩＣチップ
のりフロ一時に、それらの部品のペデスタル部の表面ま
たは迎えはんだ面に酸化膜が発生して、共晶はんだ部品
の接続信頼性が低下する。When eutectic solder parts are also mounted on the same board, an oxide film is formed on the pedestal surface or receiving solder surface of those parts during the IC chip glue flow, reducing the connection reliability of the eutectic solder parts. .
また前記文献によると、絶縁フィルムに部品導通用に円
柱状の導電性ゴムを表裏に３５μ扉突起するよう忙もう
け、ＬＳＩの旭バンプとガラス板のＭペデスタルを接続
している。本方法は導電性ゴムの構造が複雑であること
および３部品の会せ精度が高いことの欠点を有する。Further, according to the above-mentioned document, a cylindrical conductive rubber is provided on the insulating film so as to protrude 35μ on the front and back for component conduction, and the Asahi bump of the LSI and the M pedestal of the glass plate are connected. This method has the drawbacks of a complicated structure of the conductive rubber and a high degree of accuracy in the assembly of the three parts.
本発明の目的は作業性の良いはんだバンプ型ＩＣチップ
の実装方法を提供することにある。An object of the present invention is to provide a method for mounting a solder bump type IC chip with good workability.
本発明は加圧導電性材料と構成部品の突起を利用して、
常温にて組立て作業を行なって、接続を得ようとするも
のである。The present invention utilizes pressurized conductive materials and protrusions on components to
The purpose is to perform assembly work at room temperature to obtain connections.
以下、本発明の一実施例を第１図により説明する。 An embodiment of the present invention will be described below with reference to FIG.
絶縁基板上に導体配線やペデスタル６をもうけ、その上
部に絶縁材料を有し、ペデスタル６の周囲にははんだ流
れ防止のダム４を有する。Conductor wiring and a pedestal 6 are provided on an insulating substrate, an insulating material is provided on the top of the conductor wiring, and a dam 4 is provided around the pedestal 6 to prevent solder flow.
そのペデスタル６にはんだ突起５を施して、配線基板３
となす。一方、ＩＣチップ１ははんだバンプ２を有して
いるものである。A solder protrusion 5 is applied to the pedestal 6, and the wiring board 3
Nasu. On the other hand, the IC chip 1 has solder bumps 2.
これらの組立ては配線基板３の上に加圧導電性ゴム７を
乗せ、更にＩＣチップ１をはんだバンプ２と迎えはんだ
５の中心線が合うように搭載したのち押え金具８をのせ
て取付ネジ９にて、締付けて固定する。To assemble these, place the pressurized conductive rubber 7 on top of the wiring board 3, then mount the IC chip 1 so that the center lines of the solder bumps 2 and the pick-up solder 5 are aligned, then place the presser metal fitting 8 and tighten the mounting screws 9. Tighten and secure.
この押え金具８はコ状の弾性材料よりなる金具で両側よ
りはさみこんで固定する方法に変更しても良い。This holding fitting 8 may be changed to a U-shaped fitting made of an elastic material and fixed by being sandwiched from both sides.
本発明によれば加熱なしで、接続を得られるので、焼け
こげ等の７ラククス除去が不要となり、また５ｎ−Ｎｉ
合金が成虫されないので、接続信頼性を損うこともない
。According to the present invention, connection can be obtained without heating, so there is no need to remove 7 lacs of burnt parts, and 5n-Ni
Since the alloy is not immature, there is no loss of connection reliability.
また同一基板に本ＩＣチップと共晶はんだ部品を搭載し
ても共晶はんだ部品の接続信頼性を損５ことがない。Furthermore, even if the present IC chip and the eutectic solder parts are mounted on the same board, the connection reliability of the eutectic solder parts will not be compromised.
またはんだ突起５は配線基板３を迎えはんだすることに
より容易に１００μｍ程度の高さをもうけることが出来
る。よって作業性も向上する。The solder projections 5 can easily have a height of about 100 μm by soldering onto the wiring board 3. Therefore, work efficiency is also improved.
第１図は本発明の一実施例の実装状態の縦断ｌよ
面図、第２図から第４図を従来品の例を示し、第２図は
ＩＣチップの縦断面図、第３図は配線基板の縦断面図、
第４図はそれらの実装状態の縦断面図である。
１・・・ＩＣチップ、 ２・・・はんだバンプ、
６・・・配線基板、 ４・−・ダム、５・・・は
んだ突起、 ６・・・ペデスタル、７・・・加圧導
電性ゴム、８・・・押え金具。
第 １ 口
第２図
第４図FIG. 1 is a vertical cross-sectional view of an embodiment of the present invention in a mounted state, FIGS. 2 to 4 show examples of conventional products, FIG. 2 is a vertical cross-sectional view of an IC chip, and FIG. Vertical cross-sectional view of the wiring board,
FIG. 4 is a longitudinal cross-sectional view of their mounting state. 1... IC chip, 2... Solder bump,
6... Wiring board, 4... Dam, 5... Solder protrusion, 6... Pedestal, 7... Pressurized conductive rubber, 8... Holder fitting. Part 1 Figure 2 Figure 4
Claims (1)
ルにはんだ突起をもうけ、上記配線基板に加圧導電性ゴ
ムを置き、ペデスタルのはんだ突起とはんだバンプが一
致するようにＩＣチップを搭載したのち、押え板をのせ
、取付ネジにて加圧導電性ゴムを圧縮して、バンプ部を
導通させたことを特徴とするＩＣチップ実装方法。1. The wiring board has wiring and a pedestal, a solder projection is formed on the pedestal, a pressurized conductive rubber is placed on the wiring board, and an IC chip is mounted so that the solder projection of the pedestal and the solder bump match. , an IC chip mounting method characterized in that a presser plate is placed and a pressurized conductive rubber is compressed with a mounting screw to make the bump portion conductive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60261006A JPS62122137A (en) | 1985-11-22 | 1985-11-22 | Mounting method for ic chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60261006A JPS62122137A (en) | 1985-11-22 | 1985-11-22 | Mounting method for ic chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62122137A true JPS62122137A (en) | 1987-06-03 |
Family
ID=17355743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60261006A Pending JPS62122137A (en) | 1985-11-22 | 1985-11-22 | Mounting method for ic chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62122137A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009059745A (en) * | 2007-08-30 | 2009-03-19 | Kyocera Corp | Light emitting device |
| US10522504B2 (en) | 2015-11-04 | 2019-12-31 | Stmicroelectronics S.R.L. | Semiconductor device and corresponding method |
-
1985
- 1985-11-22 JP JP60261006A patent/JPS62122137A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009059745A (en) * | 2007-08-30 | 2009-03-19 | Kyocera Corp | Light emitting device |
| US10522504B2 (en) | 2015-11-04 | 2019-12-31 | Stmicroelectronics S.R.L. | Semiconductor device and corresponding method |
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