JPS62120692A - Bubble file memory device - Google Patents

Abstract

PURPOSE:To prevent the missetting of a cassette number by providing a means for detecting the simultaneous setting of the same cassette number to two or more cassettes. CONSTITUTION:The titled device is provided with a system controller 21 for controlling the whole checking operation, a maintenance controller 22 for outputting all cassette numbers. To respective bubble memory cassettes as a test at the time of checking, a cassette number overlap detecting circuit 10 for detecting the overlapped setting of each cassette number, a flip flop 23, and an alarm display means 24 for displaying an alarm. Even if the same cassette number is set to two or more cassettes in error, the overlap can be detected and the operation is inhibited, so that the defective operation of the bubble buffer memory, the damage of data and circuits, etc., can be removed.

Description

[Detailed Description of the Invention] [Summary] The present invention has means for detecting when the same cassette number is set to two or more cassettes at the same time in a bubble file memory device. This is a bubble file memory device that can prevent accidents in which two or more cassettes are accessed simultaneously during memory access operations, ensure operation, and protect circuits.

[Industrial application field]

The present invention relates to a bubble file memory device that can prevent the same cassette number from being set and operated on two or more cassettes at the same time.

[Prior art technology]

Magnetic bubble memory and memory devices are highly reliable storage devices with features such as having no mechanically moving parts, being nonvolatile, and having a low error rate. Because of its small size and large capacity, a bubble file memory device has been developed in which each element is in a cassette format and a plurality of cassettes can be loaded and accessed at the same time.

FIG. 4 shows the configuration of a conventional bubble file memory device. In FIG. 4, when an external host accesses the memory, it always selects a predetermined cassette based on the cassette number.

Now, when a cassette number is written to the cassette register from the external host, the cassette number designation signal BC3TO~2 is transferred to all cassettes via the motherboard (there are eight cassettes, so it is designated with a 3-bit signal). ing).

Inside the cassette, the transferred signals BC5TO~2 and the cassette number setting signal B S preset by the cassette number setting switch in each cassette are used.
WQ~2 are compared by respective comparators, and if they are all equal, a select signal C8 indicating that the cassette has been selected is output, and the cassette becomes operable and memory access is performed.

[Problem that the invention seeks to solve]

However, in the above operation, even if the cassette number setting switch of the bubble memory cassette is set incorrectly and two or more cassettes are set to the same cassette number, and that cassette number is selected by the controller with the BC3TO~2 signal. , the C3 signals of the plurality of cassettes are all output and become operational.

However, since the controller cannot detect that multiple cassettes are selected at the same time, the data is transferred as is, and the outputs from the multiple cassettes collide on the motherboard, potentially resulting in malfunction or damage to data and elements. It had some problems.

In order to eliminate the above-mentioned problems, the present invention has means for detecting when the same cassette number is set to two or more cassettes at the same time, thereby preventing erroneous setting of cassette numbers. The purpose is to provide a bubble file memory device.

[Means for solving problems]

In order to solve the above problems, the present invention has a cassette number check control means, and as a specific means, a system controller (
21), maintenance controller that test outputs all cassette numbers to each bubble memory cassette during check (
22), a cassette number duplication detection circuit (10) and a flip-flop (23) for detecting duplication of cassette number settings;
and alarm display means (24) for displaying a warning.

[For production]

In the above means, the cassette number check control means includes a cassette number duplication detection circuit (10), a system controller (21), and a maintenance controller (22).
), a flip-flop (23), and an alarm display means (24), and when the power is turned on or when any of the plurality of bubble memory cassettes is attached or detached, the system controller changes the interface bus to a maintenance bus. After switching to , the maintenance controller is instructed to start a check operation, and following the above operation, the maintenance controller performs an operation of sequentially transferring all cassette numbers to a plurality of bubble memory cassettes in parallel via the maintenance bus, Each time the cassette numbers are transferred, the cassette number duplication detection circuit compares the cassette select signals C3O-C37 output from each of the plurality of bubble memory cassettes, and simultaneously detects the cassette select signals from two or more bubble memory cassettes. is output, a duplicate detection signal is output to the flip-flop, and after completing the transfer operation of all cassette numbers, the system controller reads the contents of the flip-flop, and outputs the duplicate detection signal to the flip-flop. If the detection signal is set, the system controller displays a warning using the alarm display means, and after switching and connecting the interface bus to the external host, performs an operation to transfer a memory access prohibition signal to the external host. conduct.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail.

(Configuration of bubble file memory device (FIGS. 1 and 2)) FIG. 1 shows the configuration of a bubble file memory device according to the present invention.

Up to eight bubble memory cassettes 30 to 37, ie cassette O to cassette 7, can be installed and are connected to the motherboard 1. The controller 2 that controls the motherboard l is
A bubble memory controller 27 that controls each memory during access, and a cassette register 2 that holds the cassette number.
6. System register 25 that holds the system state;
a system controller 21 that manages the entire system;
A maintenance controller 22, a flip-flop 23, and an interface unit 28 that perform control during maintenance
etc., and further comprises a system controller 21
and the interface unit 28, there are a control line and a bus changeover switch SW2 for switching between the maintenance bus 221 from the maintenance controller 22 and the interface bus 29 from the external host, a LOCR signal for detecting attachment/detachment of a cassette, Control lines for the alarm lamp 24 and the like are connected. In addition, a bubble memory control signal 271 is input in parallel from the bubble memory controller 27 to each bubble memory cassette 30 to 37 via the motherboard 1, and from the cassette register 26, a cassette/node number designation signal BC3TO to 2 (hereinafter referred to as BC3TO~2) is input. Next, a cassette/node number duplication detection circuit 10 is configured on the motherboard 1, and select signals C3O to Cding from the bubble memory cassettes 30 to 37 are input, and a duplication detection signal CERR is sent to the controller 2.
The output of the flip-flop 23 is inputted to the system controller 21. On the other hand, each bubble memory cassette 30 to 37 has a cassette number setting switch 5W302, 312...
372, and compares the cassette number setting signal BSWO~2 (hereinafter abbreviated as BSWO~2) set here with the signal BC3TO~2;
1,...371.

Next, FIG. 2 shows the external structure of the bubble file memory device. The motherboard 1 and controller 2 shown in FIG. 1 are housed in a housing 4, and a bubble memory cassette 30
37 can be attached to the cassette holder 7. At the bottom of the cassette holder 7, there is an alarm lamp ALA as shown in Figure 1.
RM24. and a READY lamp indicating an operational state5. A POWER lamp 6 indicating power on is arranged.

Further, each bubble memory cassette 30 to 37 has a LOCK screw 8 for fixing the cassette linked to the lock switch SW1, and a BUSY lamp 9 indicating that the bubble memory cassette is in operation. Also, inside each cassette holder 7 is a lock switch S shown in FIG.
There is a WI.

(Operation of bubble file memory device (FIGS. 1 and 2)) Next, the operation of the bubble file memory device will be explained.

First, the system controller 21 detects the LOCK signal of the lock switch SW1 that is input when the bubble memory cassette is removed from the cassette holder 7, and puts the device in an operation prohibited state. In this state, the cassette is attached and detached, and when the cassette attachment and detachment are completed and the LOCK signal is input again, the system controller 21 switches the interface bus 29 to the maintenance bus 221 by the BSEL signal, and sends the CH to the maintenance controller 22.
Outputs ECK signal. On the other hand, when the power is turned on, the device is unconditionally disabled, the bus is switched, and the CHECK signal is output.

The maintenance controller 22 sends signals BC3TO to cassette register 26 based on this CHECK signal.
2, eight types of cassette number data are sequentially sent in. As a result, the contents of the cassette register 26 are sent to all bubble memory cassettes 30-37 via the motherboard 1, and the signals BSWO-
2 is compared by each comparator 301 to 371. As a result, if all 37 signals are equal, one of the select signals C3O to C37 indicating that the cassette has been selected is sent to the cassette number duplication detection circuit 10 on the motherboard 1, respectively.

The cassette number duplication detection circuit 10 checks whether multiple select signals are output at the same time, that is, whether multiple cassettes have been set to the same cassette number, and if they are duplicated, the CERR signal is output. It is output to the flip-flop 7 in the controller 2. This flip-flop 23 holds the output when the CERR signal is set (after being cleared once by the CHECK signal from the system controller 21, it is in a state of waiting for the CERR signal which is CLOCK). Therefore, the system controller 21 can recognize the presence or absence of duplication by looking at the output of the flip-flop 23 after the maintenance controller 22 finishes sending out all cassette numbers and sends the END signal. When a duplication occurs, the system controller 21
sends an ALARM signal to turn on the alarm lamp 24, and also sends an ALARM signal to the system register 25 and interface section 2.
8. The host side can be notified of the operation inhibited state via the interface bus 29.

Note that at the time when the END signal is sent from the maintenance controller 22, the interface section 28 is switched and connected to the host side interface bus by the BSEL signal. If no duplication occurs in the above checking operation, the system controller 21 notifies the host side that the system is normal via the system register 25 and returns to the operable state (READY lamp 5 turns on).

(Configuration of cassette number duplication detection circuit (Fig. 3)) Next,
FIG. 3 shows the configuration of a cassette/node number duplication detection circuit to enable the above operation. 30 bubble memory cassettes each
The select signals from C33 to C37 are input to the addend input A, addend input B, and carry input Cn of the adder 101.
C35 are input to the same inputs A, B, and Cn of the full adder 102, respectively, and CS6. C37 is the same input A of the full adder 103.
.

A high level signal 2φ1 is input to its carry input Cn. The sum outputs Σ1 to Σ3 of the full adders 101 to 103 are input to each input A, B, and Cn of the full adder 104, and each carry output C1 of the full adders 101 to 104 is inputted to each input A, B, and Cn of the full adder 104.
+1 is input to the AND circuit 105;
A duplication detection signal CERR is output from.

In the above configuration, each select signal cso-cS7 is
It is a negative logic signal that indicates a match when it is low level, and
The overlap detection signal CERR is also a negative logic signal that indicates overlap when it is at a low level.

(Operation of cassette number duplication detection circuit (Figure 3)) Next,
The operation of the cassette number duplication detection circuit having the above configuration will be explained.

In FIG. 3, CERR is "L" (low level), and the condition for detecting a duplicate state is whether any two or more of C33 to C35 are "L" (matching state). Therefore, if we consider dividing C8 into three blocks, two or more of C33 to C35 are “
L", 6, which force is 11 among C33 to C35 -L-
So, C3'6. The minimum necessary and sufficient condition for duplicate detection is that one of the six conditions in which either C37 is "L" occurs.

First, to detect conditions 1 to 3, full adders 101 to 1
Use c n + 1 of 03. For example, in case of condition 1,
If two or more of C8O to C32 are "L", the carry of the full adder 101 will not be enough for the output C1+1, so C
n+1 becomes "L", and the output of the AND circuit 105 becomes "L"<=CERR). Conditions 2 and 3 can be considered in exactly the same way.

Next, in order to detect conditions 4 to 6, full adders 101 to 1
The sum outputs Σ1 to Σ3 of 03 and the carry output c n + 1 of the full adder 104 are used.

In this case, when any one of the three inputs for each of the full adders 101 to 103 becomes "L" (the other two are "H"), the carry output C1+1 is output, so C1+1 becomes "
However, the sum output Σ is always low. This Σ
1 to Σ3 are input to the full adder 104. In this way, in the same manner as in the detection of conditions 1 to 3, for example, in the case of condition 4, both Σ1 and Σ2 become "L", so carry output of 104 is achieved without causing carry Cn + 1. Cn+
1 becomes "L", and the output of AND circuit 105 also becomes "L".
(=CERR). Conditions 5 and 6 can be considered in exactly the same way.

With the above operation, when the cassette numbers overlap, a negative logic overlap detection signal CERR is output.

In this case, the flip-flop 23 shown in FIG. 1 is naturally configured to operate in negative logic.

As described above, the embodiments shown in FIGS. 1 to 3 make it possible to prevent malfunctions due to duplication of cassette numbers.

〔Effect of the invention〕

According to the present invention, even if the same cassette number is mistakenly set to two or more cassettes, the duplication can be detected and the operation will be disabled, resulting in malfunction of the bubble file memory and data corruption. , it becomes possible to prevent damage to the circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a bubble file memory device according to the present invention. FIG. 2 is an external block diagram of a bubble file memory device according to the present invention. FIG. 3 is a circuit diagram of a cassette number duplication detection circuit according to the present invention. FIG. 4 is a block diagram of a conventional bubble file memory device. DESCRIPTION OF SYMBOLS 10... Cassette number duplication detection circuit, 12... System controller, 22... Maintenance controller, 23... Flip-flop, 24... Alarm lamp, 25... System register, 26... Cassette Register, BC3TO~2...Cassette number designation signal, BSWO
~2...Cassette number setting signal, C3O-C37...
・Select signal, CERR...duplication detection signal.

Claims (1)

[Claims] 1) In a bubble file memory device having a plurality of bubble memory cassettes (30 to 37), the same cassette number identified during memory access operation is set to two or more of the bubble memory cassettes at the same time. a cassette number check control means (10, 21, 22, 23, 24) that checks whether or not the memory access operation is set at the same time, performs a warning operation and prohibits the memory access operation when the memory access operation is set at the same time;
) A bubble file memory device comprising: 2) The cassette number check control means includes a cassette number duplication detection circuit (10) and a system controller (2).
1), a maintenance controller (22), a flip-flop (23), and an alarm display means (24), and the system After switching the interface bus to the maintenance bus, the controller instructs the maintenance controller to start a check operation, and following the above operation, the maintenance controller sequentially sends all cassette numbers to multiple bubble memory cassettes in parallel via the maintenance bus. The cassette number duplication detection circuit compares the cassette number matching signals outputted from each of the plurality of bubble memory cassettes and simultaneously performs a transfer operation for each cassette number. When a cassette number matching signal is output, a duplication detection signal is output to the flip-flop, and after the transfer operation of all cassette numbers is completed, the system controller reads the contents of the flip-flop and transfers the data to the flip-flop. If the duplication detection signal is set to , the system controller displays a warning using the alarm display means, and after switching and connecting the interface bus to the external host, transfers a memory access operation prohibition signal to the external host. A bubble file memory device according to claim 1, characterized in that the bubble file memory device performs the following. 3) The number of bubble memory cassettes is 8, and the cassette number duplication detection circuit (10) receives an augend input into which cassette number matching signals from the first to third bubble memory cassettes are input, and an addend. a first full adder (101) having a carry input and a carry input;
A second full adder (102) receives the cassette number matching signal from the seventh and eighth bubble memory cassettes, and a second full adder (102) receives the cassette number matching signal from the seventh and eighth bubble memory cassettes and one high level signal. 3 full adders (1
03), a fourth full adder (104) which also receives the sum outputs of the first to third full adders, and a fourth full adder (104) which receives the carry outputs of the first to fourth full adders. and an AND circuit (105) that outputs the duplication detection signal, and the cassette number matching signal output from each bubble memory cassette and the duplication detection signal output from the cassette number duplication detection circuit are each at a low level. 3. The bubble file memory device according to claim 2, wherein the bubble file memory device is a negative logic signal that becomes valid when .