JPS62120044A - Bonding method for flat plate - Google Patents

Bonding method for flat plate

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Publication number
JPS62120044A
JPS62120044A JP26030485A JP26030485A JPS62120044A JP S62120044 A JPS62120044 A JP S62120044A JP 26030485 A JP26030485 A JP 26030485A JP 26030485 A JP26030485 A JP 26030485A JP S62120044 A JPS62120044 A JP S62120044A
Authority
JP
Japan
Prior art keywords
layer
psg
substrates
bonded
heating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26030485A
Other languages
Japanese (ja)
Inventor
Akitomo Tejima
手島 章友
Takashi Ito
隆司 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP26030485A priority Critical patent/JPS62120044A/en
Publication of JPS62120044A publication Critical patent/JPS62120044A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To bond without solvent nor stress by forming the layer of thermoplastic substance film on two Si wafers, and pressurizing and heating the layers in the laminated state. CONSTITUTION:SiO2 films 12, 22 of 0.5mum thick are deposited as an impurity diffusion preventing substance layer on Si wafers 11, 21, and PSG films 13, 23 are similarly deposited in thickness of 2.5mum thereon by an ambient pressure CVD. Thus formed bonding substrates 14, 24 are superposed so that the layers 13, 23 are contacted with each other on two quartz supporting bases 15, filled in an electric furnace 17 in the state placed on a columnar quartz block 16, and bonded by pressurizing and heating. When PSG of 14mol% of P2O5 density is used, the two substrates 14, 24 are completely fusion-bonded by pressurizing with 26g/cm<2> and heating at 950 deg.C with the block 16. When the bonded substrates 14, 24 where pulverized and finely examined, separation of the substrates due to unbonding was not observed.

Description

【発明の詳細な説明】 〔概要〕 2枚の平板の表面に熱可塑性物質の層を形成し、この層
面を合せた状態で加圧、加熱を施すことにより両手板を
接着させる。
[Detailed Description of the Invention] [Summary] A layer of thermoplastic material is formed on the surfaces of two flat plates, and the two hand plates are bonded together by applying pressure and heating with the layer surfaces brought together.

〔産業上の利用分野〕[Industrial application field]

本発明は2枚の平板相互の接着技術に関するもので、さ
らに詳しく言えば、シリコン(St)ウェハ等の高精度
の平板同士を均一かつ強固に接着せしめる技術に関する
ものである。
The present invention relates to a technique for adhering two flat plates to each other, and more specifically, to a technique for uniformly and firmly bonding high-precision flat plates such as silicon (St) wafers together.

〔従来の技術〕[Conventional technology]

Siウェハの如き平板を他の平板に接着する技術は、例
えばシリコン・オン・インシュレータ(SOI)の変型
例において用いられる。SOIは絶縁物の上の非品性シ
リコンをレーザビームの如きエネルギービームによって
再結晶化し、絶縁物の上に単結晶のシリコン層を形成す
る技術であるが、非品性シリコンを再結晶化しても完全
な単結晶シリコン層を得ることが難しい。
The technique of bonding flat plates, such as Si wafers, to other flat plates is used, for example, in silicon-on-insulator (SOI) variants. SOI is a technology that recrystallizes impure silicon on an insulator using an energy beam such as a laser beam to form a single crystal silicon layer on the insulator. It is also difficult to obtain a complete single crystal silicon layer.

SOIにおいて結晶性のよい単結晶シリコンを得るため
に開発された技術を第2図の断面図を参照して説明する
と、シリコン基板31に高濃度ボロンイオン(B+)を
注入して高濃度ボロン注入層32を作り、その上にシリ
コンをエピタキシャル成長してシリコンエピタキシャル
層33(以下単にエピタキシャル層という)を作り、エ
ピタキシャル層の表面を酸化して5i02膜34を形成
し、その上に燐・シリケート・ガラス(PSG ’)を
成長してPSG膜35を形成する。
The technology developed to obtain single-crystal silicon with good crystallinity in SOI will be explained with reference to the cross-sectional view in FIG. A layer 32 is formed, silicon is epitaxially grown on it to form a silicon epitaxial layer 33 (hereinafter simply referred to as an epitaxial layer), the surface of the epitaxial layer is oxidized to form a 5i02 film 34, and phosphorus, silicate, glass is formed on top of it. (PSG') is grown to form a PSG film 35.

他方、基板36(例えば石英基板)を用意し、その上に
psc膜37を形成し、PSG膜35.37を接着する
On the other hand, a substrate 36 (for example, a quartz substrate) is prepared, a PSC film 37 is formed thereon, and PSG films 35 and 37 are adhered thereto.

第3図は基板36が第2図の場合と倒置した図であるが
、同図を参照すると、シリコン基板31を機械的に研削
する。この研削においてエピタキシャル層33だけを残
すことは難しいので、KOH−IPA−HlOの混合液
を用いてシリコン基板31の研削後残ったものをエツチ
ングすると、Stの方が高濃度ボロンよりもエツチング
速度が50倍程度速いので、前記のエツチングにおいて
高濃度ボロン注入層はストッパーとして働き、シリコン
基板31は完全に除去された後に高濃度ボロン注入層3
2が残る。
FIG. 3 is a diagram in which the substrate 36 is inverted compared to the case in FIG. 2. Referring to FIG. 3, the silicon substrate 31 is mechanically ground. Since it is difficult to leave only the epitaxial layer 33 during this grinding, when the remaining material after grinding the silicon substrate 31 is etched using a mixed solution of KOH-IPA-HlO, the etching rate of St is higher than that of highly concentrated boron. Since etching is about 50 times faster, the high concentration boron implanted layer 3 acts as a stopper in the etching described above, and the high concentration boron implanted layer 3 is etched after the silicon substrate 31 is completely removed.
2 remains.

次に、HNO3−CH5COOH−HFの混合液を用い
て高濃度ボロン注入層32をエツチングすると、高濃度
ボロン注入層のエツチング速度はSiに比べて70倍程
度速く、このエツチングでエピタキシャル層はストッパ
ーとなり、第3図に示される如り5i02膜34の上に
エピタキシャル層33が残る。このエピタキシャル層は
1μm程度の厚さに形成するが、それは理想的なシリコ
ン基板と同程度に結晶性の良い単結晶シリコンであり、
そこに所望のデバイスを形成する。
Next, when the high concentration boron injection layer 32 is etched using a mixed solution of HNO3-CH5COOH-HF, the etching rate of the high concentration boron injection layer is about 70 times faster than that of Si, and this etching turns the epitaxial layer into a stopper. , an epitaxial layer 33 remains on the 5i02 film 34, as shown in FIG. This epitaxial layer is formed to a thickness of about 1 μm, but it is made of single crystal silicon with good crystallinity comparable to that of an ideal silicon substrate.
Form the desired device there.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来は、溶剤を含む高分子系接着剤を2枚の平板間に挿
入し、均一な圧力を加えることにより接着を行っていた
。しかし、この方法では溶剤が抜けにくいため、全面に
わたる強固な接着は困難である。特に、接着させた2枚
の平板(例えばSiウェハ等)の一方を、研磨やエツチ
ングにより薄膜化し、その薄膜(前記の例ではエピタキ
シャル層)中にデバイスを作成するような用途の場合、
残留溶剤自体、さらにはそれによる不均一接着で生じる
応力等によって薄膜にクラックなどが発生し、デバイス
に悪影響を及ぼすおそれがある。
Conventionally, a polymer adhesive containing a solvent was inserted between two flat plates, and bonding was performed by applying uniform pressure. However, with this method, the solvent is difficult to escape, making it difficult to achieve strong adhesion over the entire surface. In particular, in applications where one of two bonded flat plates (for example, a Si wafer) is made into a thin film by polishing or etching, and a device is created in the thin film (epitaxial layer in the above example),
Cracks may occur in the thin film due to the residual solvent itself and stress caused by uneven adhesion caused by the residual solvent, which may adversely affect the device.

本発明は上述のような従来技術の問題を解決するため創
作されたもので、予め2枚の平板上に熱可塑性物質の層
を形成しておき、それらを合せた状態で加圧、加熱を施
すことにより融着を行い、溶剤や応力の入らない接着が
可能となる方法を提供することを目的とする。
The present invention was created to solve the problems of the prior art as described above, and involves forming a layer of thermoplastic material on two flat plates in advance, applying pressure and heating to the combined state. The object of the present invention is to provide a method that enables fusion bonding by applying a bonding agent to the bonding material, thereby making it possible to bond without using solvents or stress.

〔問題点を解決するための手段〕[Means for solving problems]

第1図は本発明実施例の断面図で、同図において、11
はSiウェハ、12はSiO2膜(不純物拡散防止物質
)、13はpsc膜(熱可塑性物質)、21はSiウェ
ハ、22は5iOz膜(不純物拡散防止物質)、 、2
3はPSG膜(熱可塑性物質膜)であり、Siウェハ、
SiO+膜、PSG膜でそれぞれ接着用基板14.24
を構成する。
FIG. 1 is a sectional view of an embodiment of the present invention, and in the same figure, 11
is a Si wafer, 12 is a SiO2 film (impurity diffusion prevention material), 13 is a psc film (thermoplastic material), 21 is a Si wafer, 22 is a 5iOz film (impurity diffusion prevention material), , 2
3 is a PSG film (thermoplastic material film), which is a Si wafer,
Adhesion substrate for SiO+ film and PSG film 14.24 respectively
Configure.

本発明は、熱可塑性物質膜13.23、望ましくはPS
G、 BSG (ボロンシリケートガラス)等の層を2
枚のSiウェハ11.21上に形成し、この層面を合せ
た状態で加圧、加熱を施すことにより熱可塑性物質の層
を十分軟化もしくは溶融させ両Stウェハ11゜21を
融着させるものである。
The invention comprises a thermoplastic film 13.23, preferably PS
2 layers of G, BSG (boron silicate glass), etc.
It is formed on two Si wafers 11 and 21, and by applying pressure and heat with the layer surfaces aligned, the thermoplastic layer is sufficiently softened or melted to fuse the two St wafers 11 and 21. be.

〔作用〕[Effect]

この接着剤としての熱可塑性物質にガラス状物質を使え
ば、固化したとき平板に加わる応力は比較的小さくなる
。特に、上記平板がSiウェハのとき、熱可塑性物質と
しはPSGやBSG等が有効である。PSGやBSGは
Si半導体デバイスのパッシベーションやデバイス面の
平坦化に従来より使われてきており、Si半導体デバイ
スへの良い効果(Naのゲッタリング等)はあっても悪
影響は殆どない。
If a glass-like material is used as the thermoplastic material for the adhesive, the stress applied to the flat plate when solidified will be relatively small. In particular, when the flat plate is a Si wafer, PSG, BSG, etc. are effective as the thermoplastic material. PSG and BSG have been conventionally used for passivation of Si semiconductor devices and planarization of device surfaces, and although they have positive effects (such as gettering of Na) on Si semiconductor devices, they have almost no negative effects.

PSGやBSGは5tOz中にそれぞれP(りん)やB
(ボロン)をドープしたもので、これらPやBのドープ
量が増すと軟化温度が低下し融着が容易になる。
PSG and BSG each contain P (phosphorus) and B in 5tOz.
(boron) doped, and as the amount of P and B doped increases, the softening temperature decreases and fusion becomes easier.

例えば2枚のSiウェハを接着し、一方のウェハを研磨
やエツチングにより薄膜化し、その薄膜中にデバイスを
形成しようとする場合、デバイスと接着剤層とが近接す
るためデバイス特性への接着剤の影響が顕著になる。溶
剤を含む高分子系°接着剤を用いた場合には残留してい
る溶剤や高分子材料がデバイス特性に悪影響を及ぼすお
それがあり、また固化がスムーズに起らないため応力の
影響も無視できなかったものである。これに反して、P
SGやBSGを用いた場合は上述のようにSi半導体デ
バイスでの十分な使用実績があり悪影響は殆どない。
For example, when two Si wafers are bonded together, one of the wafers is made into a thin film by polishing or etching, and a device is formed in the thin film, the device and the adhesive layer are in close proximity, which may affect the device characteristics. The impact becomes noticeable. When using polymeric adhesives that contain solvents, residual solvents and polymeric materials may have a negative effect on device characteristics, and the effects of stress cannot be ignored because solidification does not occur smoothly. It's something that didn't exist. On the contrary, P
When SG or BSG is used, as mentioned above, there is a sufficient track record of its use in Si semiconductor devices, and there is almost no adverse effect.

なお、低温での接着を行うには、BドープのPSGが有
利で、それを使えば800℃程度でも接着が可能である
Note that B-doped PSG is advantageous for bonding at low temperatures, and if it is used, bonding is possible even at about 800°C.

Si半導体デバイスに通用する場合、高温融着やデバイ
ス形成の過程でPSG中のP ’P BSG中のBがS
i中に拡散す葛おそれがあるので、PSGやBSG堆積
の前にSiウェハ表面に不純物拡散防止用のSiO+膜
を設けておくことが望ましい。
When applicable to Si semiconductor devices, P'P in PSG and B in BSG are converted to S during high-temperature fusion and device formation processes.
Since there is a risk of diffusion of impurities into the Si wafer, it is desirable to provide an SiO+ film for preventing impurity diffusion on the surface of the Si wafer before depositing PSG or BSG.

〔実施例〕〔Example〕

以下、図面を参照して本発明の実施例を詳細に説明する
Embodiments of the present invention will be described in detail below with reference to the drawings.

平板としては約5 cm (2インチ) Siウェハ1
1゜21を用い、Siウェハ11.21の表面に不純物
拡散防止物質層として常圧CVDで厚さ0.5μlの5
i02膜12.22を堆積させ、さらにその上に同じく
常圧CVDでPSG膜13.23を2.5μmの厚さに
堆積させた。このようにして作成した接着用基板14.
24を2枚石英支持台15の上にPSGの層13.23
が相接するように重ねて置き、その上に円柱状石英ブロ
ック16をのせた状態で電気炉17へ入れ、加圧、加熱
による接着を行った。
Approximately 5 cm (2 inches) Si wafer 1 as a flat plate
Using 1°21, a 0.5 μl thick layer of 5 was deposited on the surface of the Si wafer 11.21 by atmospheric pressure CVD as an impurity diffusion prevention substance layer.
An i02 film 12.22 was deposited, and a PSG film 13.23 was further deposited thereon to a thickness of 2.5 μm by atmospheric pressure CVD. Adhesive substrate 14 created in this way.
24 on the quartz support 15 and a layer of PSG 13.23
The cylindrical quartz blocks 16 were placed on top of each other so as to be in contact with each other, and the cylindrical quartz blocks 16 were placed on top of the quartz blocks 16, which were placed in an electric furnace 17, and bonded by pressure and heat.

h0505濃4mo1%のPSGを用いた場合、上述の
円柱状石英ブロック16による26g/ cm2の加圧
および950℃の加熱で、2枚の接着用基板14.24
は完全に融着した。融着した接着用基板14.24を粉
砕し、詳細に開べたところ、未融着による基板剥離は見
られなかった。
When PSG with h0505 concentration of 4 mo1% is used, two adhesive substrates 14.24 are bonded by applying a pressure of 26 g/cm2 and heating at 950°C using the above-mentioned cylindrical quartz block 16.
was completely fused. When the fused adhesive substrates 14 and 24 were crushed and opened in detail, no peeling of the substrates due to unfused bonding was observed.

上述のpscの代りにBを入れたPSG (BL03濃
度:3moj!%、PL03濃度9mo1%)を用いて
上記と同じ実験を行ったところ、850℃で2枚の接着
用基板は14.24は完全に融着した。
When the same experiment as above was carried out using PSG (BL03 concentration: 3moj!%, PL03 concentration: 9mo1%) in which B was substituted for the above-mentioned psc, the temperature of two adhesive substrates at 850°C was 14.24%. Completely fused.

さらに、BSGについても上記と全く同じ実験を行い、
B103濃度11mo/%のBSGの場合、1000℃
で完全な基板接着が可能なことを確認した。
Furthermore, we conducted the same experiment as above for BSG,
In the case of BSG with a B103 concentration of 11 mo/%, 1000°C
It was confirmed that complete board adhesion was possible.

本実施例では、熱可塑性物質としてpscやBSG等を
用いた場合について紹介したが、これらに限定されるも
のではなく、この外にもGeを入れるとPSGの軟化点
が下がることが確認され、このGeを入れたPSGも接
着剤として十分通用可能である。
In this example, we have introduced the case where psc, BSG, etc. are used as the thermoplastic material, but it is not limited to these, and it has been confirmed that adding Ge to other materials lowers the softening point of PSG. This Ge-containing PSG can also be used as an adhesive.

また上述の実施例では不純物拡散防止物質として5i0
2を採用したが、これに限定されるものではなく、例え
ば5iJN1等も十分な不純物拡散防止の効果がある。
In addition, in the above embodiment, 5i0 is used as an impurity diffusion prevention substance.
2 was adopted, but it is not limited to this, and for example, 5iJN1 etc. can also have a sufficient effect of preventing impurity diffusion.

その他、熱可塑性物質の種類によって様々な不純物拡散
防止物質が使用可能である。
In addition, various impurity diffusion prevention substances can be used depending on the type of thermoplastic material.

さらに、熱′可塑性物質としては、B 、 Ge、 A
s。
Furthermore, as thermoplastic substances, B, Ge, A
s.

AN 、 Na、 K 、 Mg、 Ca、 Pb+ 
Mn、 W、 Tit Zr、 Hf。
AN, Na, K, Mg, Ca, Pb+
Mn, W, Tit Zr, Hf.

Ta、 Cr、 NAl、 Nbのうち1つまたは複数
の元素を成分とするガラスを用いうろこと、また、ガラ
スとしては、PSG、 BSGの他にシリカガラス(S
iOz )も使用可能であることが確認された。さらに
、この融着を真空中で行うと、気泡の混入がないため、
ストレス等によるクランク発生が全くなく、より強固な
接着が可能であることが確認された。
Scales are made of glass containing one or more elements of Ta, Cr, NAl, and Nb, and in addition to PSG and BSG, silica glass (S
It was confirmed that 1Oz) can also be used. Furthermore, if this fusion is performed in a vacuum, there will be no air bubbles, so
It was confirmed that there was no occurrence of cranking due to stress, etc., and that stronger adhesion was possible.

上記した接着方法は第2図と第3図を参照して説明した
SOI変型例において有効で、その場合Siウェハは薄
膜化するのであるが、その場合でもストレス等による単
結晶シリコン層のクランク等が防止されることが確かめ
られた。
The above bonding method is effective in the SOI modification example explained with reference to FIGS. 2 and 3, and in that case the Si wafer is thinned, but even in that case, the single crystal silicon layer may be cracked due to stress etc. It was confirmed that this was prevented.

〔発明の効果〕〔Effect of the invention〕

以上述べてきたように本発明によれば、Siウェハの如
き平板2枚を均一かつ強固に接着することが可能となり
、それは例えばSOIの変型例において半導体装置の製
造歩留りを向上し、製造されるデバイスの信頼性を高め
るに有効である。なお、本発明の方法においては固相←
軟化状態←液相と幅広くその状態が変化する熱可塑性材
料を用いるので、加熱の条件が厳格である必要がな(、
上記に示した如き電気炉の内で加熱する簡単な方法をと
りうる利点がある。
As described above, according to the present invention, it is possible to bond two flat plates such as Si wafers uniformly and firmly, which improves the manufacturing yield of semiconductor devices in, for example, modified SOI. Effective in increasing device reliability. In addition, in the method of the present invention, the solid phase←
Since we use a thermoplastic material whose state changes widely from softened state to liquid phase, there is no need for strict heating conditions.
There is an advantage that a simple method of heating in an electric furnace as shown above can be used.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明実施例の断面図、 第2図と第3図はsorの変型例を示す断面図である。 第1図において、 11、21はSiウェハ、 12、 22は 5i02 M臭、 13、23はpsc層、 14、24は接着用基板、 15は石英支持台、 16は石英ブロックである。 本歴明1働例前面囚 第1図 Sol変型例の#面図 第2図 So1文型例O挿図 第3図 FIG. 1 is a sectional view of an embodiment of the present invention. FIGS. 2 and 3 are cross-sectional views showing modified examples of the sor. In Figure 1, 11 and 21 are Si wafers, 12, 22 is 5i02 M smell, 13 and 23 are psc layers, 14 and 24 are adhesive substrates; 15 is a quartz support stand; 16 is a quartz block. Book record 1 work case front prisoner Figure 1 # view of Sol variant Figure 2 So1 sentence pattern example O illustration Figure 3

Claims (9)

【特許請求の範囲】[Claims] (1)1対の平板(11、21)の表面に熱可塑性物質
の層(13、23)を形成し、 熱可塑性物質層(13、23)が相接する如く1対の平
板(11、21)を重ね合せて加圧および加熱を施して
1対の平板(11、21)を融着させることを特徴とす
る平板接着方法。
(1) A thermoplastic layer (13, 23) is formed on the surface of a pair of flat plates (11, 21), and the pair of flat plates (11, 21) A flat plate bonding method characterized in that the pair of flat plates (11, 21) are fused together by stacking them and applying pressure and heat.
(2)前記熱可塑性物質が燐・シリケート・ガラスであ
ることを特徴とする特許請求の範囲第1項記載の方法。
(2) The method according to claim 1, wherein the thermoplastic material is phosphorus-silicate glass.
(3)前記熱可塑性物質がシリカガラス(SiO_2)
であることを特徴とする特許請求の範囲第1項記載の方
法。
(3) The thermoplastic substance is silica glass (SiO_2)
The method according to claim 1, characterized in that:
(4)前記熱可塑性物質が、B、Ge、As、Al、N
a、に、Mg、Ca、Mn、W、Ti、Zr、Hf、T
a、Cr、Ni、Nbのうちの1つまたは複数の元素を
成分とするガラスであることを特徴とする特許請求の範
囲第1項記載の方法。
(4) The thermoplastic substance is B, Ge, As, Al, N
a, Mg, Ca, Mn, W, Ti, Zr, Hf, T
2. The method according to claim 1, wherein the glass is a glass containing one or more of the following elements: a, Cr, Ni, and Nb.
(5)前記平板(11、21)が半導体基板であり、該
基板と前記熱可塑性物質の層(13、23)との間に不
純物拡散防止物質層(12、22)を設けることを特徴
とする特許請求の範囲第1項記載の方法。
(5) The flat plate (11, 21) is a semiconductor substrate, and an impurity diffusion prevention material layer (12, 22) is provided between the substrate and the thermoplastic material layer (13, 23). A method according to claim 1.
(6)前記不純物拡散防止物質がSiO_2であること
を特徴とする特許請求の範囲第1項記載の方法。
(6) The method according to claim 1, wherein the impurity diffusion preventing substance is SiO_2.
(7)前記不純物拡散防止物質がSi_3N_4である
ことを特徴とする特許請求の範囲第1項記載の方法。
(7) The method according to claim 1, wherein the impurity diffusion preventing substance is Si_3N_4.
(8)接着した半導体基板を薄層化することを特徴とす
る特許請求の範囲第1項記載の方法。
(8) The method according to claim 1, characterized in that the bonded semiconductor substrate is thinned.
(9)前記接着が減圧状態で行われることを特徴とする
特許請求の範囲第1項記載の方法。
(9) The method according to claim 1, wherein the bonding is performed under reduced pressure.
JP26030485A 1985-11-20 1985-11-20 Bonding method for flat plate Pending JPS62120044A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26030485A JPS62120044A (en) 1985-11-20 1985-11-20 Bonding method for flat plate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26030485A JPS62120044A (en) 1985-11-20 1985-11-20 Bonding method for flat plate

Publications (1)

Publication Number Publication Date
JPS62120044A true JPS62120044A (en) 1987-06-01

Family

ID=17346170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26030485A Pending JPS62120044A (en) 1985-11-20 1985-11-20 Bonding method for flat plate

Country Status (1)

Country Link
JP (1) JPS62120044A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018137431A (en) * 2017-01-24 2018-08-30 エックス−ファブ・セミコンダクター・ファウンダリーズ・アーゲー Semiconductor substrate and method for producing semiconductor substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018137431A (en) * 2017-01-24 2018-08-30 エックス−ファブ・セミコンダクター・ファウンダリーズ・アーゲー Semiconductor substrate and method for producing semiconductor substrate

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