JPS62119914A - Method for solid-phase epitaxy of semiconductor layer - Google Patents

Method for solid-phase epitaxy of semiconductor layer

Info

Publication number
JPS62119914A
JPS62119914A JP25862585A JP25862585A JPS62119914A JP S62119914 A JPS62119914 A JP S62119914A JP 25862585 A JP25862585 A JP 25862585A JP 25862585 A JP25862585 A JP 25862585A JP S62119914 A JPS62119914 A JP S62119914A
Authority
JP
Japan
Prior art keywords
layer
recess
semiconductor
semiconductor layer
single crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25862585A
Other languages
Japanese (ja)
Inventor
Michio Negishi
根岸 三千雄
Hisao Hayashi
久雄 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP25862585A priority Critical patent/JPS62119914A/en
Publication of JPS62119914A publication Critical patent/JPS62119914A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To make it possible to form the crystal silicon layer of single crystal face easily by forming a semiconductor layer on an insulating substrate having a recess and filling the recess with the semiconductor layer, followed by heat treatment to form semiconductor grains having a single crystal face on its upper plane, and then growing the semiconductor layer by solid phase while using the semiconductor grains as seeds. CONSTITUTION:A polysilicon layer 3 is formed on an insulating substrate 1 having a recess 2. The Si layer 3 fills the recess 2. A diameter r of the recess 2 is determined in consideration of the grain size of the layer 3 and the grain size after annealing. For example, if the grain size is 500Angstrom on an average, the diameter r is determined to be about 0.6-0.8mum. Next, the grain size is enlarged by annealing (I). After forming semiconductor grains 4 having a single crystal face in the recess 2, the polysilicon layer 3 is made amorphous by ion implantation (II). The depth x in the substrate to be made amorphous is deeper than the thickness d of the layer 3 and is shallower than the sum of d and the depth h of the recess 2. A layer 5 is grown by solid phase to become a semi-crystal Si layer by using the semiconductor grains 4 as seeds.

Description

【発明の詳細な説明】 【産業上の利用分野〕     ′ 本発明は、絶縁基板上に単結晶シリコン層を成長させる
SOI  (シリコン・オン・インシュレーター)技術
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] ' The present invention relates to SOI (silicon-on-insulator) technology for growing a single crystal silicon layer on an insulating substrate.

〔発明の概要〕[Summary of the invention]

本発明は、絶縁基板上に半導体層を形成しイオン注入法
を用いて該半導体層を非晶質化させてからアニールによ
り再結晶化を図る半導体層の固相成長方法において、凹
部を設けて該凹部内に単一結晶面を上面に有する半導体
粒を形成することにより、単結晶シリコン層を絶縁基板
上に固相成長させるものである。
The present invention provides a solid phase growth method for a semiconductor layer in which a semiconductor layer is formed on an insulating substrate, the semiconductor layer is made amorphous using an ion implantation method, and then recrystallized by annealing. A single crystal silicon layer is grown in a solid phase on an insulating substrate by forming semiconductor grains having a single crystal plane on the upper surface within the recess.

〔従来の技術〕[Conventional technology]

一般に、絶縁基板或いは絶縁層上に形成された単結晶シ
リコン層に、トランジスタ等の半導体素子を形成するS
ol構造が半導体装置の3次元化、高集積化において注
目されている。
Generally, S is used to form semiconductor elements such as transistors on a single crystal silicon layer formed on an insulating substrate or an insulating layer.
The OL structure is attracting attention in the development of three-dimensional and highly integrated semiconductor devices.

ところで、上記Sol構造を形成するに用いる半導体層
の固相成長方法として、延在部を用いて、その部分から
の固相成長による半導体層の固相成長方法が知られてい
る。
By the way, as a solid-phase growth method of a semiconductor layer used to form the above-mentioned Sol structure, a method of solid-phase growth of a semiconductor layer by using an extension part and performing solid-phase growth from that part is known.

このような半導体層の固相成長方法の一例として、例え
ば、第2図に示すような平面パターン21を用いた方法
が有る。
An example of such a solid-phase growth method for a semiconductor layer is a method using a planar pattern 21 as shown in FIG. 2, for example.

即ち、先ず、結晶化領域22及び該結晶化領域22と隣
接し且つ延在されてなる延在部23からなる平面パター
ン21の形状に、多結晶シリコン層を絶縁基板上に所定
の膜厚で被着形成する。そして、上記延在部23に形成
された多結晶シリコン層24のみをレジスト等により被
覆し、この延在部23の多結晶シリコンJW24を除く
上記結晶化領域22の多結晶シリコン層をシリコンイオ
ン等をドーパントとするイオン注入により非晶質化させ
る6次に、この非晶質化した結晶化領域22の多結晶シ
リコン層を熱処理によって面相成長させる。このとき、
固相成長は、上記延在部23の多結晶シリコン層24を
種として行われ、その固相成長が結晶化領域22で絶縁
基板の主面に沿った横方向に進行することになる。
That is, first, a polycrystalline silicon layer is deposited on an insulating substrate at a predetermined thickness in the shape of a plane pattern 21 consisting of a crystallized region 22 and an extended portion 23 adjacent to and extended from the crystallized region 22. Adhesion is formed. Then, only the polycrystalline silicon layer 24 formed in the extending portion 23 is covered with a resist or the like, and the polycrystalline silicon layer in the crystallized region 22 except for the polycrystalline silicon JW 24 in the extending portion 23 is covered with silicon ions or the like. Next, the amorphous polycrystalline silicon layer in the crystallized region 22 is subjected to planar phase growth by heat treatment. At this time,
The solid phase growth is performed using the polycrystalline silicon layer 24 of the extension portion 23 as a seed, and the solid phase growth proceeds in the crystallized region 22 in the lateral direction along the main surface of the insulating substrate.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

然しなから、このような方法により固相成長させた場合
には、上記延在部23からの多結晶シリコン層24を種
とする為、種々の結晶面を有する層が再結晶層として形
成されることになる。
However, when solid phase growth is performed by such a method, since the polycrystalline silicon layer 24 from the extension portion 23 is used as a seed, layers having various crystal planes are formed as a recrystallized layer. That will happen.

即ち、上記延在部23は、イオン注入の際に被覆されて
おり、多結晶シリコン層24はそのまま多結晶半導体層
となっている。そして、上記結晶化領域22の多結晶シ
リコン層の非晶質化の後、同相成長法により再結晶化さ
せたときは、上記多結晶シリコン層24を結晶種とする
為、種々の結晶面を有する再結晶層が形成されることに
なる。
That is, the extending portion 23 is covered during ion implantation, and the polycrystalline silicon layer 24 remains as a polycrystalline semiconductor layer. When the polycrystalline silicon layer in the crystallized region 22 is made amorphous and then recrystallized by the in-phase growth method, various crystal planes are formed in order to use the polycrystalline silicon layer 24 as a crystal seed. A recrystallized layer will be formed.

このように種々の結晶面を有するような再結晶層が形成
された場合には、このような再結晶化層を用いて素子を
形成しても、そのグレインの境界において、素子の性能
を劣化させるような現象が生ずることになる。
If a recrystallized layer with various crystal planes is formed in this way, even if an element is formed using such a recrystallized layer, the performance of the element will deteriorate at the boundaries of the grains. This will cause a phenomenon to occur.

そこで、本発明は上述の問題点に鑑み、半導体層の単結
晶化を実現し得る半導体層の固相成長方法の提供を目的
とする。
SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a method for solid-phase growth of a semiconductor layer that can realize single crystallization of a semiconductor layer.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、凹部を有する絶縁基板の表面に半導体層を形
成すると共に上記凹部を該半導体層で充填した後、熱処
理を行って、上記凹部内に単一結晶面を上面に有する半
導体粒を形成し、該半導体粒を種として上記半導体層を
固相成長させる半導体層の固相成長方法により上述の問
題点を解決する。
The present invention forms a semiconductor layer on the surface of an insulating substrate having a recess, fills the recess with the semiconductor layer, and then performs heat treatment to form semiconductor grains having a single crystal plane on the upper surface within the recess. However, the above-mentioned problems are solved by a method of solid phase growth of a semiconductor layer, in which the semiconductor layer is grown in a solid phase using the semiconductor grains as seeds.

尚、本発明において絶縁基板とは、基板上に絶縁層を形
成したものを含むものとする。
Note that in the present invention, the insulating substrate includes a substrate on which an insulating layer is formed.

〔作用〕[Effect]

凹部を有する絶縁基板を使用し、この絶縁基板の凹部に
単一の結晶面を上面に有する半導体粒を形成し、この半
導体粒を種とする固相成長によって半導体層の単結晶化
の実現を図る。このとき上記凹部には、単一の結晶面が
臨むことなり、半導体粒からの固相成長は、当該半導体
粒の結晶面を反映した固相成長となる。
An insulating substrate with recesses is used, semiconductor grains with a single crystal plane on the upper surface are formed in the recesses of the insulating substrate, and the semiconductor layer is made into a single crystal by solid phase growth using these semiconductor grains as seeds. Plan. At this time, a single crystal plane faces the recess, and the solid phase growth from the semiconductor grain becomes solid phase growth that reflects the crystal plane of the semiconductor grain.

〔実施例〕〔Example〕

本発明の好適な実施例を図面を参照しながら説明する。 Preferred embodiments of the present invention will be described with reference to the drawings.

本実施例は、絶縁基板の凹部に単一の結晶面を上面に有
する半導体粒を形成し、この半導体粒を種とする固相成
長によって半導体層の単結晶化を実現する半導体層の固
相成長方法である。以下、本実施・例を工程順に説明す
る。尚、小文字の英字の見出しは、第1図の分画記号に
対応する。
In this example, semiconductor grains having a single crystal plane on the upper surface are formed in a recessed part of an insulating substrate, and the solid phase of the semiconductor layer is realized by solid phase growth using the semiconductor grains as a seed to achieve single crystallization of the semiconductor layer. It's a way of growing. Hereinafter, this embodiment/example will be explained in order of steps. Note that the lowercase alphabetic headings correspond to the division symbols in FIG.

(a)先ず、第1図aに示すように、凹部2を有する絶
縁基板lに、半導体層として多結晶シリコン層3を形成
する。この多結晶シリコン層3は、上記絶縁基板1の凹
部に充填される。
(a) First, as shown in FIG. 1a, a polycrystalline silicon layer 3 is formed as a semiconductor layer on an insulating substrate l having a recess 2. This polycrystalline silicon layer 3 fills the recessed portion of the insulating substrate 1.

ここで、上記凹部2は、絶縁基板lの表面がら深さhに
、当該口゛部2の径を径rの大きさに形成されている。
Here, the recess 2 is formed at a depth h from the surface of the insulating substrate l, and the diameter of the mouth portion 2 is r.

上記凹部2の径rは、被着する多結晶シリコン層3のグ
レインサイズ及び後述するア   ゛ニール処理後のグ
レインサイズを考慮して定めることができ、例えば、グ
レインサイズの平均を500人とした場合には、0.6
〜0.8μm程凌0値に径rの大きさを設定することが
できる。
The diameter r of the recess 2 can be determined by considering the grain size of the deposited polycrystalline silicon layer 3 and the grain size after the annealing treatment described below. For example, if the average grain size is 500, In this case, 0.6
The size of the radius r can be set to a value of about 0.8 μm.

上記多結晶シリコン層3は、例えばcVD法等により膜
厚dに被着形成され、上記凹部2に充填される。
The polycrystalline silicon layer 3 is deposited to a thickness d by, for example, the cVD method, and is filled in the recess 2.

(b)凹部2を有する絶縁基板1に多結晶シリコン層3
を形成して、上記凹部2に多結晶シリコンを充填した後
、第1図すに示すように、アニール処理を施してグレイ
ンサイズを大きくする。アニールは例えば600℃程度
の熱処理で良い。多結晶シリコン層3のグレインは、こ
のアニールによってその大きさが平均500人から平均
1μm程度まで成長することになる。
(b) A polycrystalline silicon layer 3 on an insulating substrate 1 having a recess 2
After forming polycrystalline silicon and filling the recess 2 with polycrystalline silicon, an annealing treatment is performed to increase the grain size, as shown in FIG. Annealing may be performed by heat treatment at about 600° C., for example. Through this annealing, the grains of the polycrystalline silicon layer 3 grow from an average size of 500 to about 1 μm.

上記凹部2内に充填された多結晶シリコン層3のグレイ
ンも同様にアニールによって、そのグレインサイズが大
きくなる。即ち、ある一つの半導体粒4は、アニールに
よるグレイン成長によってそのグレインサイズが上記凹
部2の径rより大きくなり、上記凹部2内を単一結晶面
を上面に有するようにふさぐことになる。
Similarly, the grain size of the polycrystalline silicon layer 3 filled in the recess 2 is increased by annealing. That is, one semiconductor grain 4 has a grain size larger than the diameter r of the recess 2 due to grain growth by annealing, and fills the inside of the recess 2 so that the single crystal plane is on the upper surface.

(c)上記凹部2内に単一結晶面を上面に有する半導体
粒4を形成した後、第1図Cに示すように多結晶シリコ
ン層3に対してイオン注入を施してこれを非晶質化させ
る。このイオン注入は、例えばシリコンイオンをドーパ
ントとし、上記多結晶シリコン1!i3の全面に施され
る。このイオン注入の投影飛程Rpにより定まる非晶質
化の深さXは、上記多結晶シリコン層3の膜厚dより深
く、且つ上記膜厚dと上記凹部の深さhの和より浅い値
であって上記半導体粒4の結晶性が維持される深さであ
る。このようなイオン注入によって多結晶シリコン層3
を非晶質化することによって、単結晶・シリコン層を成
長させることが可能となる。
(c) After forming semiconductor grains 4 having a single crystal plane on the upper surface in the recess 2, ions are implanted into the polycrystalline silicon layer 3 to transform it into an amorphous layer, as shown in FIG. 1C. to become This ion implantation uses, for example, silicon ions as a dopant, and the polycrystalline silicon 1! It is applied to the entire surface of i3. The amorphous depth X determined by the projected range Rp of this ion implantation is a value deeper than the film thickness d of the polycrystalline silicon layer 3 and shallower than the sum of the film thickness d and the depth h of the recess. This is the depth at which the crystallinity of the semiconductor grains 4 is maintained. By such ion implantation, the polycrystalline silicon layer 3
By making it amorphous, it becomes possible to grow a single crystal silicon layer.

(d)多結晶シリコン層3の非晶質化の後、第1図dに
示すように、上記半導体粒4を種として上記非晶質化さ
れた半導体115を固相成長させ、単結晶シリコン層に
する。尚、この第1図dにおいて、矢印は固相成長の方
向を示している。固相成長は、所定の温度9時間の条件
で行うことができ、また、これに限定されず、条件を適
当に選択することにより、所望の大きさの領域に単結晶
シリコン層を成長形成することができる。
(d) After the polycrystalline silicon layer 3 is made amorphous, as shown in FIG. Layer. In FIG. 1d, the arrow indicates the direction of solid phase growth. Solid-phase growth can be performed at a predetermined temperature for 9 hours, and is not limited to this. By appropriately selecting the conditions, a single crystal silicon layer can be grown in a region of a desired size. be able to.

以上の工程を経て、本実施例の半導体層の固相成長方法
を実施することが可能である。そして、本実施例の半導
体層の固相成長方法を用いることにより、従来の固相成
長方法では、種々の結晶面を有する半導体層が成長によ
って形成されていたが、本実施例では、単一結晶面を上
面に有する半導体粒4からの固相成長によるため、当該
半導休校4の結晶を反映した固相成長ができ、単結晶シ
リコン層を容易に形成し得る。
Through the above steps, it is possible to implement the solid phase growth method of a semiconductor layer of this example. By using the solid-phase growth method of the semiconductor layer of this embodiment, semiconductor layers having various crystal planes are formed by growth in the conventional solid-phase growth method, but in this embodiment, a single crystal plane is formed. Since solid phase growth is performed from semiconductor grains 4 having a crystal plane on the upper surface, solid phase growth that reflects the crystal of the semiconductor particles 4 can be performed, and a single crystal silicon layer can be easily formed.

尚、半導体層を本実施例において、多結晶シリコン層と
したが、これに限定されず、他の材料の半導体層でも良
い。
Although the semiconductor layer is a polycrystalline silicon layer in this embodiment, it is not limited thereto, and a semiconductor layer made of other materials may be used.

〔発明の効果〕〔Effect of the invention〕

本発明の半導体層の固相成長方法は、凹部内の単一結晶
面を上面に有する半導体粒を形成し、この半導体粒から
の固相成長を行うため、結晶面の単一な単結晶シリコン
層を容易に形成し得る。
In the solid phase growth method of a semiconductor layer of the present invention, semiconductor grains having a single crystal plane on the upper surface within a recess are formed, and solid phase growth is performed from this semiconductor grain. Layers can be easily formed.

【図面の簡単な説明】 第1図a〜第1図dは本発明の半導体層の固相成長方法
を工程順に説明する為の断面図、第2図は従来の半導体
層の固相成長方法を説明する為の平面図である。 特 許 出゛願 人  ソニー株式会社代理人   弁
理士     小池 見間         田村榮− 第1図a ム 第1図す 第1図C 第1図d 第2図
[Brief Description of the Drawings] Figures 1a to 1d are cross-sectional views for explaining the solid phase growth method of a semiconductor layer according to the present invention step by step, and Figure 2 is a conventional solid phase growth method of a semiconductor layer. FIG. Patent applicant Sony Corporation agent Patent attorney Koike Mima Ei Tamura - Figure 1a Figure 1C Figure 1d Figure 2

Claims (1)

【特許請求の範囲】[Claims] 凹部を有する絶縁基板の表面に半導体層を形成すると共
に上記凹部を該半導体層で充填した後、熱処理を行って
、上記凹部内に単一結晶面を上面に有する半導体粒を形
成し、該半導体粒を種として上記半導体層を固相成長さ
せる半導体層の固相成長方法。
After forming a semiconductor layer on the surface of an insulating substrate having a recess and filling the recess with the semiconductor layer, heat treatment is performed to form semiconductor grains having a single crystal plane on the upper surface in the recess, and the semiconductor layer is filled with the semiconductor layer. A method for solid-phase growth of a semiconductor layer, in which the semiconductor layer is grown in a solid-phase using grains as seeds.
JP25862585A 1985-11-20 1985-11-20 Method for solid-phase epitaxy of semiconductor layer Pending JPS62119914A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25862585A JPS62119914A (en) 1985-11-20 1985-11-20 Method for solid-phase epitaxy of semiconductor layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25862585A JPS62119914A (en) 1985-11-20 1985-11-20 Method for solid-phase epitaxy of semiconductor layer

Publications (1)

Publication Number Publication Date
JPS62119914A true JPS62119914A (en) 1987-06-01

Family

ID=17322873

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25862585A Pending JPS62119914A (en) 1985-11-20 1985-11-20 Method for solid-phase epitaxy of semiconductor layer

Country Status (1)

Country Link
JP (1) JPS62119914A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01276615A (en) * 1988-04-27 1989-11-07 Seiko Epson Corp Manufacture of semiconductor device
US5236544A (en) * 1989-06-26 1993-08-17 Canon Kabushiki Kaisha Process for growing crystal
US5457058A (en) * 1989-10-09 1995-10-10 Canon Kabushiki Kaisha Crystal growth method
JP2004134533A (en) * 2002-10-09 2004-04-30 Seiko Epson Corp Method for fabricating semiconductor device, semiconductor device, electro-optical device, and electronic apparatus
US6911359B2 (en) 2001-12-28 2005-06-28 Seiko Epson Corporation Method for manufacturing a semiconductor device, semiconductor device, display device, and electronic device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01276615A (en) * 1988-04-27 1989-11-07 Seiko Epson Corp Manufacture of semiconductor device
US5236544A (en) * 1989-06-26 1993-08-17 Canon Kabushiki Kaisha Process for growing crystal
US5457058A (en) * 1989-10-09 1995-10-10 Canon Kabushiki Kaisha Crystal growth method
US6911359B2 (en) 2001-12-28 2005-06-28 Seiko Epson Corporation Method for manufacturing a semiconductor device, semiconductor device, display device, and electronic device
JP2004134533A (en) * 2002-10-09 2004-04-30 Seiko Epson Corp Method for fabricating semiconductor device, semiconductor device, electro-optical device, and electronic apparatus

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