577137 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內容、實 施方式及圖式簡單說明） 本發明是有關於一種增加矽電極表面積的方法，且特 別是有關於一種儲存電極的製造方法。 一般電容器的結構，包括兩個電極及兩個電極之間的 介電層。爲了提高電容器的電容値，必須減少電極間介電 層的厚度，或者增加電極的表面積。其中，一種增加電極 表面積的方法係以表面具有選擇性半球形矽晶粒（Selective Hemispherical Grain ; Selective-HSG)之複晶石夕（Polysilicon) 層，作爲電容器之儲存電極。由於選擇性半球形矽晶粒具 有凹凸不平的特徵，可增加儲存電極的表面積以提高電容 値。然而，選擇性半球形矽晶粒在複晶矽層的表面上不易 形成，須以先在非晶矽（Amorphous Silicon ; a-Si)層的 表面上形成選擇性半球形矽晶粒層，再進行回火使非晶矽 層轉爲複晶矽層的方式才能完成。 第1A圖至第1E圖繪示習知一種儲存電極的製造流程 剖面圖。首先，請參照第1A圖，提供一矽基底100，矽 基底100上已形成有介電層1〇2，其中介電層102具有開 口 104暴露出矽基底100。 接著，請參照第1B圖，於矽基底1〇〇上形成非晶矽 層106，並塡滿開口 104。其中，非晶矽層106的厚度約 爲8000A，其材質例如爲摻雜的非晶矽，而摻質則例如爲 砷或磷，用以增加非晶矽層1〇6的導電性。典型形成非晶 03764tw0.doc/006 5 577137 矽層106的方法例如以化學氣相沈積法於基底100上沈積 複晶矽層106，並同時完成複晶矽層106摻質的植入’其 摻質濃度約爲1015 1/cm3。然而，上述形成非晶矽層106 的方法費時甚久’約爲12至16小時左右。 其後，請參照第1C圖’定義介電層102上的非晶矽 層106，使留下的非晶矽層106a對應在開口 104的上方， 其寬度約大於開口 104的寬度。 然後，請參照第1〇圖，於众電層1〇2上的非晶矽層106a 外圍形成選擇性半球狀矽晶粒層11〇，以增加後續完成的 儲存電極之表面積。 最後，請參照第1E圖，進行一全面性回火步驟，使 非晶矽層l〇6a轉爲複晶矽層106b，而與選擇性半球狀矽 晶粒層110共同組成一儲存電極112。然而，此儲存電極 112與基底100之間因爲氧化薄層（未繪示出）的存在，其 介面阻抗頗高，易影響電性導通的品質。 習知另一種儲存電極的製造方法，係以複晶矽層爲儲 存電極製作的起始物。首先，以離子植入法非晶化複晶矽 層的表層，再於此已非晶化的表層上形成選擇性半球形晶 粒層。此法可避免費時形成非晶矽層，因爲複晶矽形成速 率較非晶矽爲快了許多，而且複晶矽層可以破壞儲存電極 與基底間的薄氧化層，以改善電性導通的品質。然而，離 子植入法常難以使複晶矽層的表層具有較高濃度分佈的離 子，因此複晶矽層的表層非晶化的效果也就不盡理想，此 外，由於在形成選擇性半球形晶粒層的過程中，非晶矽層 03764twfi.doc/006 6 577137 會逐漸結晶化而形成複晶矽層’致使選擇性半球形晶粒層 無法形成。因此在製程上，若以非晶矽層製造儲存電極， 則會有製程時間冗長，儲存電極電性導通品質不佳等問 題，而若以複晶矽層製造儲存電極，會有非晶矽層再結晶 化等問題，亟待改進。 緣此，本發明的目的就是在提供一種形成半球形砂晶 粒層的方法，可以使複晶矽層的表層具有較高濃度分佈的 離子，以加強表層非晶化的效果，使後續的選擇性半球形 晶粒層能順利形成。 根據本發明上述及其他目的，提出一種儲存電極的製 造方法，此方法之簡述如下：首先，於提供的基底結構上 形成複晶矽層。接著，去除部份的複晶矽層，使留下的梯 形複晶矽層含有兩個側壁，其中兩個側壁之外表面與基底 結構之介電層表面的交角大於90°。然後，於梯形複晶矽 層的表層上形成緩衝層，此緩衝層的成分係可提供加長已 非晶化的表層再結晶化所需之時間的元素，且此緩衝層可 使後續離子植入以非晶化複晶矽層的步驟中，得以使用較 高之離子植入能量，以使離子植入於較深之梯形複晶矽層 表層，並使較高濃度分佈的離子更接近梯形複晶矽層的表 面，進而提昇梯形複晶矽層的表層非晶化的品質。在完成 梯形複晶矽層的表層的非晶化之後，將緩衝層移除。最後， 於梯形複晶矽層的表層上形成半球形矽晶粒層。 爲讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施例，並配合所附圖式，作詳細說明如 03764twfi.doc/006 7 577137 下： 圖式之簡單說明： 第1A圖至第1E圖爲習知一種儲存電極的製造流程剖 面圖的剖面圖；以及 第2A圖至第2F圖繪示依照本發明一較佳實施例的一 種形成半球形矽晶粒層的流程剖面圖。 圖式標記說明= 100 :矽基底 102、202 :介電層 104、204 :開口 106、106a :非晶砂層 106b、206、206a :複晶矽層 110 :選擇性半球形矽晶粒層 112、220 :儲存電極 200 :基底 207 ··表層 208 :緩衝層 209 :離子植入步驟 210 :半球形砂晶粒層 212 :基底結構 214 :側壁 216 :外表面 218 :交角 實施例 03764twf3.doc/006 8 577137 請參照第2A圖至第2F圖，其繪示依照本發明一較佳 實施例的一種形成半球形矽晶粒層的流程剖面圖。 首先，請參照第2A圖，形成基底結構212。提供材質 例如爲矽的基底200，並於基底200上形成具有開口 204 的介電層202，以完成基底結構212之製作，其中開口 204 暴露出基底200。 接著，請參照第2B圖，於基底200上形成複晶矽層 206,並塡滿開口 2〇4。其中，複晶矽層206的厚度約8000A 左右，其材質例如爲摻雑的複晶矽，而此摻雜的摻質例如 爲砷或磷，用以增加複晶矽層206的導電性。典型形成複 晶矽層206的方法例如在以化學氣相沈積法於基底200上 沈積複晶矽層206的同時，完成複晶矽層摻質的植入，此 植入的濃度約爲1〇15 Ι/cm3左右。特別注意的是，由於以 化學氣相沈積法形成厚度約8000A的複晶矽的速率較習知 形成厚度約8000A的非晶矽的速率快了許多，因此可節省 製程時間，提高工作產能。此外，在形成複晶矽層206之 時，複晶矽層206可破壞複晶矽層206與基底2〇〇之間的 氧化薄層（未繪示出），以降低複晶矽層206與基底200之 間的介面阻抗。 其後，請參照第2C圖，去除部份的複晶矽層206 ’使 留下的梯形複晶矽層206a含有兩個側壁214 ’其中兩個側 壁214之外表面216與基底結構212之介電餍202表面的 交角218大於90。，以利於在後續的製程中’以例如離子 植入法對側壁214的表層207進行非晶化。典型去除部份 9 03764twf3.doc/006 577137 的梯形複晶矽層206的方法’可以圖案化的梯形光阻層（未 繪示出）爲罩幕’進行梯形複晶矽層2〇6的非等向性蝕刻， 接著去除圖案化的梯形光阻層以執行之。 然後，請參照第2D圖，於梯形複晶矽層2〇6a的表層 207上形成緩衝層208。緩衝層208的成分包括具有可加 長已非晶化的表層207再結晶化所需之時間的元素，例如 爲氧或氮等，因此緩衝層208可例如爲氧化矽層或氮化矽 層等，其中氧化矽層的形成方法例如爲熱氧化法，而氮化 矽層的形成方法則例如爲化學氣相沈積法。上述之緩衝層 208的功能有二，其一在於此緩衝層208的成分具有可加 長已非晶化的表層207再結晶化所需之時間的元素，用以 提昇後續梯形複晶矽層206a的表層207非晶化的品質， 其二在於此厚度例如約爲100A〜500A左右的緩衝層208， 可使後續離子植入步驟209得以使用較高之離子植入能 量，以使較高濃度分佈的離子更接近梯形複晶矽層206a 的表面，進而加強梯形複晶矽層206a的表層207非晶化 的效果，其中緩衝層208的厚度係視離子植入步驟209的 植入能量而定。577137 发明 Description of the invention (The description of the invention should state: the technical field to which the invention belongs, the prior art, the content, the embodiments, and the drawings are simply explained) The present invention relates to a method for increasing the surface area of a silicon electrode, and more particularly to a method for increasing the surface area of a silicon electrode. Manufacturing method of storage electrode. The structure of a general capacitor includes two electrodes and a dielectric layer between the two electrodes. In order to increase the capacitance of the capacitor, it is necessary to reduce the thickness of the dielectric layer between the electrodes or increase the surface area of the electrodes. Among them, a method of increasing the surface area of the electrode is to use a polysilicon layer with a selective hemispherical grain (Selective-HSG) on the surface as a storage electrode of the capacitor. Because the selective hemispherical silicon grains are uneven, the surface area of the storage electrode can be increased to increase the capacitance 値. However, selective hemispherical silicon crystal grains are not easy to form on the surface of the polycrystalline silicon layer. The selective hemispherical silicon crystal grain layer must be formed on the surface of the amorphous silicon (a-Si) layer first, and then Tempering can be used to transform the amorphous silicon layer into a polycrystalline silicon layer. FIG. 1A to FIG. 1E are cross-sectional views showing a manufacturing process of a conventional storage electrode. First, referring to FIG. 1A, a silicon substrate 100 is provided. A dielectric layer 102 has been formed on the silicon substrate 100, and the dielectric layer 102 has an opening 104 to expose the silicon substrate 100. Next, referring to FIG. 1B, an amorphous silicon layer 106 is formed on the silicon substrate 100, and the opening 104 is filled. The thickness of the amorphous silicon layer 106 is about 8000 A. The material of the amorphous silicon layer 106 is, for example, doped amorphous silicon, and the dopant is, for example, arsenic or phosphorus, to increase the conductivity of the amorphous silicon layer 106. A typical method for forming the amorphous 03764tw0.doc / 006 5 577137 silicon layer 106 is to deposit the polycrystalline silicon layer 106 on the substrate 100 by chemical vapor deposition, and simultaneously complete the implantation of the doped silicon compound 106. The mass concentration is about 1015 1 / cm3. However, the above method for forming the amorphous silicon layer 106 takes a long time ', about 12 to 16 hours. Thereafter, please refer to FIG. 1C to define the amorphous silicon layer 106 on the dielectric layer 102, so that the remaining amorphous silicon layer 106a corresponds to the opening 104, and its width is greater than the width of the opening 104. Then, referring to FIG. 10, a selective hemispherical silicon grain layer 11 is formed on the periphery of the amorphous silicon layer 106a on the electric current layer 102 to increase the surface area of the storage electrode to be completed later. Finally, referring to FIG. 1E, a comprehensive tempering step is performed to transform the amorphous silicon layer 106a into a polycrystalline silicon layer 106b, and together with the selective hemispherical silicon grain layer 110, a storage electrode 112 is formed. However, due to the existence of a thin oxide layer (not shown) between the storage electrode 112 and the substrate 100, the interface impedance is relatively high, which easily affects the quality of electrical conduction. It is known that another method for manufacturing a storage electrode is to use a polycrystalline silicon layer as a starting material for the storage electrode. First, the surface layer of the polycrystalline silicon layer is amorphized by ion implantation, and then a selective hemispherical grain layer is formed on the amorphized surface layer. This method can avoid the time-consuming formation of amorphous silicon layer, because the formation rate of polycrystalline silicon is much faster than that of amorphous silicon, and the polycrystalline silicon layer can destroy the thin oxide layer between the storage electrode and the substrate to improve the quality of electrical conduction. . However, it is often difficult for the ion implantation method to make the surface layer of the polycrystalline silicon layer have a higher concentration distribution of ions. Therefore, the effect of amorphizing the surface layer of the polycrystalline silicon layer is not ideal. In addition, since a selective hemispherical is formed, During the grain layer process, the amorphous silicon layer 03764twfi.doc / 006 6 577137 will gradually crystallize to form a polycrystalline silicon layer, which prevents the formation of a selective hemispherical grain layer. Therefore, in the manufacturing process, if an amorphous silicon layer is used to fabricate a storage electrode, there will be problems such as long process time and poor electrical conductivity of the storage electrode. However, if a storage electrode is fabricated with a polycrystalline silicon layer, there will be an amorphous silicon layer. Problems such as recrystallization need urgent improvement. Therefore, the object of the present invention is to provide a method for forming a hemispherical sand grain layer, which can make the surface layer of the polycrystalline silicon layer have a higher concentration distribution of ions, so as to enhance the effect of surface amorphization and make subsequent selection. The semi-spherical grain layer can be formed smoothly. According to the above and other objects of the present invention, a method for manufacturing a storage electrode is proposed. The method is briefly described as follows. First, a polycrystalline silicon layer is formed on a provided base structure. Then, a part of the polycrystalline silicon layer is removed, so that the remaining ladder-shaped polycrystalline silicon layer contains two side walls, wherein the intersection angle between the outer surface of the two side walls and the surface of the dielectric layer of the base structure is greater than 90 °. Then, a buffer layer is formed on the surface layer of the trapezoidal polycrystalline silicon layer. The composition of the buffer layer can provide an element that prolongs the time required for the recrystallization of the amorphous surface layer, and the buffer layer can allow subsequent ion implantation. In the step of amorphizing the polycrystalline silicon layer, a higher ion implantation energy can be used, so that the ions are implanted on the deeper surface of the trapezoidal polycrystalline silicon layer, and the ions with a higher concentration distribution are closer to the trapezoidal complex. The surface of the crystalline silicon layer further improves the amorphization quality of the surface layer of the trapezoidal polycrystalline silicon layer. After the amorphization of the surface layer of the trapezoidal polycrystalline silicon layer is completed, the buffer layer is removed. Finally, a hemispherical silicon grain layer is formed on the surface of the trapezoidal polycrystalline silicon layer. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description, such as 37764twfi.doc / 006 7 577137: Brief description: FIG. 1A to FIG. 1E are cross-sectional views of a conventional cross-sectional view of a manufacturing process of a storage electrode; and FIGS. 2A to 2F illustrate a hemispherical silicon crystal formed according to a preferred embodiment of the present invention. Granular flow profile. Description of graphical symbols = 100: silicon substrates 102, 202: dielectric layers 104, 204: openings 106, 106a: amorphous sand layers 106b, 206, 206a: polycrystalline silicon layer 110: selective hemispherical silicon grain layer 112, 220: Storage electrode 200: Base 207 .. Surface layer 208: Buffer layer 209: Ion implantation step 210: Hemispherical sand grain layer 212: Base structure 214: Side wall 216: Outer surface 218: Cross angle. Example 37764twf3.doc / 006 8 577137 Please refer to FIGS. 2A to 2F, which are cross-sectional views of a process for forming a hemispherical silicon crystal layer according to a preferred embodiment of the present invention. First, referring to FIG. 2A, a base structure 212 is formed. A substrate 200 made of a material such as silicon is provided, and a dielectric layer 202 having an opening 204 is formed on the substrate 200 to complete the fabrication of the base structure 212, wherein the opening 204 exposes the substrate 200. Next, referring to FIG. 2B, a polycrystalline silicon layer 206 is formed on the substrate 200 and fills the opening 204. The thickness of the polycrystalline silicon layer 206 is about 8000 A. The material is, for example, erbium-doped polycrystalline silicon, and the doped dopant is, for example, arsenic or phosphorus, to increase the conductivity of the polycrystalline silicon layer 206. A typical method for forming the polycrystalline silicon layer 206 is, for example, by depositing the polycrystalline silicon layer dopant while depositing the polycrystalline silicon layer 206 on the substrate 200 by a chemical vapor deposition method. About 15 Ι / cm3. In particular, because the rate of forming polycrystalline silicon with a thickness of about 8000 A by chemical vapor deposition is much faster than the rate of conventionally forming amorphous silicon with a thickness of about 8000 A, it can save process time and increase working capacity. In addition, when the polycrystalline silicon layer 206 is formed, the polycrystalline silicon layer 206 can destroy the thin oxide layer (not shown) between the polycrystalline silicon layer 206 and the substrate 200 to reduce the polycrystalline silicon layer 206 and Interface impedance between the substrates 200. Thereafter, please refer to FIG. 2C, and remove a part of the polycrystalline silicon layer 206 'so that the trapezoidal polycrystalline silicon layer 206a has two side walls 214'. The outer surface 216 of the two side walls 214 and the base structure 212 are interposed. The intersection angle 218 of the surface of the electrode 202 is greater than 90. In order to facilitate the amorphization of the surface layer 207 of the sidewall 214 in a subsequent process, for example, by an ion implantation method. Typical method of removing part 9 03764twf3.doc / 006 577137 of trapezoidal compound silicon layer 206 'can be patterned trapezoidal photoresist layer (not shown) as a mask' to perform trapezoidal compound silicon layer 206 Isotropic etching is then performed to remove the patterned trapezoidal photoresist layer. Then, referring to FIG. 2D, a buffer layer 208 is formed on the surface layer 207 of the trapezoidal polycrystalline silicon layer 206a. The composition of the buffer layer 208 includes an element that can lengthen the time required for recrystallization of the surface layer 207 that has been amorphized, such as oxygen or nitrogen. Therefore, the buffer layer 208 may be a silicon oxide layer or a silicon nitride layer, for example. The method for forming the silicon oxide layer is, for example, a thermal oxidation method, and the method for forming the silicon nitride layer is, for example, a chemical vapor deposition method. The above-mentioned buffer layer 208 has two functions. One is that the composition of the buffer layer 208 has an element that can lengthen the time required for recrystallization of the surface layer 207 that has been amorphized, and is used to enhance the The quality of the surface layer 207 is amorphized, and the second is that the thickness of the buffer layer 208 is, for example, about 100A to 500A, which enables the subsequent ion implantation step 209 to use a higher ion implantation energy, so that a higher concentration distribution The ions are closer to the surface of the trapezoidal polycrystalline silicon layer 206a, thereby enhancing the effect of the amorphization of the surface layer 207 of the trapezoidal polycrystalline silicon layer 206a. The thickness of the buffer layer 208 depends on the implantation energy of the ion implantation step 209.
之後，請參照第2E圖，將梯形複晶矽層206a的表層 2〇7非晶化。例如以傾斜於基底結構212表面的方向，進 行梯形複晶矽層206a之表層207的離子植入步驟209，使 梯形複晶矽層206a的表層207非晶化。當由第2E圖左上 方進行傾斜離子植入步驟209時，將有利於非晶化梯形複 晶矽層206a左側側壁214的表層207，同理，當由第2E 03764twf3. doc/006 圖右上方進行傾斜離子植入步驟209時，將有利於非晶化 梯形複晶矽層206a右側側壁214的表層207。此外，在進 行離子植入步驟209時，部份緩衝層208的元素，例如氮 或氧等，將會被打進梯形複晶矽層206a的表層207，可以 加長已非晶化的表層207再結晶化所需的時間。更有甚者， 緩衝層208還可發揮緩衝的作用，使離子植入步驟209的 離子植入能量得以提高，例如以約lOOkeV〜200keV的植入 能量對複晶半導體層206a植入磷，或例如以約 120keV〜300keV的植入能量對複晶半導體層206a植入砷， 以使離子植入於較深之梯形複晶矽層206a表層207，並使 較高濃度分佈的離子更接近梯形複晶矽層206a的表面， 進而加強梯形複晶砂層206a的表層207非晶化的效果。 接著，請參照第2F圖，移除緩衝層208，並於梯形複 晶矽層206a的表層207上形成半球形矽晶粒層210，而與 梯形複晶砂層206a則共同構成一儲存電極220，其中移除 緩衝層208的方法例如爲蝕刻法。特別注意的是，雖然在 形成半球形矽晶粒層210的時候，已非晶化的梯形複晶矽 層206a會有再結晶化的現象，但本發明使用高能量的離 子植入步驟209，其植入的離子深度較深，可使梯形複晶 矽層206a中較深的部份也能被非晶化，故而即使在形成 半球形矽晶粒層210時，已非晶化的梯形複晶矽層2〇6a 發生再結晶化，也是由梯形複晶砂層206a中較深的部份 開始結晶化，而在梯形複晶矽層206a中接近表面較淺的 部份尙未結晶化的時候’半球形矽晶粒層210即可完成。 03764twf3.doc/006 577137 此外，部份緩衝層208的元素，例如氮或氧等，將會在高 能量的離子植入步驟209中，被打進梯形複晶矽層206a 的表層207，可以加長已非晶化的表層207再結晶化所需 的時間，亦有利於順利形成半球形矽晶粒層210。 因此，本發明具有下列特徵： 1·本發明於複晶半導體表層上所形成的緩衝層，可發 揮緩衝的作用，使離子植入步驟的離子植入能量得以提 高，以使較高濃度分佈的離子更接近複晶矽層的表面，進 而加強複晶矽層的表層非晶化的效果。 2. 本發明於梯形複晶矽層的表層上所形成的緩衝層， 使離子植入步驟的離子植入能量得以提高，進而增加離子 植入的深度，可使梯形複晶矽層中較深的部份也能被非晶 化，故而即使在形成半球形矽晶粒層時，已非晶化的梯形 複晶矽層發生再結晶化，也是由梯形複晶矽層中較深的部 份開始結晶化，而且在進行離子植入步驟時，部份緩衝層 的元素，將被打入梯形複晶矽層的表層中，以加長梯形複 晶矽層中接近表面較淺的部份再結晶化所需的時間，因此 本發明可提供足夠的時間，在梯形複晶矽層中接近表面較 淺的部份尙未結晶化的時候，順利於梯形複晶矽層的表層 上形成半球形矽晶粒層。 3. 本發明在進行複晶矽層的非晶化之前，先使複晶矽 層含有兩個側壁，其中兩個側壁的外表面與基底結構之介 電層表面的交角大於90°，以利於使用離子植入法進行側 壁表層的非晶化。 12 03764twf3.doc/006 577137 4.本發明以化學氣相沈積法形成複晶矽層，除了可以 改善習知非晶矽層與基底間介面阻抗較高的問題外，還可 利用複晶矽形成速率較非晶矽爲快的特性，來縮短製程時 間，提高工作產能。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 03764twR.doc/006 13After that, referring to FIG. 2E, the surface layer 207 of the trapezoidal polycrystalline silicon layer 206a is made amorphous. For example, the ion implantation step 209 of the surface layer 207 of the trapezoidal polycrystalline silicon layer 206a is performed in a direction inclined to the surface of the base structure 212, so that the surface layer 207 of the trapezoidal polycrystalline silicon layer 206a is made amorphous. When the inclined ion implantation step 209 is performed from the upper left of FIG. 2E, the surface layer 207 of the left side wall 214 of the amorphized trapezoidal compound silicon layer 206a will be beneficial. Similarly, when from FIG. 2E 03764twf3. Doc / 006, the upper right When the inclined ion implantation step 209 is performed, the surface layer 207 of the right side wall 214 of the amorphized trapezoidal polycrystalline silicon layer 206a will be beneficial. In addition, during the ion implantation step 209, some elements of the buffer layer 208, such as nitrogen or oxygen, will be driven into the surface layer 207 of the trapezoidal polycrystalline silicon layer 206a, and the surface layer 207 that has been amorphized can be lengthened. The time required for crystallization. What's more, the buffer layer 208 can also play a buffering role, so that the ion implantation energy of the ion implantation step 209 can be increased, for example, the polycrystalline semiconductor layer 206a is implanted with phosphorus at an implantation energy of about 100 keV to 200 keV, or For example, arsenic is implanted into the polycrystalline semiconductor layer 206a with an implantation energy of about 120 keV to 300 keV, so that the ions are implanted in the deeper trapezoidal polycrystalline silicon layer 206a and the surface layer 207, and the ions with a higher concentration distribution are closer to the trapezoidal complex. The surface of the crystalline silicon layer 206a further enhances the effect of amorphizing the surface layer 207 of the trapezoidal complex crystal sand layer 206a. Next, referring to FIG. 2F, the buffer layer 208 is removed, and a hemispherical silicon grain layer 210 is formed on the surface layer 207 of the trapezoidal complex crystal silicon layer 206a, and together with the trapezoidal complex crystal sand layer 206a, a storage electrode 220 is formed. The method in which the buffer layer 208 is removed is, for example, an etching method. It is particularly noted that, while the hemispherical silicon grain layer 210 is formed, the trapezoidal polycrystalline silicon layer 206a that has become amorphous will recrystallize, but the present invention uses a high-energy ion implantation step 209, The implanted ion has a deeper depth, which can make the deeper part of the trapezoidal complex crystal silicon layer 206a amorphized. Therefore, even when the hemispherical silicon grain layer 210 is formed, the trapezoidal complex crystal layer 210 has been amorphized. When the crystalline silicon layer 206a recrystallizes, it also begins to crystallize from the deeper part of the trapezoidal complex crystalline sand layer 206a. When the shallower surface of the trapezoidal complex crystalline silicon layer 206a is not crystallized, 'The hemispherical silicon die layer 210 can be completed. 03764twf3.doc / 006 577137 In addition, some elements of the buffer layer 208, such as nitrogen or oxygen, will be driven into the surface layer 207 of the trapezoidal polycrystalline silicon layer 206a in the high-energy ion implantation step 209, which can be lengthened The time required for recrystallization of the surface layer 207 that has been amorphized also facilitates the formation of the hemispherical silicon grain layer 210. Therefore, the present invention has the following features: 1. The buffer layer formed on the surface of the polycrystalline semiconductor according to the present invention can play a buffering role, so that the ion implantation energy of the ion implantation step can be increased, so that a higher concentration distribution The ions are closer to the surface of the polycrystalline silicon layer, thereby enhancing the effect of amorphization of the surface layer of the polycrystalline silicon layer. 2. The buffer layer formed on the surface layer of the trapezoidal polycrystalline silicon layer according to the present invention enables the ion implantation energy of the ion implantation step to be increased, thereby increasing the depth of ion implantation, and making the trapezoidal polycrystalline silicon layer deeper. The part can also be amorphized, so even when the hemispherical silicon grain layer is formed, the recrystallized trapezoidal polycrystalline silicon layer is formed by the deeper part of the trapezoidal polycrystalline silicon layer. Began to crystallize, and during the ion implantation step, some elements of the buffer layer will be driven into the surface layer of the trapezoidal polycrystalline silicon layer to recrystallize the shallower surface of the trapezoidal polycrystalline silicon layer. The time required for the crystalization, therefore, the present invention can provide sufficient time to successfully form a hemispherical silicon on the surface of the trapezoidal polycrystalline silicon layer when it is not crystallized near the shallower surface of the trapezoidal polycrystalline silicon layer. Grain layer. 3. Prior to the amorphization of the polycrystalline silicon layer of the present invention, the polycrystalline silicon layer is made to contain two side walls, wherein the intersection angle between the outer surface of the two side walls and the surface of the dielectric layer of the base structure is greater than 90 °, so as to facilitate Amorphousization of the sidewall surface layer was performed using an ion implantation method. 12 03764twf3.doc / 006 577137 4. The present invention uses a chemical vapor deposition method to form a polycrystalline silicon layer. In addition to improving the conventional problem of high impedance between the amorphous silicon layer and the substrate, it can also be formed using polycrystalline silicon. The speed is faster than that of amorphous silicon to shorten the process time and increase the working capacity. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. 03764twR.doc / 006 13