JPS62119009U - - Google Patents

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Publication number
JPS62119009U
JPS62119009U JP515886U JP515886U JPS62119009U JP S62119009 U JPS62119009 U JP S62119009U JP 515886 U JP515886 U JP 515886U JP 515886 U JP515886 U JP 515886U JP S62119009 U JPS62119009 U JP S62119009U
Authority
JP
Japan
Prior art keywords
capacitor
load
circuit
damped vibration
inductance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP515886U
Other languages
Japanese (ja)
Other versions
JPH0332091Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986005158U priority Critical patent/JPH0332091Y2/ja
Publication of JPS62119009U publication Critical patent/JPS62119009U/ja
Application granted granted Critical
Publication of JPH0332091Y2 publication Critical patent/JPH0332091Y2/ja
Expired legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の減衰振動発生回路の実施例に
よる電気回路図、第2図は第1図の回路によつて
生じた振動波形図、第3図は従来の減衰振動発生
回路の例の電気回路図、第4図は第3図の回路に
よつて生じた振動波形図である。 なお、1:直流電源、2,5:抵抗、3:コン
デンサ、4:インダクタンス、6:ゲート制御回
路、7:サイリスタ、8:ゲート。
Fig. 1 is an electrical circuit diagram of an embodiment of the damped vibration generation circuit of the present invention, Fig. 2 is a vibration waveform diagram generated by the circuit of Fig. 1, and Fig. 3 is an example of a conventional damped vibration generation circuit. The electrical circuit diagram, FIG. 4, is a diagram of vibration waveforms generated by the circuit of FIG. 3. Note that 1: DC power supply, 2, 5: resistor, 3: capacitor, 4: inductance, 6: gate control circuit, 7: thyristor, 8: gate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 直流電源1により充電されたコンデンサ3の電
荷を抵抗5とインダクタンス4とよりなる回路を
負荷として放電する減衰振動発生回路において、
前記コンデンサ3と前記負荷との間にゲート8が
制御される一方向性サイリスタ7を接続してなる
減衰振動発生回路。
In a damped vibration generation circuit that discharges the electric charge of a capacitor 3 charged by a DC power source 1 using a circuit consisting of a resistor 5 and an inductance 4 as a load,
A damped vibration generating circuit comprising a unidirectional thyristor 7 whose gate 8 is controlled is connected between the capacitor 3 and the load.
JP1986005158U 1986-01-20 1986-01-20 Expired JPH0332091Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986005158U JPH0332091Y2 (en) 1986-01-20 1986-01-20

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986005158U JPH0332091Y2 (en) 1986-01-20 1986-01-20

Publications (2)

Publication Number Publication Date
JPS62119009U true JPS62119009U (en) 1987-07-28
JPH0332091Y2 JPH0332091Y2 (en) 1991-07-08

Family

ID=30786483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986005158U Expired JPH0332091Y2 (en) 1986-01-20 1986-01-20

Country Status (1)

Country Link
JP (1) JPH0332091Y2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5651111A (en) * 1979-10-04 1981-05-08 Tohoku Metal Ind Ltd Device for supply of spurious noise on power source current
JPS57153346A (en) * 1981-03-18 1982-09-21 Fujitsu Ltd Noise voltage generation tester

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5651111A (en) * 1979-10-04 1981-05-08 Tohoku Metal Ind Ltd Device for supply of spurious noise on power source current
JPS57153346A (en) * 1981-03-18 1982-09-21 Fujitsu Ltd Noise voltage generation tester

Also Published As

Publication number Publication date
JPH0332091Y2 (en) 1991-07-08

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