JPH0332091Y2 - - Google Patents
Info
- Publication number
- JPH0332091Y2 JPH0332091Y2 JP1986005158U JP515886U JPH0332091Y2 JP H0332091 Y2 JPH0332091 Y2 JP H0332091Y2 JP 1986005158 U JP1986005158 U JP 1986005158U JP 515886 U JP515886 U JP 515886U JP H0332091 Y2 JPH0332091 Y2 JP H0332091Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- thyristor
- capacitor
- inductance
- vibration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 4
- 230000002457 bidirectional effect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010891 electric arc Methods 0.000 description 2
- 230000003534 oscillatory effect Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Generation Of Surge Voltage And Current (AREA)
Description
【考案の詳細な説明】
〔産業上の利用分野〕
本考案はサイリスタを振動波の発生源とする擬
似雑音用の減衰振動発生回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a damped vibration generation circuit for pseudo noise using a thyristor as a source of vibration waves.
擬似雑音発生器において高振幅の減衰振動波を
発生させる回路は振動波の発生部に放電ギヤツプ
または継電器を用いコンデンサなどに充電したエ
ネルギーをインダクタンスと抵抗からなる負荷に
放電する手段が用いられている。従来この種の発
生回路の例は第3図のように高圧直流電源1より
抵抗2を経てコンデンサ3に充電されたエネルギ
ーは継電器11を動作させるとその接点12を閉
成し、抵抗5とインダクタンス4を負荷とする回
路に放電する。このときコンデンサ3の容量値と
インダクタンス4の値によつて固有の振動が発生
し、継電器11の動作時に接点12に起こるアー
ク放電が発生し第4図のように減衰振動が発生す
る。
The circuit that generates high-amplitude damped oscillatory waves in pseudo-noise generators uses a discharge gap or relay in the oscillatory wave generation section to discharge the energy charged in a capacitor or the like to a load consisting of inductance and resistance. . Conventionally, an example of this kind of generation circuit is as shown in Fig. 3. Energy charged in a capacitor 3 from a high-voltage DC power supply 1 via a resistor 2 operates a relay 11, which closes its contact 12, and is connected to a resistor 5 and an inductance. 4 is discharged into a circuit with a load. At this time, a unique vibration is generated depending on the capacitance value of the capacitor 3 and the value of the inductance 4, and when the relay 11 is operated, an arc discharge occurs at the contact point 12, and a damped vibration is generated as shown in FIG.
しかし従来の減衰振動の発生手段では連続して
使用した場合、接点12の劣化を生じ、また発生
はアーク放電で行なわれるため安定な放電が得ら
れず、第4図の波形において波尾に点線のような
正しい波形が得られず、実線のように波形に歪を
正じ、振幅が不安定で振動が途切れるなどの欠点
がある。
However, if the conventional damped vibration generating means is used continuously, the contact 12 deteriorates, and since the generation is performed by arc discharge, stable discharge cannot be obtained. It has disadvantages such as not being able to obtain the correct waveform as shown in the solid line, correcting the distortion in the waveform as shown in the solid line, the amplitude being unstable, and the vibration being interrupted.
本考案は従来のかかる欠点を除き、高圧直流電
源1より充電されたコンデンサ3の電荷を抵抗5
とインダクタンス4とよりなる回路を負荷として
放電する擬似雑音用の減衰振動発生回路におい
て、コンデンサ3と負荷との間にゲートが制御さ
れるサイリスタを接続してなる減衰振動発生回路
であり、安定な振動を発生させるにある。
The present invention eliminates such drawbacks of the conventional method and transfers the electric charge of the capacitor 3 charged from the high voltage DC power supply 1 to the resistor 5.
In a damped vibration generation circuit for pseudo noise that discharges a circuit consisting of an inductance 4 and an inductance 4 as a load, the damped vibration generation circuit is a damped vibration generation circuit formed by connecting a thyristor whose gate is controlled between the capacitor 3 and the load, and is stable. The purpose is to generate vibrations.
サイリスタがオン状態から逆バイアスされてカ
ツトオフされるまでの蓄積時に逆方向電流を流し
て双方向スイツチとして振動電流を流すものであ
る。
When the thyristor is reverse biased from the on state and accumulates until it is cut off, a reverse direction current flows, and an oscillating current flows as a bidirectional switch.
〔実施例〕
本考案の減衰振動発生回路の実施例は第1図に
示すように直流電源1より抵抗2を径て充電され
たコンデンサ3との充電回路とインダクタンス4
と抵抗5とを負荷とする放電回路との間にゲート
制御回路6によつてゲート8が制御される一方向
サイリスタ7を接続して形成される。[Embodiment] As shown in FIG. 1, an embodiment of the damped vibration generating circuit of the present invention includes a charging circuit with a capacitor 3 charged from a DC power source 1 through a resistor 2, and an inductance 4.
A one-way thyristor 7 whose gate 8 is controlled by a gate control circuit 6 is connected between the discharge circuit and the discharge circuit having a resistor 5 as a load.
いま直流電源1によりコンデンサが充電された
とき、ゲート制御回路6からサイリスタ7のゲー
ト8に電流を流すと、サイリスタ7は急にオン状
態となりコンデンサ3は抵抗5とインダクタンス
4を負荷とする放電回路に放電しはじめる。オン
の時にアノード9からカソード10に回つて電流
が流れ逆方向にバイアスされたときに微少な電流
のみが流れるサイリスタ7がオン状態から逆バイ
アスされるカツトオフするまでの蓄積時間にゲー
ト8に逆方向電流を流す。したがつてオン電流は
コンデンサ3の容量Cとインダクタンス値Lで構
成される共振周波数Fの周期で振動をはじめ、さ
らに電流が流れてから1/2F時間後に通常のサイ
リスタ7の使用状態では生じない逆流がはじま
る。しかしゲート8より注入され順方向電流によ
つて発生したキヤリアがサイリスタ7内に存在し
ている逆回復時中には整流特性は示さず逆回復時
間に対し振動周期が十分小さいときは双方向性サ
イリスタ7でなく振動電流は流れる。したがつて
振動波は第2図のように放電現象により発生する
波形の波尾にみだれは生じなく安価な一方向性サ
イリスタ7で擬似雑音を発生させることができ
る。 Now, when the capacitor is charged by the DC power supply 1, when a current is passed from the gate control circuit 6 to the gate 8 of the thyristor 7, the thyristor 7 is suddenly turned on and the capacitor 3 becomes a discharge circuit whose load is the resistor 5 and inductance 4. begins to discharge. When the thyristor 7 is on, a current flows from the anode 9 to the cathode 10, and when it is biased in the reverse direction, only a small current flows.Thyristor 7 is reverse biased from the on state, and during the accumulation time until it is cut off, a current flows in the reverse direction to the gate 8. Pass current. Therefore, the on-current starts to oscillate at the period of the resonant frequency F, which is composed of the capacitance C of the capacitor 3 and the inductance value L, and does not occur in the normal usage state of the thyristor 7 after 1/2 F time after the current flows. Backflow begins. However, during the reverse recovery period when the carrier generated by the forward current injected from the gate 8 exists in the thyristor 7, the rectification characteristic is not exhibited, and when the oscillation period is sufficiently small with respect to the reverse recovery time, the thyristor exhibits bidirectional characteristics. The oscillating current flows through the thyristor 7 instead. Therefore, as shown in FIG. 2, the waveform of the vibration wave generated by the discharge phenomenon does not have any droop at its tail, and pseudo noise can be generated using the inexpensive unidirectional thyristor 7.
以上に述べたように本考案によれば、従来のよ
うに継電器のような機械的要素を用いることなく
1個の一方向性サイリスタ7を用いて双方向スイ
ツチの性能を持たせ高振幅で安定がよく振動波に
乱れが生じない振動波が得られる擬似雑音発生器
に適した振動波発生回路が得られる。
As described above, according to the present invention, a single unidirectional thyristor 7 is used to provide the performance of a bidirectional switch, without using a mechanical element such as a relay as in the past, and it is stable with high amplitude. A vibration wave generation circuit suitable for a pseudo-noise generator that can generate vibration waves with good vibration and no disturbance is obtained.
第1図は本考案の減衰振動発生回路の実施例に
よる電気回路図、第2図は第1図の回路によつて
生じた振動波形図、第3図は従来の減衰振動発生
回路の例の電気回路図、第4図は第3図の回路に
よつて生じた振動波形図である。
なお、1:直流電源、2,5:抵抗、3:コン
デンサ、4:インダクタンス、6:ゲート制御回
路、7:サイリスタ、8:ゲート。
Fig. 1 is an electrical circuit diagram of an embodiment of the damped vibration generation circuit of the present invention, Fig. 2 is a vibration waveform diagram generated by the circuit of Fig. 1, and Fig. 3 is an example of a conventional damped vibration generation circuit. The electrical circuit diagram, FIG. 4, is a diagram of vibration waveforms generated by the circuit of FIG. 3. Note that 1: DC power supply, 2, 5: resistor, 3: capacitor, 4: inductance, 6: gate control circuit, 7: thyristor, 8: gate.
Claims (1)
荷を抵抗5とインダクタンス4とよりなる回路を
負荷として放電する減衰振動発生回路において、
前記コンデンサ3と前記負荷との間にゲート8が
制御される一方向性サイリスタ7を接続してなる
減衰振動発生回路。 In a damped vibration generation circuit that discharges the electric charge of a capacitor 3 charged by a DC power source 1 using a circuit consisting of a resistor 5 and an inductance 4 as a load,
A damped vibration generating circuit comprising a unidirectional thyristor 7 whose gate 8 is controlled is connected between the capacitor 3 and the load.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986005158U JPH0332091Y2 (en) | 1986-01-20 | 1986-01-20 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986005158U JPH0332091Y2 (en) | 1986-01-20 | 1986-01-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62119009U JPS62119009U (en) | 1987-07-28 |
JPH0332091Y2 true JPH0332091Y2 (en) | 1991-07-08 |
Family
ID=30786483
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986005158U Expired JPH0332091Y2 (en) | 1986-01-20 | 1986-01-20 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0332091Y2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5651111A (en) * | 1979-10-04 | 1981-05-08 | Tohoku Metal Ind Ltd | Device for supply of spurious noise on power source current |
JPS57153346A (en) * | 1981-03-18 | 1982-09-21 | Fujitsu Ltd | Noise voltage generation tester |
-
1986
- 1986-01-20 JP JP1986005158U patent/JPH0332091Y2/ja not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5651111A (en) * | 1979-10-04 | 1981-05-08 | Tohoku Metal Ind Ltd | Device for supply of spurious noise on power source current |
JPS57153346A (en) * | 1981-03-18 | 1982-09-21 | Fujitsu Ltd | Noise voltage generation tester |
Also Published As
Publication number | Publication date |
---|---|
JPS62119009U (en) | 1987-07-28 |
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