JPS62118628A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain the performance excellent in those all such as insertion loss, maximum gain control quantity and broad band by forming the titled device by three FETs sealed in a package and plural external lead terminals. CONSTITUTION:The drain electrode of the FET 5 is connected to the drain electrode of the FET 6, the connecting point 15 is connected to the external lead terminal 8 and the source electrode of the FET 6 is connected to the external lead terminal 9. Further, the drain electrode of the FET 7 is connected to the external lead terminal 10, the source electrodes of the FETs 5, 7 are connected to the external lead terminal 11, the gate electrodes of the FETs 5, 7 are connected together, its connecting point 16 is connected to the external lead terminal 12 via a resistor 17 and the gate electrode of the FET 6 is connected to the external lead terminal 13 via a resistor 18. A capacitor 19 is mounted externally between the external lead terminals 9 and 10, the external lead terminal 9 is connected to common together with the external lead terminal 11 via an externally mounted choke coil 20 and the external lead terminals 10 and 8 are used respectively as input and output terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a variable attenuator semiconductor device for electrical signals, particularly high frequency electrical signals.

Conventional technologyHigh frequency variable attenuators are used in wideband amplifiers that require particularly low distortion, such as boosters and CAT''/converters.
It is often used to multiply C and C.

Conventionally, for this purpose, a variable attenuator was constructed by connecting PiN diodes using Si as shown in FIG. 5B. This takes advantage of the fact that the forward resistance of a PiN diode changes depending on the applied voltage.1 The high frequency equivalent circuit of FIG. 5a is expressed as shown in FIG. 6. By changing the resistance values R1 and R2 of 2 as shown in FIG. 4, a desired amount of attenuation can be obtained. PiN diodes have low capacitance, and the resistance when ON is as low as 7Ω, and the resistance when OFF can be increased to 1Ω, so it has a low insertion loss of about 1dB and
A large attenuation of 0 to 5 odB is 60 to 10010
Conventionally, most attenuators using PiN diodes have been used for this purpose because they can be obtained at a high frequency of 0O over a wide band.

Problems to be Solved by the Invention However, such an attenuator has a problem in that current consumption is large, about 10 mA, because current flows in the forward direction through the PiN diode. Furthermore, the number of parts was large, which was disadvantageous for aiming at compact packaging.

Means for Solving the Problems In order to solve the above problems, the present invention comprises three FETs sealed in a package and a plurality of external lead-out terminals, and the drain electrode of the first FET is connected to the second FET. The source electrode of the second FET is connected to the drain electrode of the third FET, and the two connection points, the source electrodes of the first and third FETs, and the third Provided is a semiconductor device characterized in that gate electrodes of individual FETs are connected to separate external lead-out terminals.

Effect With this configuration, by simply using the channel of the GaAsFET as a resistor and changing the gate bias, a variable range of about 5 to 10 Ω can be easily obtained. At this time, since almost no bias current needs to flow, it is possible to reduce power consumption.

Example The present invention will be explained based on the embodiment shown in FIG.

As shown in FIG. 1, three GaAsF1! : TaN2, six external lead-out terminals 8 to 13, and two resistors 17°18 are sealed in a package, and the drain electrode of FET6 is connected to FET6.
It is connected to the drain electrode of ET6, its connection point 16 is connected to external lead-out terminal 8, the source electrode of FET6 is connected to external lead-out terminal 9, the drain electrode of FET7 is connected to external lead-out terminal 1o, and FET5 and The source electrode of FET 7 is connected to the external lead terminal 11, the gate electrodes of FET 6 and 7 are connected to each other, the connection point 16 of 1 is connected to the external lead terminal 12 via the resistor 17, and the gate electrode of FET 7 is connected to the external lead terminal 11. resistance 18
It is connected to the external lead-out terminal 13 via.

A capacitor 19 is externally connected between external lead-out terminals 9 and 10,
The external lead-out terminal 9 is connected externally via the choke coil 2o.
By grounding together with external lead terminal 11 and using external lead terminals 10 and 8 as input terminal and output terminal, respectively,
A high frequency equivalent circuit shown in FIG. 6 is formed.

The channel resistance of FET6 is set to resistor 1 (R1), and the FET
The channel resistances of FET 6 and FET 7 correspond to resistance 2 (R2). Each channel resistance of the FET is determined by the reverse bias vG+''G2 applied between the external lead terminal 13゜12 connected to the gate electrode and the ground point connected to the source electrode.
is controlled so that the value shown in FIG. 4 is obtained. According to the above configuration, υ, the source of FETe and the FET:
The drain of T7 is separated from DC and connected to separate external lead-out terminals 9 and 10 in order to apply a bias, and both row lead-out terminals 9 and 1o are connected only to AC through capacitor C1. . The choke coil 20 is FE
This is to make the Te source Ov in a direct current manner.

However, when using it with an attenuation of 6 dB or more, when applying a negative bias to the external lead-out terminal 13 connected to the gate of FET 6, as shown in Figure 4, the channel resistance of FET y has a resistance value of 300 Ω or less. As shown in FIG. 2, capacitor 19. of FIG. A simplified circuit configuration is possible in which the choke coil 2o is omitted, the source terminal of FETa is connected to the drain terminal of FET 7, the connection point 21 is connected to the external lead-out terminal 22, and this terminal is used as an input terminal. It is.

Furthermore, it is also possible to form a monolithic IC within the dotted lines in FIGS. 1 and 2 by the following method. In order to make the channel resistance of FET 6 ON to 6Ω and the channel resistance of FETs 7 and 6 to 8OΩ, the gate dimensions of FET 6 were designed to be 1×1000 μm, and the gate dimensions of FETs 7 and 6 were designed to be 1×60 μm. The spacing between the source electrode and the gate electrode and between the gate electrode and the drain electrode were both 1 μm. The chip size is 0.5×O, 8mm.

The gate electrode was formed in a multilayer structure of T i /P + /muU, the ohmic layer was formed in muGe/Mi/Au, and the wiring was formed in a Ti/Au multilayer structure. Each FET had an active layer and an n+ layer formed by implanting Si ions into a semi-insulating substrate. Furthermore, the external lead-out terminals in FIGS. 1 and 2 are replaced with bonding pads 8, 9, 10 (22), and 11.

12. External terminal 2 of the package shown in Figure 13 respectively.
3, 24, 25, 28, 27.28 were wire bonded and sealed. In this way, the prototype GaAs IC
The insertion loss of the attenuator is 0.6 dB.

A maximum gain control amount of 40 dB was obtained in the high frequency band of 60 to 100,100 O.

Although the above description has been made using a GaAsFET as an example, the present invention can also be implemented using a 5iFIET, as is clear from its principle.

Effects of the Invention As described above, according to the present invention, insertion loss and
Excellent performance can be obtained in terms of maximum gain control amount, wideband performance, etc. This is because the internal capacity of the source and drain of the GaAsFET is extremely small.

Furthermore, as can be seen from the above explanation, since no direct current flows through the FET channel, this method is significantly more advantageous than the conventional method in terms of power consumption.

However, GaAs has the advantage of being integrated into ICs and can be made extremely small.

[Brief explanation of drawings]

Figures 1 and 2 are circuit diagrams showing one embodiment of the present invention, and Figure 3 is a circuit diagram showing an embodiment of the present invention.
The figure is a schematic external view of a device in which a monolithic IC chip having the circuit configuration shown in FIGS. 1 and 2 is mounted in a package.
Fig. 4 is a characteristic diagram showing the relationship between resistance value and attenuation of the circuit shown in Fig. 6, Fig. 6a is a circuit diagram of an attenuator using a conventional PiN diode, and Fig. 5 is its high frequency equivalent circuit diagram. It is. 1~4.17.18,32.33...mark/resistance, 6~7
・・・・・・FET, 8~13.22・River・・External lead-out terminal, 14・・・・Package, 15, 16.21
...Connection point, 19.34-37... Capacitor, 2o. 38...Choke coil, 23...Output terminal, 24...FET source terminal, 26...River...
・Input terminal, 26... Ground terminal, 27...
・・Gate bias terminal of FET7, 5, 28・・・・
...yx'rs gate bias terminal, 29-31...
...PiN diode. Name of agent: Patent attorney Toshio Nakao and 1 other person 5+
7-・fE7 Il, If--Ichiryo Akatsuki, Miia, 1J---Se I J919-11 cop Y no f na r---4,,Go4Ishi@2Figure 2f-Nuikawa 22-Output phantom--output, c1)
(□-1゜32.33-11㎖洛 37--1-t de'n T Ihe 4--U: Friend,

Claims (3)

[Claims] (1) Consisting of three FETs sealed in a package and a plurality of external lead-out terminals, the drain electrode of the first FET is connected to the drain electrode of the second FET, and the second FET is connected to the drain electrode of the second FET.
The source electrode of the ET is connected to the drain electrode of the third FET, and the two connection points, the source electrodes of the first and third FETs, and the gate electrodes of the three FETs are each separately led out. A semiconductor device characterized by being connected to a terminal. (2) The connection between the source electrode and the third drain electrode of the second FET is removed, and the two electrodes are connected to the first and second FET.
a connection point between the drain electrodes of the ET, the first and third FE;
The semiconductor device according to claim 1, wherein the semiconductor device is connected to separate external lead-out terminals other than the external lead-out terminals respectively connected to the source electrode of the transistor T and the gate electrodes of the three FETs. (3) removing the connection between the gate electrodes of the first and third FETs and the external lead-out terminals, and connecting both the gate electrodes to each other;
This connection point is connected to the connection point between the drain electrodes of the second and first FETs, the connection point between the first and third source electrodes, and the three FETs.
3. The semiconductor device according to claim 1, wherein the semiconductor device is connected directly or via a resistor to separate external lead-out terminals other than the external lead-out terminals respectively connected to the gate electrodes of T.