JPH05183161A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device capable of unifying the power supply for power FETs, etc., for use in microwave communication wherein one power supply for power FETs is realized by a small power capacity resistor by simplifying a process of resistor formation and distributing a drain current to a plurality of unit source electrodes. CONSTITUTION:An extended part of a source electrode 1 of a field effect transistor(FBT) formed on a semiconductor substrate is partly removed to interrupt a circuit, on which interrupted part there is formed a resistor 4 for provision of one power supply type gate bias voltage. Further, in this case, the source electrode is constructed with a plurality of unit source electrodes 1 and the resistor 4 is formed on each unit source electrode 1 to distribute a drain current to each unit source electrode 1, whereby even any small power capacity resistor is prevented from being burned out owing to heating.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device capable of realizing a single power source such as a power FET used for microwave communication.

In recent years, mobile communication represented by a mobile phone, a car phone, etc., satellite communication performed between a base station on land and an artificial satellite over the earth, and satellite communication between satellites have been carried out. It is showing remarkable development, and it is predicted that it will continue to develop at an accelerated pace.

In such a communication system, a power F represented by a GaAs MESFET for the purpose of high frequency power amplification in a high frequency signal receiving and transmitting section.
ET is used.

As a method of applying a gate bias voltage for properly operating the FET such as MESFET, a ground potential and a power source of negative voltage and positive voltage are used.
There are a power supply system and a single power supply system in which one power supply is used by using resistors and capacitors in an external circuit.

[0005]

2. Description of the Related Art FIGS. 2A and 2B are explanatory views of a gate bias system of an FET. FIG. 2A shows a circuit of the dual power supply gate bias system, and FIG. 2B shows a circuit of the single power supply gate bias system.

In the dual power supply gate bias system of FIG. 2 (A), a negative gate bias voltage is applied to the gate electrode G through the inductance L ₁ by the negative power supply −V _G , and the drain electrode D through the inductance L _2. A positive drain voltage is applied by the positive power source + V _D , and the source electrode S is grounded.

The drain current is controlled by the signal input from the input terminal IN via the coupling capacitor C ₁ , and the amplified signal is output from the output terminal OUT through the coupling capacitor C ₂ .

C ₃ is a capacitor for coupling a high frequency signal to the source electrode S. This dual power supply method has excellent stability of the gate bias voltage, but on the other hand, it is necessary to provide two positive and negative power supplies, and there is a problem in that the number of wirings is increased.

In the single power supply gate bias system of FIG. 2B, a positive drain voltage is applied to the drain electrode D through the inductance L ₃ by the positive power supply + V _D , and the drain current I _ds is attached to the outside. Resistance R ₂
The negative voltage is equivalently applied to the gate electrode G through the resistor R ₁ by the potential difference generated across the resistor R ₂ . Incidentally, C ₅ and C ₇ are capacitors for high frequency passage.

The drain current is controlled by the signal input from the input terminal IN via the coupling capacitor C ₄ , and the amplified signal is output from the output terminal OUT through the coupling capacitor C ₆ . This one power source system has an advantage that the operating voltage of the FET can be given by one power source.

FIG. 3 is a diagram showing the structure of a conventional FET for a single power supply gate bias system. In this figure, 11 is a unit source electrode, 12 is a drain electrode, 13 is a gate electrode, 14 is an external source electrode, and 15 is a chip resistor.

In this conventional FET, a drain electrode 12 and unit source electrodes 11 are arranged on both sides of the semiconductor substrate, and a gate electrode 13 is arranged between the drain electrode 12 and the unit source electrode 11. A large number of unit structures are arranged side by side, and the depletion layer in the channel formed between the drain electrode 12 and the unit source electrode 11 is controlled by the voltage applied to the gate electrode 13.

The unit source electrodes 11 are collectively connected in parallel by an external electrode 14 to amplify a large amount of power, and a chip resistor 15 is connected to the external electrode 14. A gate bias voltage based on a single power supply system can be applied.

[0014]

In the conventional FET for a single power supply system, as shown in FIG. 2B, a resistor R ₂ externally attached to the source electrode and a high frequency passing capacitor C _{5 are used.} Therefore, the manufacturing process was complicated.

If the FET is for low power and the drain current I _ds is small, the external resistor R ₂ may be a resistor for relatively low power, such as a commercially available chip resistor or Although a thin film resistor or the like may be used, in the case of a high power FET, the current flowing through this resistor is large and reaches about 1 to 10 A, so that the resistor as described above burns out and becomes unusable.

The present invention simplifies the manufacturing process by forming a resistor in the extension of the source electrode in the manufacturing process of the FET, and divides the source electrode into a plurality of unit source electrodes. The purpose of the present invention is to enable the power FET to have a single power source by forming a resistor in each of the resistors and dispersing the drain current in each resistor.

[0017]

In a semiconductor device according to the present invention, a source electrode extension portion of an FET formed on a semiconductor substrate is partially removed, and a resistor for applying a gate bias voltage to the source electrode extension portion is provided there. Formed body.

In the above case, the source electrode of the FET is divided into a plurality of unit source electrodes, and a resistor for applying a gate bias voltage is formed on the extension of each unit source electrode by the one power supply method.

[0019]

The FE formed on the semiconductor substrate as in the present invention
The manufacturing process can be simplified by removing a part of the source electrode extension of T and forming a resistor for applying a gate bias voltage by the one power supply method, and the source electrode of the FET can be formed into a plurality of unit source electrodes. When the resistor is divided and a resistor is formed on each unit source electrode, when a gate bias voltage is applied using this resistor, the drain current is dispersed to each unit source electrode, so the current flowing through each resistor is reduced. It is possible to prevent the resistor from generating heat and burning out.

[0020]

EXAMPLE An example of the semiconductor device of the present invention will be described below. FIG. 1 is a configuration explanatory diagram of a FET for a single power supply gate bias system according to an embodiment of the present invention. In this figure,
Reference numeral 1 is a unit source electrode, 2 is a drain electrode, 3 is a gate electrode, 4 is a resistor, and 5 is an external electrode.

In the FET of this embodiment, a drain electrode 2 and unit source electrodes 1 are arranged on both sides of the semiconductor substrate, and the drain electrode 2 and the unit source electrode 1 are arranged.
A plurality of unit structures in which the gate electrode 3 is arranged between them are arranged side by side, and depending on the voltage applied to the gate electrode 3,
Although not shown, the drain electrode 2 and the unit source electrode 1
It controls the depletion layer in the channel that is formed between the two.

Then, the metal film constituting each unit source electrode 1 or its extension is partially removed, and a metal resistance thin film is deposited on the trace by sputtering, or in a semiconductor substrate which is a semi-insulator. Resistors 4 are formed by ion-implanting impurities to have a desired resistance value, and the side opposite to the source electrode of each resistor 4 is connected by an external electrode 5 to perform amplification of high power. It has become.

According to this embodiment, the conventional semiconductor manufacturing technique can be applied to the step of forming the resistors in each of the source electrodes, and therefore it is necessary to connect the discrete resistors as in the conventional technique. However, it can be easily manufactured. Also, since a large number of unit source electrodes are juxtaposed, the drain current is distributed to each unit source electrode,
Even if the resistor formed in each unit source electrode is made to have a small power capacity, the resistor is not burned due to heat generation, and a large power operation can be realized as a whole. As a capacitor for high frequency passage, a DC current does not flow, as a matter of course, and therefore an external commercially available capacitor or the like can be used.

[0024]

As described above, according to the present invention,
A resistor for applying a gate bias voltage to the FET can be easily formed, and since the drain current is divided into each unit source electrode, the resistor for generating the gate bias voltage is prevented from burning due to heat generation, and power is prevented. FET can be provided.

[Brief description of drawings]

FIG. 1 is a configuration explanatory diagram of an FET for one power supply gate bias system according to an embodiment of the present invention.

2A and 2B are explanatory diagrams of a gate bias system of an FET.

FIG. 3 is a diagram illustrating the structure of a conventional FET for a single power supply gate bias system.

[Explanation of symbols]

 1 unit source electrode 2 drain electrode 3 gate electrode 4 resistor 5 external electrode

Claims (2)

[Claims] 1. A circuit is cut off by removing a part of a source electrode extension of a field effect transistor (FET) formed on a semiconductor substrate, and a gate bias voltage is applied to the cut off part by a single power supply system. A semiconductor device characterized in that a resistor is formed to provide a charge. 2. The source electrode of a field effect transistor (FET) formed on a semiconductor substrate is composed of a plurality of unit source electrodes, and an extension of each unit source electrode is partially removed to disconnect the circuit, A semiconductor device, wherein a resistor for applying a gate bias voltage is formed in a part where the circuit is cut off by a single power supply method, and a drain current is distributed to each unit source electrode.