JPS62117011A - Channel display device for input and output unit - Google Patents

Abstract

PURPOSE:To improve the working efficiency at the user side by knowing the channel numbers of input/output units even in a dark place without counting the number of rack devices and those input/output units. CONSTITUTION:The number of channels are detected for input/output units 11-1-11-n respectively before execution of a main body program. At the same time, these detected channel numbers are integrated to obtain the head channel number value of those units 11-1-11-n respectively. These channel number values are displayed on each display device 12 of units 11-1-11-n. Thus it is possible to know the channel numbers of the units 11-1-11-n just with a single glance given to each device 12.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a channel display device for an input/output unit that displays a channel number on an input/output unit attached to a programmable controller.

<Summary of the Invention> A channel display device for an input/output unit according to the present invention detects the number of channels of each input/output unit attached to a programmable controller main body by means of a channel number detection means, and detects the number of channels of each input/output unit attached to a programmable controller main body by means of a channel number display means based on the detection result. By displaying the channel number on the display of the input/output unit, it is possible to know the channel number of these input/output units without knowing the rack number and unit number in which these input/output units are installed. It is.

<Prior art> In a programmable controller (hereinafter referred to as PC) that executes sequence processing, an input/output unit is installed in the programmable controller 2 body (PC body), which is the main part of this PC, and this input/output unit Accordingly, the signals from the PC main body are matched with the signals input to the PC main body and the signals of devices controlled by the PC main body, and the signals are converted.

FIG. 6 is a front view showing an example of a PC system using such an input/output unit.

The system shown in this figure is a system in which a plurality of CPU rack devices 2 to 6 are connected, and a CPU main body (PC main body) 7 of the CPU device 1 is installed on the CPU device and each rack device 2 to 6. It is designed to control a large number of input/output units 8-1 to 8-n.

<Problems to be Solved by the Invention> However, in this type of system, several channels are assigned to each input/output unit 8-1 to 8-n. like,
When you want to know the channel number of a specific input/output unit or to which input/output unit a specific channel is assigned, count the input/output units in the rack device with the lowest number from the left and select this input/output unit. It was not possible to know the channel number of a specific input/output unit or which input/output unit a specific channel was included in without mentally adding up the number of channels included in the units.

For this reason, when this system is installed in a dark place or when there are a large number of rack devices, it is easy to miscount the number of racks and input/output units and misrecognize the channel numbers of the input/output units. There were problems such as reduced work efficiency during depacking work and the need to replace another input/output unit.

In order to eliminate such inconvenience, in such a 7-stem system, each input/output unit 8-1 to 8-n is appropriately picked up by a program console 9 provided in the CPU device 1. 9 to read the data of each input/output unit, and
As shown in the figure, the channel number N-CH of this picked up input/output unit is set to the rack number N at this time.
-L.

There is also a method of displaying unit numbers NU and input/output information in association with each other.

However, although this method eliminates the task of adding up the number of channels assigned to each input/output unit, it is necessary to actually count the rack devices and input/output units to determine the desired input/output unit. There is a problem in that it is not possible to know where the output unit is.

In view of the above circumstances, the present invention makes it possible to know the channel number of an input/output unit even in a dark place without having to count the sides of the rack device or input/output unit, thereby improving work efficiency on the user side. The purpose is to provide a channel display device for input/output units.

<Means for Solving the Problems> In order to solve the above-mentioned problems, the input/output unit channel display device according to the present invention has a channel display device that is attached to a programmable controller main body and that matches between the programmable controller main body and external equipment. A channel display device for an input/output unit that displays the channel number of the input/output unit includes a channel number detection means for detecting the number of channels of each input/output unit, and a channel number detection means for detecting the number of channels of each input/output unit; The present invention is characterized by comprising a channel number display means for displaying a channel number on a display provided at the channel number.

<Embodiment> FIG. 1 is a circuit block diagram showing an embodiment of a channel display device for an input/output unit according to the present invention.

The device shown in this figure reads out the number of input and output channels 11-1 to 11-n using the PC main body 10 to determine the channel numbers of each input/output unit 11-1 to 11-n. Connect this to each input/output (22) 11-
1 to 11-n and each indicator 1 provided thereon.
2 is configured to display each channel number, and the inside of the PC main unit 10 executes the above-mentioned channel number readout process (channel number detection function) and channel number display process (channel number display function). C.P.
A UI 3 and a memory 14 serving as a work area for the CPU 13 are provided.

In this case, the CPU 13 includes an arithmetic device such as a microprocessor, a ROM (read-only memory) in which a system program for the arithmetic device is stored, and a RAM (read-only memory) in which a user program regulating the operation of the arithmetic device is stored.
Random access memory) or P-ROM (programmable read-only memory), and the system program includes a program for providing the arithmetic unit with the channel number detection function and channel number display function. is added.

The memory 14 is composed of a RAM, etc., and a part thereof is provided with a unit/channel information table 15 shown in FIG. 2.

The unit/channel information table 15 is
It is created by the channel number detection function of
In that main table, there are the inputs and outputs (22) 11-1~
Each arrangement address (unit address) of 11-n and each leading channel number of each of these input/output units 11-1 to 11-n are written in correspondence, and at the end of this main table, a table final code ( For example, FF
) is added.

Moreover, in each of the input/output units 11-1 to 11-n,
As shown in FIG. 3, in addition to the display 12, a gate array 16 and an input/output section 17 are provided.

The gate array 16 supplies the data and status sent from the CPU 13 to the input/output section 17, and receives the data or status of the input/output section 17 in response to a request from the CPU 3 and sends it to the CPU 3 side. It is configured to transmit data, and the data terminal D
O-D7 and address terminals AO, AI, A2. A9
, a chip selection terminal surface, and an input/output terminal I10.

In this case, the data terminals DO to D7 are connected to the data terminals DO to D7 of the CPU 13 provided on the PC main body 10 side via a data bus, and the gate array 16 is connected to the data terminals DO to D7 via the data terminals DO to D7. Data and status are received from the CPU 13.

The chip selection terminal C8 is an input/output unit selection terminal of the CPU 3 (this terminal is, for example, the input/output unit selection terminal of the CPU 1).
The CPU 13 supplies the channel selection terminal C317CI10 with the unit selection signal IOCH. At this time, the gate array 16 is turned on.

Also, an address terminal AO of the gate array 16.

AI, A2. A9 is connected to the CPU1 via an address bus.
3 address terminals AO・, AI, A2. Each is connected to A9. And in this case, address terminals AI, A2
is a terminal that receives channel selection data when it is output from the address terminals AI and A2 of the CPU 13, and the gate array 16 is set in the input/output unit 11 based on the channel selection data.
0 channels, that is, any one of the four channels set in the input/output section 17;
Address terminal A9 of the gate array 16 is connected to the CPU
Data/status information (
This is a terminal that receives a signal (“1” or °O” signal) when it is output, and the gate array 16 receives the signal supplied to the data terminal DO-D7 based on the signal supplied to the address terminal A9. Output the parallel signal as data or status information from the input/output terminal I/Q and supply it to the input/output section 17, or output data or status information from the input/output section 17 via the input/output terminal I/Q. It reads out and outputs it from the data terminal Do-D7.

Further, the address terminal AO of the gate array 16 is connected to a low bit/bit signal which specifies either the upper 8 bits or the lower 8 bits of the channel selected by the address terminals AI and A2 from the address terminal AO of the CPU 3.
This is a terminal that receives a high bit selection signal when it is output, and the gate array 16 operates based on the signal supplied to the address terminal AO from the data terminal Do-
The 8-bit parallel signal supplied to D7 is used as the upper 8 bits or the lower 8 bits of the 16 bits, and
The upper 8 bits or the lower 8 bits of the 16-bit parallel signal are read out from this input/output section 17.
This is outputted from the data terminals DO to D7.

Further, the input/output section 17 has four channels, each of which is composed of 16 bits, and the CPU which is supplied via the gate array 16
It controls an external device (not shown) based on the output (data, status) of the I3, or receives an output from a 7-inch device installed in this external device and sends it through the gate array 16. The data supplied to the CPUI 3 is as follows.

Further, the display device 12 receives display data (
This display data is displayed when the channel number (indicating the channel number) is supplied to the CPtJ13.
Write signal WRIT, segment on signal SEG from the side
and an AND gate 18 that is turned on when the I/Q unit selection signal IOCH is supplied, and 8-bit display data that is turned on when the AND gate 18 is turned on and output by the CPU 3. is taken in and displayed on the segment display (for example, a light-emitting 7-segment display) 20, and its reset terminal R
Display driver 1 that turns off the segment display 20 when a reset signal (“O” signal) is supplied to 3T
9.

In this case, the display driver 19 has its reset terminal R.
8T is pulled up to +5V via a resistor 22, and a switch 23 provided on the PC body 10@
When y is pressed, the CPU 13 outputs a reset signal, and the reset circuit 26 consisting of the OR gate 24 and the inverter 25 outputs the @θ'' signal.

In addition, the segment'' display 20 has two segments as shown in FIG.
The display driver 19 is also supplied with display data and lights up to display it in case of emergency.

Next, the operation of this embodiment will be explained with reference to the main flowchart shown in FIG. 5(A) and the channel number assignment routine shown in FIG. 5(B).

First, when the power switch of this PC is turned on, the CPU 13 in the PC main body 10 sequentially increments (or decrements) the I/Q unit selection signal 10CH while repeatedly outputting the segment on signal SEG and write signal WRITt in step STI. ) and each input/output unit) 11-1 to 11-n, the display units 12 are sequentially selected, and zero data (data for clearing the display) is supplied to these display units 12 to clear these displays. .

Next, in step ST2, the CPU 13 jumps to the channel number assignment routine 30, and in step ST3 of this routine 30, sets the value UN of the unit address counter in the CPU 3 to an initial value (for example, "l"), Set the value CN of channel color to “0”
’.

Next, in step ST4, the CPU 13 outputs the address data (or other data) corresponding to the value UN of the unit address counter, and performs the first input/output (22).
11-1 is supplied with the I/Q unit selection signal β number 10CH, and the information (data) necessary to read the data of the first channel is output from the address terminals AO to A2 and A9. 2) Read the data of the first channel of 11-1.

And here, if we get this data, the CPU
3, this input/output unit 11-1 is installed, this value is stored as the first channel number value of this input/output unit 11-1, and in the next step ST6, this value is stored as the first channel number value of this input/output unit 11-1. Read the data of the second channel.

If this data is obtained, the CPU 13 determines that the input/output unit 11-1 has at least two channels, and increments the value CN of the channel counter by 11'' in the next step ST7.

Next, the CPU 13 checks whether the input/output unit 11-1 has the third channel and the fourth channel in steps ST8, ST9 and steps 5TIO and STI1, and if it has the third channel, , the channel counter value CNt-"1" is incremented, and if there is a fourth channel, the channel counter value CN is further incremented by 11".

Next, in step STI 2, the CPU 13 writes the value UN of the unit address counter and the first channel number value stored in the above step ST5 to the first address 15-1 of the unit/channel information table 15 in the memory 14, and then writes the value UN of the unit address counter in step ST13. This input/output unit) 11
Check whether -1 is the final unit.

In this case, since this input/output unit (11-1) is not the final unit, the CPU 13
13, the process branches to step STI4, where the value UN of the unit address counter is incremented by "1", and the process returns to step ST4.

In addition, in the above explanation, the crowd crab knit 11-1
The explanation has been made assuming that the input/output unit H1-1 is equipped with 4 channels, but if this input/output unit H1-1 is equipped with only 1 channel, only channels 1 and 2, or only channels 1 and 2.3. Then, the CPU 3 performs steps ST6 and Sr1.

5TIO detects this and sets the value C of the channel counter.
The program branches to step STI 2 without incrementing N, and writes the current unit address counter value UN and the first channel number value to the first address 15-1 of the unit/channel information table 15.

Furthermore, in the above explanation, it is assumed that the input/output unit 11-1 is installed, but if this input/output unit 11-1 is not installed, the CPU
13 detects this in step ST4, and the step S
Since T5 to T12 are skipped, this input/output unit 11- is included in the unit/channel information table 15.
The value corresponding to 1 is not stored.

Next, when the operation of detecting the number of channels of the input/output unit 11-1 is completed, the CPU 13 detects the number of channels of the input/output unit 11-1.
1-2, the channel number detection operation is performed.

In this operation, it is first checked in step ST4 whether the input/output 22) 11-2 is installed, and if it is installed, the value CN of the channel counter is incremented in step ST5.
This is stored as the first channel number value, and the process proceeds to step ST6.

Sr1, this input/output unit 11 in STI O
-2 channel number detection is performed, and the value CN of the channel counter is incremented in steps ST7, Sr1, and STI1 in accordance with this detection result.

In this case, the channel counter initially holds the value of the number of channels of the input/output unit (11-1), so
When the operation of detecting the number of channels of the input/output unit 11-2 ends, the value obtained by integrating the number of channels of the input/output unit 11-1 and the number of channels of this input/output unit 11-2 is held in the channel counter. Ru.

Thereafter, in step STI 2, the CPU 3 stores the value UN of the unit address counter and the first channel number value of this input/output unit 11-2 stored in step ST5 as a unit/channel information channel.

The information of the input/output unit l-11-1 of the pull 15 is stored at the address 15-2 next to the address 15-1 where 1 is stored.

After this, the CPU 13 checks in step 5T13 whether this input/output unit 11-2 is the final unit or not, and returns to step ST4. The unit number and channel number of 11-n are determined and stored in the unit/channel information table 15 in sequence.

After writing the unit number and channel number of the final unit (input/output unit) 11-n into the unit/channel information table 15, in step 5T13, it is determined that this input/output unit 11-n is the final unit. After detecting the detection and writing the final code (value "FF") to the final address of the 22-bit channel information table 15, the process returns to step Sτ15 of the main flow, and the main program including the user program is executed.

Next, the CPU 13 checks whether a display on switch (not shown) has been turned on/off in step 5T16, and if it has been turned off, the process proceeds to step STI7.
output a reset signal to all input/output units) 1
The display devices 12 of 1-1 to 11-n are turned off. Further, if the display on switch is turned on, the CPU 13 stops outputting the reset signal in step STI 7, reads each unit number and channel number from the unit/channel information table 15, and sets this unit number to Output the corresponding I/Q unit selection signal 10CH, segment on signal SEG, and write signal WRIT for input/output)
11-n sequentially, and these input/output units) 11-
Each of the displays 12 from 1 to 11-n is caused to display its channel number.

Further, in step STI 6, when the display on switch is not turned on/on, the CPU 13
The program returns from step 5T16 to step 5T15 and executes the main program.

As described above, in this embodiment, the number of channels of each input/output unit (11-1 to 11-n) is detected prior to execution of the main program, and each input/output unit (22) is integrated by integrating the number of channels. ) 11-1 to 11-n
After that, calculate the first channel number value of , and then display these on the corresponding input/output units (11-1 to 11-n).
Since the channel number of each of the input/output units 11-1 to 11-n can be known just by glancing at each of these displays 12.

In addition, in this embodiment, the channel number is displayed on each display 12 only when the display on switch is turned on, so if this is normally turned off, the consumption of each display 12 is reduced. You can save electricity as much as possible. In this case, only when you don't know each channel number,
Just turn on the display on switch.

<Effects of the Invention> As explained above, according to the present invention, it is possible to know the channel number of an input/output unit even in a dark place without counting the number of rack devices or input/output units. Work efficiency can be improved.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing one embodiment of the present invention, and FIG.
The figure is a memory map showing an example of the configuration of the memory shown in Fig. 1, @3 causes is a detailed circuit diagram of the input/output unit shown in Fig. 1, and Fig. 4 is a front view of the PC body equipped with this input/output unit. , FIG. 5(A). (B) is a flowchart showing an example of the operation of the same embodiment, FIG. 6 is a front view showing an example of a PC system using a conventional input/output unit, and FIG. 7 is a program controller used in this system. FIG. 2 is a schematic diagram when unit numbers, channel numbers, etc. are displayed in correspondence using . 10...Program controller main body, 11-1 to 1
1-n...Input/output unit, 12...Display device, 13
...Channel number detection means, channel number display means (
CPU).

Claims (1)

[Claims] A channel for detecting the number of channels of each input/output unit in an input/output unit channel display device that is attached to the programmable controller body and displays the channel number of the input/output unit for matching between the programmable controller body and external equipment. An input/output unit comprising a channel number detection means and a channel number display means for displaying a channel number on a display provided in each input/output unit based on the detection result of the channel number detection means. Channel display device.