JP3399709B2 - Data extraction method in programmable controller and programmable controller - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller used in industrial equipment, etc.
The present invention relates to a sequence program in a U unit (PC main body), a data fetching method in a programmable controller that writes data in a device memory to a removable external storage medium, a programmable controller, and an external peripheral device.

[0002]

2. Description of the Related Art Conventionally, a sequence control device has been widely used as a control device such as an industrial machine. The sequence control device referred to here is, in the control of an industrial machine or the like, that the end of one control operation is confirmed and the next operation is selected according to the result, and the control is performed according to a predetermined order. Is a control device that performs control (sequence control) to sequentially advance each of the steps.

As a recent sequence control device, a programmable controller (hereinafter abbreviated as PC) capable of changing a sequence program has been used.

FIG. 20 shows a general structure of a conventional PC. The PC has a CPU unit 1 which is a main part of the PC, and an external peripheral device 2 is detachably connected to the CPU unit 1 by a cable 3.

The CPU unit 1 has a peripheral interface (hereinafter, referred to as a "peripheral interface" for transmitting / receiving data to / from the external peripheral device 2).
Peripheral I / F 4), a reception buffer 5 for temporarily saving the data transmitted from the external peripheral device 2, and a transmission buffer 6 for temporarily storing the data to be transmitted to the external peripheral device 2. , A sequence program memory 7 for storing a sequence program, and a device memory for storing device data for input / output signals necessary for ON / OFF control of a control target external device on the sequence program and a state of a device handling numerical values 8, a system ROM 9 storing a system program, and a data RAM 10 for temporarily storing data during execution by the CPU 12.
And various signal lines such as address signal lines and data signal lines 1
1 and a CPU 12 that executes a system program stored in the system ROM 9.

The external peripheral device 2 is like a programming console, has a keyboard 2a and a display unit 2b, and has a memory (external storage medium) 19 such as a floppy disk or an IC memory card detachably mounted. To be done.

Here, assuming that a sequence program including 10 steps from the 0th step to the 9th step is already stored in the sequence program memory 7, the sequence program for the 10 steps is stored in the PC.
A series of processes for reading from the CPU unit 1 to the external peripheral device 2 will be described.

When the user turns on the external peripheral device 2, a main menu as shown in FIG. 20 is displayed on the display unit 2b. In this main menu, as shown in FIG. 20, "PC read" is displayed in the first row and "device read" is displayed in the second row.

In order to read the sequence program from the CPU unit 1 to the external peripheral device 2, select the first-stage "PC read" from the main menu and press the RET key (return key).

As a result, as shown in FIG.
The PC read screen opens. In this screen, "Read start address [] step" is displayed in the first row,
"Read last address [] step" is displayed in the second row. In this example, the read start address is the 0th step and the final address is the 9th step. Therefore, the user sets "0" in the [] of the first row
] And set "9", and press RET.

As a result, the sequence program read request data creation routine shown in FIG. 23 is started. The sequence program read request data creation routine sets the data structure of the request for reading the sequence program in the sequence program memory 7 in the CPU unit 1 to the external peripheral device 2 in the transmission buffer (not shown) of the external peripheral device 2, This is a routine for executing a process of transmitting this to the CPU unit 1.

FIG. 24 exemplifies a data configuration set in the transmission buffer of the external peripheral device 2 when a read request for the sequence program is made. This is a data length storage area and a request code storage area for reading the sequence program. , An offset step value storage area and a read step number storage area. In this way, CP
In order to perform various communication processes between the CPU unit 1 and the external peripheral device 2, such as reading a sequence program from the U unit 1, the external peripheral device 2 sends the CPU unit 1 to the CPU unit 1.
The data structure issued toward the destination is called communication request data.

In the sequence program read request data creation routine, first, in step S501, the request code for sequence program read is set in the request code storage area of the transmission buffer of the external peripheral device 2. Here, the request code for reading the sequence program is previously set to "1".

Next, in step S502, the external peripheral device 2
Set the read first step in the offset step value storage area of the transmission buffer of. In this example, since the read first step is 0 step, as shown in FIG. 24, “0” is stored in the offset step value storage area.
Set.

Next, in step S503, the read step number is set in the read step number storage area of the transmission buffer of the external peripheral device 2. In this example, the read step number is 10 steps from the 0th step to the 9th step. Therefore, as shown in FIG. 24, "10" is set in the read step number storage area area.

Next, in step S504, the data length of the sequence program read request is set in the data length storage area of the transmission buffer of the external peripheral device 2. Since the sequence program read request is composed of the three data set in steps S501 to S503 described above, "3" is set in the data length storage area as shown in FIG.

At the next step S505, a data transmission interrupt signal is sent to the CPU unit 1, and at the next step S505.
At 506, the data of the above-mentioned transmission buffer of the external peripheral device 2 is transmitted to the CPU unit 1.

Next, the sequence program read processing in the CPU unit 1 will be described according to the main routine shown in FIG.

When the CPU unit 1 is powered on,
Its main routine is started. In this main routine, first, in step S601, the sequence program stored in the sequence program memory 7 is executed.

Next, in step S602, the external peripheral device 2
It is detected whether or not there is a data transmission interrupt signal. If there is a data transmission interrupt signal, the process proceeds to step S603, and communication request data reception processing from the external peripheral device 2 is executed.

Here, the description of the main routine is interrupted, and the communication request data receiving process in step S603 will be described with reference to the flowchart shown in FIG.

First, in step S701, the data length written in the data length storage area of the transmission buffer of the external peripheral device 2 is acquired by the peripheral I / F 4.

Next, in step S702, the peripheral I / F 4
The acquired data length is set to the address 0 of the reception buffer 5, and in the next step S703, it is written in each of the request code storage area, the offset step value storage area, and the read step number storage area of the transmission buffer of the external peripheral device 2. The peripheral I / F 4 obtains the stored data and sets them at the address 1 and later of the reception buffer 5.

Next, in step S704, it is determined whether or not the data has been received for the data length based on the data length set in the address 0 of the reception buffer 5, and this determination repeatedly executes step S703 for the data length. .

As a result, the data as shown in FIG. 27 is set in the reception buffer 5. in this case,
As shown in FIG. 27, the reception buffer 5 is provided with a data length area, a request code storage area, an offset step value storage area, and a read data length storage area, and external peripheral devices are provided in these areas. The data in the second transmission buffer is written as it is.

Now, let us return to the description of the main routine shown in FIG. When the data reception as described above is completed, next, in step S604, the type of the communication request data from the external peripheral device 2 is changed to +1 from the start address of the reception buffer 5, that is, the content of the request code storage area is changed. Judge by reading. The value is "1"
If so, it is determined that the type of communication request data is the sequence program read, and the process proceeds to step S605 to execute the sequence program read processing.

Next, the sequence program read processing in step 605 will be described with reference to the flow chart shown in FIG.

First, in step S801, the offset step value stored in the offset step value storage area of the reception buffer 5 and the read step number stored in the read step number storage area are read, and the sum of the two data is read. And the maximum step value of the sequence program memory 7 are compared.

If the sum of the offset step value and the number of read steps is smaller than the maximum step value of the sequence program memory 7, it is determined that both the offset step value and the number of read steps are normal values, and In step S802, it is checked whether the number of read steps stored in the read step number storage area of the reception buffer 5 is within the capacity of the transmission buffer 6.
29 shows an example of the sequence program stored in the sequence program memory 7.

If the number of read steps is smaller than the capacity of the transmission buffer 6, the read step number is a normal value.
Next, proceeding to step S803, processing for setting the sequence program for the designated number of steps from the designated offset step in the transmission buffer 6 is performed.

Here, the values of the offset step value storage area and the number of read steps stored in the read step number storage area of the reception buffer 5 are "0" and "10", respectively, so that they are exemplified in FIG. From the 0th step of the sequence program, the data for 10 steps is set in the read data storage area (see FIG. 30) of the transmission buffer 6.

As shown in FIG. 30, the transmission buffer 6 includes a data length storage area, a response code storage area, and a response propriety data storage area in which data indicating a normal response or an abnormal response is stored. It is composed of an offset step value storage area, a read step number storage area, and a read data storage area. This send buffer 6
The data capacity of is set to 1005 steps, for example,
A maximum of 100 can be issued by one sequence program read request.
Program reading in 0 steps is possible.

Next, in step S804, the offset step value stored in the offset step value area of the receiving buffer 5 and the read step number stored in the read step number storage area, that is, the offset step value and the read of the request packet. The step number is set in the offset step value storage area and the read step number storage area of the transmission buffer 6, respectively.

[0034] Then in step S805, the sets "0" indicating a normal response to the response propriety data storage area of the transmission buffer 6.

Next, in step S806, the read step number storage area of the transmission buffer 6 and the header length (fixed length).
The response data length is calculated from this, and it is set in the data length storage area of the transmission buffer 6. In this example, the number of read steps is 10 and the length of the header section is 4
The step is the response data length.

Generally, the data structure of the communication request data and the response data is roughly divided into a fixed data length portion and a variable data length portion. In the arrangement of these two sets of data, the part where the data length is fixed comes first, and then the variable part. Of these two sets of data, the part where the data length is fixed is called the header part because of the arrangement of the data, and the length is called the header length.

Next, in step S807, the response code for reading the sequence program is set in the response code storage area of the transmission buffer 6. In this example, the response code for reading the sequence program is "81".

Next, in step S808, the response data for reading the sequence program (see FIG. 30) in the transmission buffer 6 is transmitted from the peripheral I / F 4 to the external peripheral device 2 via the cable 3.

As described above, the CPU unit 1 issues it to the external peripheral device 2 in order to perform various communication processes between the CPU unit 1 and the external peripheral device 2, such as reading a sequence program from the CPU unit 1. The data structure is called communication response data.

If the sum of the offset step value and the number of read steps is larger than the maximum step value of the sequence program memory 7 in step S801,
It is determined that at least one of the offset step value and the read step number is an abnormal value, and step S809 is performed.
In step S809, "FFFFH" indicating an abnormal response is displayed in the response propriety data storage area of the transmission buffer 6.
Set.

Next, in step S810, the packet length (response data length) is set in the data length storage area of the transmission buffer 6, and then the process proceeds to steps S807 and 808. In this case as well, the sequence program read in the transmission buffer 6 is read. Response data from the peripheral I / F 4 to cable 3
To the external peripheral device 2 via.

Next, reading of data from the device memory will be described.

First, the case where the data read from the device memory is necessary will be described. F
A When the system is stopped due to some abnormality, in order to restart the system, the CPU during system operation
It is necessary to save the contents of the device memory of the unit 1, and at this time, the contents of the device memory are written to the removable memory.

In this conventional example, the user sets the device memory to the device No. during the sequence program. 0 to device No. It is assumed that 10 words up to 9 are used.

When the user turns on the external peripheral device 2, the main menu shown in FIG. 21 is displayed on the display unit 2a. C from the CPU unit 1 to the removable memory 19 via the external peripheral device 2
In order to transfer the data in the device memory of the PU unit 1, select the "read device" in the second row from the main menu and press the RET key.

As a result, as shown in FIG.
The device read screen opens. In this screen, 1
"Read first device No. []" is displayed in the second row, and "Read last device No. []" is displayed in the second row. In this example, the read head device No. Is "0", and the final device No. Is "9", the user sets "0" in [] of the first row and "9" in [] of the second row, and presses the RET key.

As a result, the device memory read request data creation routine shown in FIG. 32 is started.
In the device memory read request data creation routine, first, in step S901, the device memory read request code "2" is set in the request code storage area of the transmission buffer of the external peripheral device 2, as shown in FIG. set.

Subsequent steps S902-906
Is a step S502 in the sequence program read request data creation processing routine shown in FIG.
.. 506, the communication request data for reading the device memory is sent to the transmission buffer of the external peripheral device 2 (see FIG.
3)). This communication request data is composed of a data length, a request code, an offset address, and the number of read words.

The CPU unit 1 executes the main routine shown in FIG. 34 (the same as the main routine shown in FIG. 25), and in step S603, the request data reception process from the external peripheral device 2 is shown in FIG. 35, the data of the transmission buffer of the external peripheral device 2, that is, the data length, the request code, the offset address, and the number of read words are read. Write as it is.

Next, in step S604, if the write value in the request code storage area of the reception buffer 5 is "2", it is determined that the type of communication request data is device memory read, and the flow advances to step S605 to set the device. Executes memory read processing.

Next, the device memory read processing will be described with reference to the flow chart shown in FIG. Step S10 in the device memory read processing routine
01 to 1006 are steps S801 in the sequence program read processing routine shown in FIG.
.About.806, and in step S1007, "82" is set as the response code of the device memory read defined in advance in the address that is +1 from the head of the transmission buffer 6, that is, in the response code storage area.

FIG. 37 shows a data memory configuration example of the device memory 8.

Next, in step S1008, response data for reading the device memory in the transmission buffer 6 (see FIG. 38).
Response data is transmitted from the peripheral I / F 4 to the reception buffer (not shown) of the external peripheral device 2 via the cable 3.

In this way, the data in the device memory (see FIG. 37) in the response data received by the reception buffer of the external peripheral device 2 is written in the memory 19 loaded in the external peripheral device 2.

Further, JP-A-61-35653 discloses that
When the IC memory card is attached to the communication terminal device, an interrupt signal is generated in the MPU of the communication terminal device, the data held by the IC memory card is written to the RAM in the communication terminal device, or the data in the RAM in the communication terminal device is written. Writing data to an IC memory card is shown.

[0056]

In the conventional method of reading a sequence program described above, the CPU unit 1 is used.
Since the request data and the response data are exchanged between the external peripheral device 2 and the external peripheral device 2 using the cable 3, for example, when reading a sequence program at the time of maintenance and inspection, the maintenance person has a PC installed. To the site External peripheral equipment 2
Take the CPU unit 1 of the PC and the external peripheral device 2 with the cable 3 to read the sequence program to the external peripheral device 2, and bring the external peripheral device 2 back to the design room or the like. However, there is a problem that it is troublesome for the maintenance staff to carry the external peripheral device 2 to the site where the PC is installed.

When the data in the device memory during system operation is stored in the removable memory 19 such as the FD, the data in the device memory read from the CPU unit 1 is once written in the buffer memory in the external peripheral device 2 and then From the buffer memory in the external peripheral device 2 to F
In order to write data to the removable memory 19 such as D, reading / writing must be performed twice, and C
When the amount of data in the vise memory read from the PU unit 1 is large, there is a problem that the processing takes a considerable amount of time.

Further, the one disclosed in Japanese Patent Laid-Open No. 61-35653 is premised on writing all the data in the RAM in the communication terminal device to the IC memory card at all times. In order to read only the data of, the change of the read start address, the read data amount, etc. is not considered. In this communication terminal device, the read start address,
It is necessary to preset data for read control such as the number of read data. Read start address,
In order to change the amount of read data, it is necessary to change the read start address, the number of read data, etc. by connecting an external peripheral device to the communication terminal device.

Therefore, if the data transfer technique of the communication terminal device is diverted to the data reading in the programmable controller, the external peripheral device is brought to the site where the CPU unit is installed to change the read start address, the read amount, and the like. Must be done, and C
Since it is necessary for the maintenance staff to perform an operation of designating the read start address, the read amount, etc. for the PU unit, it is not improved that the external peripheral device is troublesome to carry to the site where the PC is installed.

The present invention has been made by paying attention to the above-mentioned problems, and the sequence program memory and the device memory in the programmable controller can be stored in the programmable controller without carrying the external peripheral equipment to the site where the PC is installed. An object of the present invention is to provide a data fetching method in a programmable controller capable of fetching only a required amount of data to an external storage medium that can be detached, and a programmable controller and an external peripheral device used for implementing the data fetching method.

[0061]

In order to achieve the above-mentioned object, a data fetching method in a programmable controller according to the present invention is a detachable external storage for data of a programmable controller for controlling a controlled device based on a sequence program. In the method of extracting to the medium, by registering the communication request data in which the type and area of the data reading are rewritable in the external storage medium and setting the external storage medium in the external storage medium driver provided in the programmable controller, the memory address of the external storage medium by generating an interrupt signal allocated to the memory address of the programmable controller, specifies the type and area of the data read by reading the communication request data of the outer <br/> unit storage medium Get information and the area
When it is determined that the specified information of No. 1 is a normal value, the data of the specified type and area is written to the external storage medium as communication response data, while the specified information of the area is written.
When it is determined that the value is an abnormal value, the data indicating the abnormality is written in the external storage medium.

Therefore, in the data fetching method in the programmable controller according to the present invention, the communication request data designating the type and area of data reading is rewritably registered in the external storage medium by using the external peripheral device, and the external request is made. The storage medium is set in the external storage medium driver of the programmable controller. When the external storage medium is set in the external storage medium driver of the programmable controller, an interrupt signal is generated, the memory address of the external storage medium is assigned to the memory address of the programmable controller, and the programmable controller is registered in the external storage medium. By reading the communication request data, the data read type and the area designation information are acquired, and the data of the designated (requested) type and area is written in the external storage medium as the communication response data.

As a result, only by setting the external storage medium in the external storage medium driver of the programmable controller, the data of the sequence program memory and the device memory in the programmable controller can be taken out to the removable external storage medium as much as necessary. .

In the data fetching method in the programmable controller according to the next invention, the communication request data is
It has a request code that identifies the sequence program read and device memory data read as data that specifies the type of data read, and the sequence program read first step or device memory read first as the data that specifies the data read area. It includes the address and the number of read steps of the sequence program or the number of read words of the device memory.

Therefore, in this data fetching method, the read data can be selectively designated to either the sequence program or the data in the device memory by the request code, and the read start step of the sequence program or the read start address of the device memory, By specifying the number of read steps of the sequence program or the number of read words of the device memory, it is possible to take out the necessary amount of data of the sequence program or device memory to the external storage medium.

A programmable controller according to the next invention is a programmable controller for controlling a device to be controlled based on a sequence program, wherein an interrupt circuit for generating an interrupt signal by mounting a removable external storage medium, and the external circuit by the interrupt signal. read out the memory address of the storage medium and the address allocation means for allocating the memory addresses of the programmable controller, the communication request data registered in the external storage medium in the memory address allocated by the address allocation unit
Information to specify the type of data read and the area
The reading means to be obtained and the specified information of the area are normal values.
Data of the specified type and area,
Writing data into the external storage medium as communication response data , and the writing means is a finger of the area.
When it is determined that the constant information is an abnormal value, the data indicating the abnormality is written in the external storage medium.

Therefore, in the programmable controller according to the present invention, when the external storage medium is mounted, the interrupt circuit generates an interrupt signal, and the address assigning means changes the memory address of the external storage medium to the memory address of the programmable controller by the interrupt signal. Assign to.
As a result, the programmable controller can read and write data in the external storage medium, and the programmable controller reads the communication request data registered in advance in the external storage medium by the reading means.
The type and area of data read are recognized, and the communication response data is written in the external storage medium by the writing means in accordance with the type and area of data read specified by this communication request data.

As a result, the data of the device memory of the required number of sequence programs or the required number of words designated in the area is written to the external storage medium, the sequence program is read, and the contents of the device memory are saved.

In the programmable controller according to the next invention, the communication request data has a request code for identifying a sequence program read and a device memory data read as data for designating a data read type, and a data read area. As the data for specifying, the read start step of the sequence program or the read start address of the device memory and the number of read steps of the sequence program or the read word number of the device memory are included.

Therefore, in this programmable controller, the read data can be selectively designated as either the sequence program or the data in the device memory by the request code, and the read start step of the sequence program or the read start address of the device memory,
By specifying the number of read steps of the sequence program or the number of read words of the device memory, it is possible to take out the necessary amount of data of the sequence program or device memory to the external storage medium.

A programmable controller according to the next invention has an external storage medium driver to which an external storage medium is detachably attached, and outputs an ON signal when the external storage medium is attached to the external storage medium driver. A switch is provided, and the interrupt circuit generates an interrupt signal by taking in an ON signal output from the switch.

Therefore, in this programmable controller, the external storage medium is attached to the external storage medium driver, and the switch outputs the ON signal, whereby the interrupt circuit generates the interrupt signal.

[0073]

[0074]

[0075]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. In the embodiment of the present invention, the same components as those in the above-mentioned conventional example are designated by the same reference numerals as those in the above-described conventional example, and the description thereof will be omitted.

[Embodiment 1] FIG. 1 shows a schematic configuration of a programmable controller according to the present invention.

In the CPU unit 1, the IC memory card driver 20 into which the IC memory card 17, which is an external storage medium, is detachably mounted, and the start address of the IC memory card 17 are set in a predetermined memory map of the entire RAM of the CPU unit 1. An address allocating means 13 for allocating to an address, for example, 10000, and an interrupt circuit 14 for newly generating an interrupt signal when the IC memory card 17 is attached to the CPU unit 1 are newly provided, and the interrupt circuit 14 generates an interrupt. The signal is directly input to the CPU 12 by the interrupt signal line 18.

As shown in FIG. 2, the IC memory card driver 20 is provided with a limit switch 20a.
An ON signal is generated when the C memory card 17 is attached. The interrupt circuit 14 generates an interrupt signal by taking in this ON signal. The system program stored in the system ROM 9 has a portion for writing the data in the sequence program memory 7 into the IC memory card 17.

The external peripheral device 2 is the IC memory card 17
Is a removably mounted type, and data registration means 15 for registering communication request data such as sequence program read to the IC memory card 17, and communication response data such as sequence program read from the IC memory card 17. It has a data reading means 16.

Although not shown in the figure, the external peripheral device 2 has an IC memory card registration buffer, and this buffer indicates the presence or absence of request data, as shown in FIG. A flag storage area where flags are stored,
It includes a data length storage area, a request code storage area, an offset step value storage area, and a read step number storage area.

Here, assuming that a sequence program having a length of 10 steps from the 0th step to the 9th step is stored in the sequence program memory 7, the sequence program having a length of 10 steps is stored in the CP of the PC.
A series of processes for reading from the U unit 1 to the IC memory card 17 will be described.

When the user turns on the power of the external peripheral device 2, the main menu shown in FIG. 4 is displayed on the display unit 2a. This main menu has
The items of "PC read registration to IC memory card", "PC read from IC memory card", and "device memory read to IC memory card" are displayed in the first to third rows.

From the main menu, select the item "PC read registration to IC memory card" in the first row and click RE.
Press the T key. This opens the PC read registration screen for the IC memory card as shown in FIG. In this screen, the first row is the "read start address [] step", and the second row is the "read last address [] step".
"Step" is displayed.

In the case of this embodiment, the read start address is 0.
Since this is the 9th step and the final address is the 9th step, the user sets "0" in the first row [] and "9" in the second row [], and presses the RET key. To do.

As a result, the sequence program read request data creation processing routine shown in FIG. 6 is started, and the communication request data for reading the sequence program is created.

In the sequence program read request data creation processing routine, first, in step S11, the request code "1" representing the sequence program read is set in the request code storage area of the IC memory card registration buffer of the external peripheral device 2.

Next, in step S12, the read head step is set in the offset step value storage area of the IC memory card registration buffer. In the case of the present embodiment, since the read first step is 0 step, "0" is set in this area . In step S13 in the next, to set the number of read steps in the read step number storage area of the IC memory card registration buffer. In the case of the present embodiment, the number of read steps is 10 steps from the 0th step to the 9th step, so 10 is set in this area.

Next, in step S14, the data length of the sequence program read request is set in the data length storage area of the IC memory card registration buffer. In this embodiment, the sequence program read request because it is composed of three data sets in the above-described step S. 11 to S 13, sets "3" to the data length storage area.

Next, in step S15, "1111", "2222" and "3333" are set in the flag storage area. The set value in the flag storage area indicates that the communication request data has been set in the IC memory card, and this is defined as a request data present flag.

Next, in step S16, the processing for registering the communication request data in the IC memory card 17 is executed.

FIG. 7 shows the IC in step S16 described above.
The routine for the communication request data registration processing to the memory card is shown. In this registration processing routine, first, step S
In step 21, the drive designation is designated as the IC memory card designation, and in the next step S22, communication program request data for sequence program read that has already been set in the IC memory card registration buffer is set in order from the 0th address of the IC memory card 17. .

This communication request data registration processing routine realizes the communication request data registration means 15 for the IC memory card.

Next, the operation of the CPU unit 1 in the process of reading the sequence program to the IC memory card will be described according to the main routine of the programmable controller shown in FIG.

When the CPU unit 1 is powered on,
The main routine of this is started. Since steps S31 to S35 in this main routine are the same as steps S601 to S605 in the main routine of the conventional programmable controller shown in FIG. 25, description thereof will be omitted.

[0095] In the programmable controller of the main routine of the CPU unit 1 according to the present invention, the step S3 6 to 40 have been added, in step S3 6,
The presence / absence of an interrupt signal from the interrupt circuit 14 of the CPU unit 1 is checked. If there is an interrupt signal from the interrupt circuit 14, the process proceeds to the next step S37, and the address allocation process of the IC memory card is performed.

FIG. 9 shows the address allocation processing routine of the IC memory card in step S37. In this address allocation processing routine, first, step S5
In step 1, the address allocating means 13 is instructed to "use address 10000 of the entire RAM memory as the start address of the IC memory card", and in the next step S52, the address allocating means 13 is set as shown in FIG. By connecting the address control line 21 to the IC memory card,
Processing for displaying the address as address 0 of the IC memory card is performed.

FIG. 10 shows the entire memory map of the RAM of the CPU unit 1. By using the address assigning means 13, the address 10000 is set to 0 of the IC memory card 17.
By showing the address, the CPU unit 1
It becomes possible to read the contents of the memory card 17 and write data to the IC memory card 17.

Next, in step S38 of the main routine, it is checked whether or not communication request data exists in the IC memory card 17, the contents of addresses 0 to 2 of the IC memory card 17, that is, the CPU unit 1A of FIG. It is determined whether or not the contents of the entire address 10000 to 10002 of the RAM are “1111”, “2222”, and “3333”.

Total address 10000 to 100
The contents of address 02 are "1111,""2222," and "3.
If it is 333 ", it is determined that there is communication request data in the IC memory card 17, and the process proceeds to step S39. In step S39, the type of communication request is the address 4 of the IC memory card 17 and the RAM of the CPU unit 1A. It is judged by reading the value of the entire address 10004. If the value is "1", it is judged that the type of communication request data is the sequence program read, and step S40
Then, the sequence program reading process for the IC memory card 17 is executed.

Here, the memory contents of the IC memory card 17 will be described with reference to FIG. The IC memory card 17 has a communication identification flag storage area in which a flag indicating whether the communication request data or the communication response data is stored, a data length storage area, a request code storage area, and a read offset step value. Storage area,
It has a read step number storage area.

FIG. 12 shows I in step S40 described above.
8 shows a sequence program read processing routine for the C memory card 17. In this routine, first, in step S61, I shown in FIG.
The offset step value, which is the contents of the read offset step value storage area indicated by the total address 10005 of the RAM of the CPU unit 1, and the read step number storage area indicated by the address 10006. The number of read steps, which is the content of, is read, and the sum of the two data and the maximum step value of the sequence program memory 7 are compared in magnitude.

If the sum of the offset step value and the read step is smaller than the maximum step value of the sequence program memory 7, both the offset step value and the read step number are normal values and the process proceeds to step S62.

In step S62, the size of the read step number stored in the read step number storage area of the IC memory card 17 shown in FIG. 11A and the memory capacity of the IC memory card 17 are compared. , if the number of read steps is smaller than the memory capacity of the IC memory card 17, processing proceeds as the number of read steps is normal value to the next step S 6 3, the sequence program I
The writing process to the C memory card 17 is performed.

In this case, the offset step value stored in the read offset step value storage area of the IC memory card 17 and the read step number stored in the read step number storage area are "0",
Since it is "10", the sequence program data corresponding to the designated step, that is, 10 steps from the 0th step (designated offset step) of the sequence program written in the sequence program memory 7 is I
Address 8 of the C memory card 17 (see FIG. 11B), that is, the entire address 1000 of the RAM of the CPU unit 1.
Set in the read data area allocated from address 8.

Next, in step S64, addresses 5 and 6 of the IC memory card 17 shown in FIG.
That is, the entire address 100 of the RAM of the CPU unit 1
The offset step value and the number of read steps at the address 05 and the address 10006 are set to R of the CPU unit 1A.
By setting the total addresses of the AM at addresses 10006 and 10007, the offset step value is set at address 6 of the IC memory card 17, and the number of read steps is set at address 7.

In the next step S65, "5" of the IC memory card 17 is set to the address 5 of the IC memory card 17, that is, the whole address 10005 of the RAM of the CPU unit 1A to set the address 5 of the IC memory card 17 to the normal address. “0” indicating a normal response is set to 0.

Next, in step S66, the response data length is calculated from the number of read steps and the header length (fixed length), and the response data length is set to the third address of the IC memory card 17, that is, C.
It is set to the entire address 10003 of the RAM of the PU unit 1. In this embodiment, the number of read steps is 10
The length of the header part is added to the step, 4 steps are added, and 14 steps are the response data length.

Next, in step S67, the response code for reading the sequence program is set to 4 in the IC memory card 17.
The address is set to the total address 10004 of the RAM of the CPU unit 1. Taken here to be "81" the response code sequence program read.

Next, in step S68, addresses 0 to 2 of the IC memory card 17, that is, the RAM of the CPU unit 1
The response data present flag is set at the total address 10000 to 10002 of the above. In this embodiment, the response data presence flag is set to "AAAAH", "BBBBH",
It is referred to as "CCCCH". H represents a hexadecimal number.

FIG. 11C shows the memory contents of the IC memory card 17 after the series of data write processing described above has been performed.

If the sum of the offset step value and the number of read steps is larger than the maximum step value of the sequence program memory 7 in step S61, at least one of the offset step value and the number of read steps is set. It is determined to be an abnormal value and step S69
In step S69, "FFFFH" indicating an abnormal response is set in the address 5 of the IC memory card 17.

Next, in step S70, the packet length (response data length) is set in the address 3 of the IC memory card 17, and thereafter, the process proceeds to steps S67 and 68.

After the IC memory card 17 in which the data has been written as described above is attached to the external peripheral device 2, the user selects "IC memory" in the second row of the main menu of the external peripheral device 2 shown in FIG. When the "PC read from card" item is selected and the RET key is pressed, the communication response data read processing routine from the IC memory card shown in FIG. 13 is started.

In this communication response data read processing routine, first, in step S71, 0 of the IC memory card 17 is read.
The contents of the address 2 are read out, and in the next step S72, the contents read out are "AAAAH", "BBBBH", "C".
It is checked whether or not it is "CCCH".
If "H", "BBBBH", and "CCCCH",
Since the communication response data exists in the IC memory card 17, the process proceeds to step S73 in this case, and the data after the address 2 of the IC memory card 17 is stored in the reception buffer (not shown) of the external peripheral device 2. set.

By this communication response data reading processing routine, the response data reading means 16 from the IC memory card
Is realized.

After that, the external peripheral device 2 reads the sequence program from the reception buffer and displays the sequence program.

According to the above configuration, the external peripheral device 2
By setting the communication request data for reading the sequence program in the IC memory card 17, the data such as the read start address can be changed in the design room in which the external peripheral device 2 is installed.
The person in charge of maintenance only needs to bring the IC memory card 17 to the site where the IC is installed.
Only by mounting the memory card 17 on the CPU unit 1, the required sequence program can be read.

Next, during the sequence program, the device memory is set to the device No. 0 to device No. 1 up to 9
A series of processes for transferring the data of 10 words to the IC memory card 17 assuming that 0 words are used will be described.

When the user turns on the power of the external peripheral device 2, the main menu shown in FIG. 4 is displayed on the display unit 2a. From the main menu, select the item "read device memory from IC memory card" on the third row and press the RET key.

As a result, as shown in FIG.
The screen for reading the device memory to the IC memory card opens. In this screen, "reading head device No. []" is displayed in the first row, and "reading last device No. []" is displayed in the second row. In this embodiment, the first device No. Is "0", and the final device No.
Is “9”, the user sets “0” in the first row [] and sets “9” in the second row [], and R
Press the ET key.

As a result, the device memory read request data creation processing routine shown in FIG. 15 is started. In the device memory read request data creation processing routine, first in step S81, in the request code storage area of the IC memory card registration buffer of the external peripheral device 2,
As shown in FIG. 16, the device memory read request code "2" is set.

Steps S82 to S86 after this are
This is equivalent to steps S12 to S16 of FIG. 6, and communication request data for reading the device memory is created in the IC memory card registration buffer (see FIG. 16) of the external peripheral device 2. This communication request data is composed of a data length, a request code, an offset address, and the number of read words. As a result, device memory read request data (communication request data) is created, and this communication request data is processed by the communication request data registration processing routine shown in FIG. 7 as shown in FIG. It is registered in the IC memory card 17.

Next, the operation of the CPU unit 1 side in the process of setting the contents of the device memory 8 in the IC memory card 17 will be described.

When power is turned on to the CPU unit 1, FIG.
The main routine shown in 8 is started. FIG.
8 is the same as the main routine shown in FIG. 8. Here, when the communication request is a device read communication request, the device memory read processing is performed.

Therefore, in step S39, the fourth address of the IC memory card 17, that is, the RAM of the CPU unit 1
Of the entire address 10004 of "1" is "2", and if it is "2", it is determined that the type of communication request data is device memory read, and in step S41, the device memory read for the IC memory card 17 Execute the process.

FIG. 19 shows the device memory read processing routine in step S41. Steps S91 to 9 in this device memory read processing routine
6, 98 to 100 are steps S61 to S61 in the sequence program read processing routine shown in FIG.
66, 68 to 70, and in step S97,
As shown in FIG. 17B, the response code “82” for reading the device memory is set to 4 in the IC memory card 17.
The address is set to the total address 10004 of the RAM of the CPU unit 1.

FIG. 17C shows the memory contents of the IC memory card 17 after the series of data writing processing described above has been performed.

Since the data in the device memory 8 can be read into the IC memory card 17 as described above,
The maintenance staff pulls out the IC memory card 17 whose data has been registered from the CPU unit 1 and stores the IC memory card 17, and the work of sucking up the data in the device memory 8 is completed.

[0129]

As is apparent from the above description, in the data fetching method in the programmable controller according to the present invention, the communication request data designating the type and area of data reading is registered in advance in the external storage medium, and By setting the external storage medium in the external storage medium driver of the programmable controller, the data of the sequence program memory and device memory in the programmable controller can be taken out to the removable external storage medium only for the required amount, so that the external peripheral device Does not need to be carried to the site where the PC is installed, and there is no need to set the data read area such as the first step and the number of read steps in the programmable controller (CPU unit) in advance. It will be reduced.

Further, since the device memory data is directly transferred from the programmable controller to the external storage medium without passing through the external peripheral device, the time taken for the data to be downloaded from the programmable controller of the device memory can be considerably shortened as compared with the conventional case. .

In the data fetching method in the programmable controller according to the next invention, the read data can be selectively designated as either the sequence program or the data in the device memory by the request code. By specifying the start address and the number of read steps of the sequence program or the number of read words of the device memory, the required amount of the sequence program or the data of the device memory can be taken out to the external storage medium. Data of the sequence program memory and device memory in the programmable controller can be taken out to an external storage medium that can be detached only as needed, without having to carry it to the site. Advance the top step, such as a read step number, because there is no need to set the data read-out region to the programmable controller, correspondingly, the maintenance personnel burden is reduced.

In the programmable controller according to the next invention, the external storage medium preregistered with the communication request data designating the type and area of data reading is set in the external storage medium driver of the programmable controller. Since the data in the sequence program memory and device memory can be taken out to the removable external storage medium only as much as necessary, it is not necessary to carry the external peripheral device to the site where the PC is installed, and the first step and the reading step in advance. It is not necessary to set the data read area such as the number in the programmable controller (CPU unit), and the burden on the maintenance staff is reduced accordingly.

Further, since the device memory data is directly transferred from the programmable controller to the external storage medium without passing through the external peripheral equipment, the time taken for the data to be taken from the programmable controller of the device memory can be considerably shortened as compared with the conventional case. .

In the programmable controller according to the next invention, the read data can be selectively designated to either the sequence program or the data of the device memory by the request code, and the read start step of the sequence program or the read start address of the device memory can be specified. By specifying the number of read steps of the sequence program or the number of read words of the device memory, the required amount of the sequence program or the data of the device memory can be taken out to the external storage medium. Therefore, the external peripheral device is a PC. Data of the sequence program memory and device memory in the programmable controller can be taken out to an external storage medium that can be detached only as needed, without having to carry it to the site.
Further, since it is not necessary to set the data read area such as the first step and the number of read steps in the programmable controller in advance, the burden on the maintenance staff can be reduced accordingly.

In the programmable controller according to the next invention, when the external storage medium is attached to the external storage medium driver, the switch outputs an ON signal,
Since the interrupt circuit generates an interrupt signal, if the external storage medium is attached to the external storage medium driver, the interrupt signal is reliably generated and the data fetching process is performed.

[0136]

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a programmable controller according to the present invention.

FIG. 2 is a schematic diagram of a driver of an IC memory card used in the programmable controller according to the present invention.

FIG. 3 is an explanatory diagram showing a request data structure of a sequence program reading process in the programmable controller according to the present invention.

FIG. 4 is a diagram showing a screen of a main menu of an external peripheral device used in the programmable controller according to the present invention.

FIG. 5 is a diagram showing a screen for reading a sequence program of an external peripheral device used in the programmable controller according to the present invention.

FIG. 6 is a flowchart showing a sequence program read request data creation processing routine in an external peripheral device used in the programmable controller according to the present invention.

FIG. 7 is a flowchart showing a communication request data registration processing routine to an IC memory card in an external peripheral device used in the programmable controller according to the present invention.

FIG. 8 is a flowchart showing a main routine in the programmable controller (CPU unit) according to the present invention.

FIG. 9 is a flowchart showing an address allocation processing routine of an IC memory card in the programmable controller according to the present invention.

FIG. 10 is a diagram showing a memory map of a RAM of the programmable controller according to the present invention.

FIG. 11A shows the contents of the IC memory card in which the request data for the sequence program read processing is registered,
(B) is a diagram showing the contents of the IC memory card during the sequence program reading process, and (c) is a diagram showing the contents of the IC memory card after the completion of the sequence program reading process.

FIG. 12 is a flowchart showing a sequence program read processing routine in the programmable controller according to the present invention.

FIG. 13 is a flowchart showing a read processing routine of communication response data from an IC memory card in an external peripheral device used in the programmable controller according to the present invention.

FIG. 14 is a diagram showing a screen for reading device memory of an external peripheral device in the programmable controller according to the present invention.

FIG. 15 is a flowchart showing a device memory read request data creation processing routine in an external peripheral device in the programmable controller according to the present invention.

FIG. 16 is a diagram showing a request data structure of a device memory reading process in the programmable controller according to the present invention.

FIG. 17A is a content of an IC memory card in which request data for device memory read processing is registered, FIG. 17B is a content of an IC memory card in the middle of device memory read processing, and FIG. It is a figure which shows the content of each IC memory card after the completion of device memory reading.

FIG. 18 is a flowchart showing a main routine in the programmable controller according to the present invention.

FIG. 19 is a flowchart showing a device memory read processing routine in the programmable controller according to the present invention.

FIG. 20 is a block diagram of a conventional programmable controller.

FIG. 21 is a diagram showing a screen of a main menu of an external peripheral device in a conventional example.

FIG. 22 is a diagram showing a screen for reading a sequence program of an external peripheral device in a conventional example.

FIG. 23 is a flowchart showing a sequence program read request data creation processing routine in an external peripheral device in a conventional example.

FIG. 24 is a diagram showing a state in which sequence program read request data is set in a transmission buffer of an external peripheral device.

FIG. 25 is a flowchart showing a main routine of a programmable controller in a conventional example.

FIG. 26 is a flowchart showing a request data reception processing routine from an external peripheral device in a conventional example.

FIG. 27 is a diagram showing a state in which request data for reading a sequence program is set in a reception buffer of the programmable controller.

FIG. 28 is a flowchart showing a sequence program read processing routine in a conventional example.

FIG. 29 is a diagram showing an example of a sequence program stored in a sequence program memory.

FIG. 30 is a diagram showing a state in which response data for reading a sequence program is set in a transmission buffer of a programmable controller.

FIG. 31 is a diagram showing a screen for reading a device memory of an external peripheral device in a conventional example.

FIG. 32 is a flowchart showing a device memory read request data creation processing routine in an external peripheral device in a conventional example.

FIG. 33 is a diagram showing a state in which vice memory read request data is set in a transmission buffer of an external peripheral device.

FIG. 34 is a flowchart showing a main routine of a programmable controller in a conventional example.

FIG. 35 is a diagram showing a state in which request data for device memory reading is set in a reception buffer of the programmable controller.

FIG. 36 is a flowchart showing a device memory read processing routine in a conventional example.

FIG. 37 is a diagram showing the contents of a device memory.

FIG. 38 is a diagram showing a state in which response data of device memory read is set in a transmission buffer of the programmable controller.

[Explanation of symbols]

1 CPU unit, 2 external peripheral device, 3 cable, 4 peripheral interface, 5 receive buffer, 6
Transmission buffer, 7 Sequence program memory, 8
Device memory, 9 system ROM, 10 data R
AM, 11 various signal lines, 12 CPU, 13 address allocating means, 14 interrupt circuit, 15 request data registration means, 16 response data reading means, 17 IC memory card, 18 interrupt signal line, 19 memory, 20 I
C card driver, 21 address control line

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G05B 19/05 G06K 17/00 G06K 19/00

Claims (5)

(57) [Claims] 1. A method of retrieving data of a programmable controller for controlling a controlled device based on a sequence program into a removable external storage medium, wherein communication request data designating a type and area of data reading is rewritten in the external storage medium. capable registered, by the external storage medium is set in the external storage medium driver provided in the programmable controller, and assigned to generate an interrupt signal to a memory address of the external storage medium to the memory address of the programmable controller, wherein acquires designation information of the type and area of the data read by reading the communication request data in the external storage medium, designation of the area
When it is determined that the information is a normal value, the data of the designated type and area is written to the external storage medium as the communication response data, while the designated information of the area is abnormal.
A data extraction method in a programmable controller, characterized in that, when it is determined that the value is a value, data indicating an abnormality is written in the external storage medium. 2. The communication request data has a request code for identifying read of a sequence program and data read of a device memory as data for designating a type of data read, and sequence as data for designating a data read area. 2. The data fetching method in a programmable controller according to claim 1, wherein the method includes a program read start step or a device memory read start address, and a sequence program read step number or a device memory read word number. 3. A programmable controller for controlling a control target device based on a sequence program, wherein an interrupt circuit for generating an interrupt signal when a removable external storage medium is attached, and a memory address of the external storage medium by the interrupt signal are provided. an address assignment means for assigning the memory addresses of the programmable controller, said external storage medium to the registered communication request read <br/> data to the memory address allocated by the address allocation unit by tying the data read type And designation information of the area
Information to read information and the specified information of the area is normal
If it is determined to be a value, the specified type and area
Is written in the external storage medium as communication response data.
And a writing means for burn them, said writing means, said territory
A programmable controller, characterized in that, when it is determined that the area designation information is an abnormal value, data indicating that the area is abnormal is written to the external storage medium. 4. The communication request data has a request code for identifying read of a sequence program and data read of a device memory as data for designating a data read type, and a sequence as data for designating a data read area. 4. The programmable controller according to claim 3, wherein the programmable controller includes a program read start step or a device memory read start address, and a sequence program read step number or a device memory read word number. 5. An external storage medium driver to which an external storage medium is detachably mounted, wherein the external storage medium driver is provided with a switch that outputs an ON signal when the external storage medium is mounted, The programmable controller according to claim 3, wherein the interrupt circuit generates an interrupt signal by taking in an ON signal output from the switch.