JPS62117004A - Sequence processor - Google Patents

Abstract

PURPOSE:To perform the sequence arithmetic processing by using a sequence arithmetic processing means to write and read data to and out of a common memory for each bit. CONSTITUTION:An input/output means 400 performs the writing and reading actions of data to a storing means 1000. While a sequence processing means 500 performs the writing and reading actions to the means 1000 via a selection means 600. Here the data of a single bit is valid at a specific position of the parallel data in terms of the means 500. The means 500 can perform the writing or reading action in a virtual series data style since the sequence arithmetic processing is originally equal to the processing of the series data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a sequence processing device, and more specifically, to a sequence processing device that performs sequence calculation processing on input information and outputs the resultant data in order to increase the calculation speed.

[Prior Art] Conventionally, as this type of sequence processing device, one that performs parallel data processing is known.

The $2 factor is an example of a conventional sequence processing device, and FIGS. 3 and 4 show examples of its processing. Here, as shown in FIG. 3, the first input card installed in the device The case where the data of the j-th bit of is outputted to the sentence bit of the th output card will be exemplified.

The input/output microcomputer 4, which serves as the input section, writes parallel data from the input card 2 to the common memory 1 as parallel data via the data bus driver 8. At this time, the address information and memory selection signal of the common memory 1 are , are transmitted from the input/output microcomputer 4 to the common memory 1 via the address bus driver 6.

The sequence processing microcomputer 5 as a sequence processing section specifies the address of the common memory l via the address bus driver 7, and reads input information as parallel data via the data bus driver 11. The sequence calculation processing microcomputer 5 performs sequence calculation processing on this data, and then writes the calculation result as parallel data to the common memory l via the bus driver 10. At this time, the address of the common memory l is set to the address It is selected by the sequence calculation processing microcomputer 5 via the bus driver 7.

The input/output microcomputer 4 reads the output data from the common memory 1 as parallel data via the data bus driver 9 and outputs it to the output card 3.

In FIG. 2, 21, 22 and 23 are the CPU, ROM and RAM of the microcomputer 4, respectively, and 24, 25 and 26 are the CPU, ROM and RAM of the microcomputer 5, respectively.

Also, A.

D and C5 are the address terminal, data terminal and chip select terminal of the common memory I.

[Problems to be solved by the invention] By the way, in such a conventional sequence processing device,
Since parallel data processing is performed during sequence calculation processing, there is a problem that the processing becomes complicated and the processing time becomes long.

Specifically, as shown in FIG. 4, the data of the i-th input card 2 written to the common memory l by the data input/output microcomputer 4 is processed as follows.

The input parallel data is 1NDTi, the input bit to be referenced is BiTj, the parallel data after sequence operation processing is 0υTDTk, the output bit to be rewritten is BiTM, and the intermediate operation results are WORKDI, WORKD2, W.
In the process of ORKD3 tot 6 and FIG.

WORKD1 = 1NDTi to old Tj (Step PI) WORKD2 = Shift (WORKDI)
(Step P2) is performed. Note that the process in step P2 is 0-order indicating that data at least at the position of bit j of the operation result WORKDI is shifted to the position of bit l.

WORKD3= 0UTDTk A BiTT (X Te, y 7' P3) OUT[1Tk=WORKD2VW
ORKI] 3 (step P4), that is, in the conventional device, the above 4 steps are performed in order to perform the process shown in the second diagram.
A problem arises in that step-by-step calculations must be performed, resulting in a reduction in the processing speed of the device.

[Means for solving the problem] The present invention solves the problem, and the data input/output means accesses the memory as parallel data, and the sequence operation processing means accesses the memory as serial data (in bit units). An object of the present invention is to provide a sequence processing device that can perform high-speed processing by accessing the sequence data.

In order to achieve this object, the present invention, as shown in FIG. 1, includes an input/output means 400 for inputting and outputting parallel data;
Storage means 1000 stores information constituting parallel data supplied from input/output means 400 in correspondence with bit positions on the parallel data, and sequence processing means 500 performs sequence calculation processing on specific bit positions of the parallel data. , storage means 1000 and sequence processing means 5
00 and selecting means 800 for selecting or distributing data at a predetermined bit position of the parallel data.

[Function] That is, in the present invention, the input/output means 400 is the storage means 1
000, while the sequence processing means 500 writes to and reads from the storage means 1000 via the selection means 600. At this time, when viewed from the sequence processing means 500, the data is parallel. One bit of data at a specific position of data becomes valid. Since sequence arithmetic processing is essentially serial data processing, the sequence processing means 500 is designed to be able to write to or read from memory in the form of apparent superposition column data.

[Example] Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 5 shows an example of the configuration of the apparatus of the present invention, in which corresponding parts are given the same reference numerals as to parts that can be configured in the same manner as in the prior art. 104 and 105 are an input/output unit and a sequence processing unit, respectively, and can be in the form of a microcomputer. In the input/output unit 104,
121, 122, and 123 are a CPU for performing input/output processing, and an RO that stores the processing procedures, etc.
M and a working RAM. In the sequence processing unit 105, 124, 125 and 12B are respectively a CPU that executes various sequence calculation processing procedures including the processing procedure shown in FIG. 7, and a ROM that stores a program for the CPU 124 to execute those processing procedures. ,
and a RAM having a storage area for processing procedures executed by the CPU 124 and a working area.

31 is a data distributor (hereinafter referred to as a distributor) that distributes 1-pi i column data at a predetermined bit position from the sequence processing unit 105 into multiple bits in parallel; 32 is a common memory 1;
This is a data selector that selects 1-bit data at a bit position specified by the sequence processing unit 105 from the parallel data starting from 00 and supplies it to the data bus driver 11. 33 is an address decoder that generates a selection signal corresponding to each bit when the sequence processing unit 105 specifies the address of the common memory lOO via the address bus driver 7, and the selection signal is sent to the gate 141.・・・
・Memories (RAM) 151, . . . , 15 arranged corresponding to each bit in the common memory 100 via .
It is led to the chip select terminal C5 of No.2.

In this configuration, input data from the input card 2 is read by the input/output unit 104 and written to the common memory lOO via the data bus driver 8. RAM 51 of each bit of the common memory 100,..., 5
At this time, the selection signal No. 2 is sent from the input/output microcomputer 104 to the address bus driver 6 and the gate 141.
．． ....

142, each RAM51,
. . , 52, data is written simultaneously. That is, data from the input/output unit 104 is written to the common memory 100 as parallel data.

On the other hand, when the sequence processing unit 105 reads data from the common memory 100, the selection signals for each RAM 51, . is supplied, and only the gate of any one selected bit position is turned on. RAM51
, . . , 52, only the 1-bit data at a predetermined bit position read from the one whose selection signal is turned on is added to the data selector 32 as valid data, and this 1-bit data is sent to the 7 data selector 32. 32 and supplied to the data line 5DBOL at a specific bit position of the data bus via the data bus driver 11 is read in parallel by the sequence processing unit 105 along with invalid data at other bit positions.

In addition, the common memory 100 is
Valid data is output only to the data bus 5DBO, but is distributed in parallel to all the remaining data lines of the data bus by the 1 distributor 31, and transmitted to the common memory 100 via the data bus driver 10. be done. Bit RAM51 of common memory ioo,・
. . , 52 selection signals are applied from the sequence processing unit 105 to the address decoder 33 via the address bus driver 7, thereby turning on the gate of one designated bit position, selecting one RAM, Data is written only to this selected RAM.

The input/output unit 104 reads data to be output to the output card 3 from the common memory 100. The selection signal C8 of the RAMs 51, . . . , 52 of the common memory 100 is sent from the input/output section 104 to the address bus driver 6 and
1. . . , 42, but at this time they are all turned on at the same time. That is, the read data in this case is output as parallel data to the data buses DBO-DBn, and is then output to the data bus 1oD via the data bus driver 9.
It is transmitted to BO~10DBn and read into the input/output unit 104.

FIG. 6 shows the correspondence between addresses and data when the common memory 100 is accessed from the input/output unit 104 and when the common memory lOO is accessed from the sequence processing unit 105.
The n-bit parallel data Dn, . . . , DO written to or read from address A of 0 is processed by the sequence processing unit 105 as bit-by-bit data from addresses A' to A'+n. It turns out.

FIG. 7 shows an example of a processing procedure when the sequence calculation process shown in the ladder diagram of FIG. 3 is performed by the apparatus according to this embodiment. In other words, it is sufficient to simply read the data at the address corresponding to the j-th bit of the i-th input card from the common memory 100 and write it to the address corresponding to the j-th bit of the i-th output card in the common memory 100. , it becomes possible to perform high-speed sequence calculation processing.

[Effects of the Invention] As explained above, according to the present invention, the sequence calculation processing means is capable of writing and reading data to and from the common memory in bit units. Since there is no need to perform a position shift process, the sequence arithmetic process is simplified, and as a result, the sequence arithmetic process time is shortened, and the speed of the sequence arithmetic process can be increased.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of the present invention, FIG. 2 is a block diagram showing an example of the configuration of a conventional sequence processing device, and FIG. 3 is a lag diagram showing an example of processing by the sequence processing device.
Figure, 4th rI! J is a flowchart showing a processing procedure for performing the processing shown in the third figure with a conventional sequence processing device. FIG. 5 is a block diagram showing an example of the configuration of the sequence processing device of the present invention, FIG. 6 is an explanatory diagram for explaining the correspondence between parallel data and serial data according to an embodiment of the present invention, and FIG. 12 is a flowchart illustrating an example of a processing procedure for performing the processing shown in the third figure according to the embodiment. 1.100...Common memory, 2...Input card. 3... Output card, 4.104... Input/output section, 5.105... Sequence processing section, 6... Input/output section address bus driver, 7... Sequence processing section address bus driver, 8 .9... Input/output section data bus driver, 10.11... Sequence processing section data bus driver, 21.24, 121, 124... CPU. 22.25, 122, 125...ROM, 23.28
, 123, 126...RAM. 31...Data distributor, 32...Data selector, 33...Address decoder. Figure 3 Figure 4 Figure 5 Bit Figure 6 Figure 7

Claims (1)

[Scope of Claims] Input/output means for inputting and outputting parallel data; storage means for storing information constituting the parallel data supplied from the input/output means in correspondence with bit positions on the parallel data; Sequence processing means that performs sequence calculation processing; Data selection means that selects data at any one bit position of the parallel data read from the storage means and sends it to the input of the sequence processing means; The sequence processing means 1. A sequence processing device comprising: data distribution means for distributing data at a predetermined bit position of parallel data outputted from the storage means to each bit position of the storage means.