JPS62114353A - Buffer circuit for loop network - Google Patents

Abstract

PURPOSE:To prevent errors from being accumulated in the next frame and subsequent frames by using the time, when heading of the next marker bit comes, to adjust loop delay if the timing of a marker bit in a specific position of a frame and the timing of a bit read clock do not coincide with each other. CONSTITUTION:The marker bit of a marker in a specific position like the beginning of a frame in a loop network is read out from a marker bit storage part 11 provided in a first-in first-out memory 10, and its timing is compared with the timing of the marker read clock by a read control part 12. If the dissidence between both timings is detected because of an error in the frame, the control part 12 switches an output switch 6 and resets a buffer register 13. The operation is restarted when they coincide with each other, that is, the heading of the next marker bit comes, and loop delay is controlled automatically. As the result, errors in the frame are prevented from being accumulated in the next frame.

Description

[Detailed Description of the Invention] [Summary] In a loop type time division multiplexing synchronous communication network, an integer number of ■ and I division frames can be placed on the loop by providing a frame buffer circuit and adjusting the frame circulation time delay. This made it possible to carry it.

[Industrial application field]

The present invention relates to improvements in buffer circuits for loop networks.

In a loop-type time division multiplex synchronous communication network,
A time division multiplexed frame is circulated on a loop, and each node accesses the loop signal in a pre-specified time slot, thereby performing communication between desired nodes. Therefore, at this time, it is necessary that exactly an integer number of time-division multiplexed frames be placed on the loop so that each node can access it in a specified time slot at a constant period. However, since the loop length is rarely an integral multiple of the frame length, it is desirable to provide a buffer circuit in the loop and adjust the time.

[Conventional technology]

A conventional means for placing an integral number of time-division multiplexed frames on a loop will be explained.

FIG. 2 shows an example of the structure of a time division multiplexed frame.

In the figure, 1 is a frame header, 2-1 to 2. , n are channel time slots.

The frame header is a signal indicating the beginning of the frame, 2-1
~2-n are time-division signals for n channels for communicating between nodes.

FIG. 3 shows a circulating state of a time division multiplexed frame on a loop.

3-1, 3-2, . . . are time division multiplexed frames shown in FIG. 2, and 4-1 to 4-m are nodes arranged along the loop.

FIGS. 4a) and 4b) diagrammatically show the adjustment of the loop length by means of the frame buffer memory.

Same 1ffl a) L! : A frame buffer memory 5 is provided for adjusting the loop length. The frame buffer memory 5 adjusts the loop length twice so that exactly an integer number of time-division multiplexed frames are placed on the loop, as shown in FIG.

FIG. 5 shows a block circuit diagram of an example of the configuration of a conventional frame buffer memory.

In the figure, 6 is an output switch of the frame buffer memory, 7 is a master clock, 8 is a frame generator, 9 is a synchronization extractor, and 10 is a first-in first-out memory.

The frame buffer memory of FIG. 5 operates as follows. First, at the time of startup, the output isochiro is 8
1 is selected, and thereby the frame generated in the frame generation unit 8 using the signal from the master clock 7, that is, the generated frame is outputted to the output unit 61 as a transmission frame.
Send to. At this time, the read line 106 of the first-in-first-out memory 10 is inhibited.

The transmitted frame goes around on a loop and returns as a feedback frame to the left input of the frame buffer memory circuit.

A frame clock and the like are extracted from the feedback frame in a synchronization extracting section 9, and the frame is written into a first-in first-out memory in order from the beginning of the frame by a write clock 91 generated by the synchronization extracting section 9. at the same time,
In the synchronization extractor 9, the amount of data stored in the first-in first-out memory 10 is monitored, and when a predetermined amount of data is accumulated, a read control signal 9 is output.
4. According to the output switching control signal 95, the first-in first-out memory I starts from the time when the beginning of the frame is generated.
Reading of O is started and sent out from the output unit 61 as a sending frame.

By successively reading and writing to the first-in-first-out memory in the same process,
An integral number of time-division multiplexed frames can be made to circulate on the loop at all times.

[Problem that the invention seeks to solve]

However, conventional frame buffer memory circuits have problems when input data is abnormal. In other words, in the conventional circuit, once the amount is increased, data is continuously transferred in the first-in-first-out memory, so if some abnormality occurs, the input data to the first-in-first-out memory is When dropouts or additions occur, the condition that there is an integral number of time-division multiplexed frames on the loop is lost, and each node is unable to access the time slots at the correct time.

[Means for solving problems]

The above problem can be solved by providing a marker bit recording section (11) that stores marker bits provided at specific positions within the frame in addition to the first-in-first-out memory (10), and when reading the bits of the frame, the marker bits and bits are The read clock is compared in the read control unit (12), and if the timing does not match, the first-in first-out memory (1
0) to locate the next marker bit, and when the timing for reading the marker bit on the reading side arrives, the operation is resumed and the loop delay is adjusted. This problem is solved by the loop-type network buffer circuit of the present invention.

[Effect]

According to the present invention, by recording a marker bit provided at a specific position within a frame in the marker recording section of the frame buffer memory circuit, the reading side can constantly monitor the operation of the frame buffer memory section.
Data loss or erroneous data addition during reading within a frame is detected, the next frame is cued, and then the operation is restarted, so it is possible to prevent errors from accumulating in the next frame or later.

〔Example〕

The details of the present invention will be explained according to the illustrated embodiments.

FIG. 1 is a block diagram of a frame buffer memory circuit in one embodiment of the present invention.

In the figure, 11 is a marker bit recording section provided in the first-in-first-out memory, 12 is a read control section, and 13 is a buffer register. Other circuit parts similar to those in FIG. 3 are indicated by the same numbers as in the same figure.

The circuit of the invention operates as follows.

In the configuration of the present invention, a marker bit recording section 11 is provided in the first-in first-out memory, and in the input section of the frame buffer memory circuit,
For each return frame, a marker indicating a specific position within the frame, for example, the beginning of the frame, is recorded in the marker bit recording unit 11 by the synchronization extraction unit 9, and
Write the return frame to portion 10 of the first-in-first-out memory.

On the other hand, on the output side of the frame buffer memory circuit, a frame generation section 8 running independently generates frame generation timing and a generated frame 81, and also outputs a read clock 84 and a marker read clock 83 to the read control section 12. .

The read control unit 12 checks the first-in-first-out memory status signal 112 and determines that the first-in-first-out memory is ready, that is, there is enough data in the first-in-first-out memory for reading, and that the first-in-first-out memory is ready. If the memory is not in an overflow state, data is read from the first-in first-out memory 10 by the clock 84 from the frame generator 8. At this time, the buffer register section 13 serves as a shift register as part of the first-in first-out memory, and the output isochiro selects the line 131.

The read control unit 12 also reads the marker bit from the marker recording unit 11 via the line 111, compares it with the marker read clock 1113 given from the frame generator 8, calculates the exclusive OR of both, and monitors the operating state. I do.

When a mismatch is detected in this part, the read control unit 1'2 first switches the output iso-chiro to the generated frame 81 side, and at the same time resets the bumper register 13 by the reset signal 125 while transmitting the original frame.

Next, the read control unit 12 creates a read clock and does not read the data in the first-in first-out memory 10 until the marker bit is detected from 111.

At this point, the beginning of the data in the first-in-first-out memory is completed, so next the frame generation unit 8
When the marker read clock arrives, data is read from the IO of the first-in-first-out memory using the read clock 123 using the clock 84 given from the frame generator 8, and the signal is connected to the line 13.
1 side and sends it out from the output unit as a sending frame.

Since automatic correction in the event of a malfunction is performed in a short time without setting the first-in-first-out memory, recovery within a -frame is possible by speeding up the cue clock for detecting the mismatch.

〔Effect of the invention〕

According to the present invention, when the network loop length changes, it is possible to automatically adjust the loop delay time, and it is possible to prevent errors in a frame from accumulating in the next frame and thereafter, and the effect is extremely high. big.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a frame buffer memory circuit in an embodiment of the present invention, FIG. 2 is a configuration diagram of a time division multiplexed frame, and FIG. 3 is a diagram of a circulating state on a loop of a time division multiplexed frame. , FIGS. 4a) and 4b) are diagrams of loop length adjustment using a frame buffer memory, and FIG. 5 is a block circuit diagram of a conventional frame buffer memory. In the figure, 1 is a frame header, 2-1 to 2-n are time slots, 3-1, 3-2, ... are time division multiplexed frames, and 4-1
~4-m is a node, 5 is a frame buffer memory, 6 is an output switch, 7 is a master clock, 8 is a frame generation section, 9 is a synchronization extraction section, 10 is a first-in first-out memory, 11 is a marker bit recording section, 12 is a read control unit, and 13 is a buffer register. Fig. 1 Slot 1 Hour/minute side strip m Frame configuration diagram m 2 Fig. 3

Claims (1)

[Claims] A marker bit recording section (11) for storing a marker bit provided at a specific position within a frame is provided in addition to the first-in-first-out memory (10), and a readout control section controls the marker bit and the bit readout clock when reading out bits of the frame. (12), if the timing does not match, the data in the first-in-first-out memory is read blankly, the next marker bit is located, and the operation is resumed when the marker bit read timing on the reading side arrives. A buffer circuit for a loop type network, characterized in that the buffer circuit is configured to adjust loop delay by adjusting the loop delay.