JPS62111337A - Memory control circuit - Google Patents

Abstract

PURPOSE:To speed up inter-memory DMA transfer and also to attain inter- memory DMA transfer even if a DMA controller (DMAC) having no inter- memory transfer mode by replacing the inter-memory DMA transfer with inter- FIFO memory DMA transfer. CONSTITUTION:An address bus 7 when a RAM 5 is accessed at random as a memory or an output of an address counter 42 when the RAM 5 is sequentially accessed as an FIFO is selected by an address selector 41 in a control circuit 4. When a DMA transfer instruction is written in a control register 43 after setting up the address counter 42, the inter-memory DMA transfer is replaced with the inter-FIFO memory transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to memory (It, AM) of microcomputers.
), rung l, accessible memory and sequentially accessible FIFO (First InFi
rst out memory).

Conventional technology Conventionally, in data processing of microcomputers,
In order to increase the transfer speed and reduce the load on the CPU, the so-called DMA (Dir
ect Memory Access) method is generally widely adopted.

The DMA controller (hereinafter referred to as DMAC) is
This DMAC has two types of transfer modes: inter-memory transfer and inter-memory transfer.

I10 memory-to-memory transfer refers to receiving a transfer request from the "■" device, outputting the specified memory address along with the response, and transferring data from the device to the memory or from the memory to the "■" device. Refers to the method of carrying out. This method has the advantage of being able to transfer data in cycles and being effective for devices that request data transfer discontinuously.

Memory-to-memory transfer is to first output a specified memory address according to the instructions of the CPU, read that data once into the DMAC, output the other specified address, and output the data from the DMAC and write it into the memory. Refers to the method. This method has ■products.

This has the advantage that a special circuit for transfer, such as a circuit for generating a transfer request signal to be sent to the DMAC, is not required.

The two transfer modes are used depending on the purpose.

In addition, as a conventional means of expanding memory space, MMU
A method using dedicated hardware such as a memory management unit (memory management unit) or a memory mapper has been adopted. These dedicated hardwares have an internal address translation register, and have a structure in which part or all of the address line output from the CPU is input to the address translation register, and the output is converted and output. In other words, conventionally, a method has been adopted in which the address itself is expanded by increasing the number of address lines using dedicated hardware, thereby expanding the memory space.

Problems to be Solved by the Invention However, the above-mentioned conventional technology has the following problems.

(1) When performing memory-to-memory transfer using DMAC, ■
ρThe transfer speed is twice that of memory-to-memory transfer. Furthermore, if a DMAC that does not have an inter-memory transfer mode is used, DMA transfer cannot be performed.

(2) Memo'J When expanding the space between 2, dedicated hardware must be used and the number of address lines increases, which increases the need for hardware such as address decoders and address buffers, which increases costs. .

On the other hand, in recent years, as the speed and volume of data processing in systems has increased, there has been a strong demand for faster data transfer and expansion of memory space.

Therefore, in order to solve the above problems and satisfy the above requirements, the present invention aims to speed up inter-memory DMA transfer, and realize inter-memory DMA transfer when using a DMAC that does not have an inter-memory transfer mode. It is an object of the present invention to provide a memory control circuit which is capable of expanding the actual memory space without using dedicated hardware or increasing the number of address lines.

Means for Solving the Problems In order to achieve the above object, the memory control circuit of the present invention comprises:
Memory space ζ FIFO access input/output water output port 1
A memory (RAM) consisting of a group of accessible memories and a group of inaccessible memories overlapping this memory in the same space can be used not only as a memory but also as a FIFO. The memory is characterized in that it is made accessible, and the accessible memory is switched between accessible memory and inaccessible memory so that the accessible memory can be randomly accessed.

According to the present invention having the above configuration, the memory-to-memory passion transfer F
By replacing it with 11"O memory-to-memory DMA transfer, it is possible to speed up the memory-to-memory DMA transfer.

Furthermore, practical inter-memory DMA transfer can be realized even by using D to anti-C which do not have an inter-memory transfer mode.

In addition, in the case of sequential access, access to multiple inaccessible memory groups arranged in the same space as accessible memories is always possible by using one group of input/output water output ports for FIFO access. In the case of random access, this is possible by switching an accessible memory to an inaccessible memory. Therefore, the memory space can be substantially increased without using conventional means such as increasing the number of address lines.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a memory map (conceptual diagram of memory space) of the memory (RAM) controlled by the memory control circuit according to the present invention, in which 1 and 1' are 8 groups of input/output water output ports for FIFO access. My port group 1 is memory 1-1
port group 1' consists of I10 for memory 2-1, I10 for memory 2-2, I10 for memory 1-2, etc.
It consists of 10...etc. 2.2' is an accessible memory currently selected as a memory, of which memory 2 is arranged as memory 1-1 in the illustrated example, and memo IJ 2' is arranged as memory 2-1 in the illustrated example. 1 is arranged. 3.3' is a group of inaccessible memories arranged in multiple layers in the same space as memory 2.2', of which memory group 3 is memory 1-2, memory 1-3, and so on.
etc., and memory group 3' consists of memory 2-2, memory 2-
Consists of 3...etc.

In other words, the memory groups 3 and 3' are arranged in the same space when viewed from the CPU, but are memory groups that are invisible to the CPU.

Furthermore, by accessing the input/output port groups 1 and 1', sequential access is possible to all memories in the inaccessible memory groups 3 and 3', including the accessible memories 2 and 2'. Become.

Note that the accessible memories 2 and 2', that is, the memory 1-
1. Random access is possible to the memory 2-1. Therefore, the memory lJ2,2' contains the memory 1-1.
For example, if memory 1-2.2=2 is switched and arranged as described below instead of 2-1, the memory 1-2
．． Random access becomes possible for 2-2.

FIG. 2 is a schematic block diagram showing an embodiment of the specific configuration of the memory control circuit according to the present invention. ) 5 can be used (accessed) as memory or as FIFO. Note that 6 is a control bus from the CPU (not shown), through which input/output timing signals, transfer request signals to the DMAC, response signals therefor, etc. are exchanged. 7 is the same (C
An address bus from the PU exchanges addresses when randomly accessing the RIAM 5 as a memory, and addresses pointing to address counters, control registers, data buffers, etc., which will be described later. 8 is a data bus from the CPU.

The memory control circuit 4 includes an address selector 41, an address counter 42, a control register 13, a data buffer 44, and a memory controller (memory control section) 45.

The address selector 41 has the function of selecting either the address bus 7 or the output of the address counter 42. That is, when random accessing the RAM 5 as a memory via the memory address line 9, the address bus 7 is selected, and when sequentially accessing the RAM 5 as a FIFO, the output of the address counter 42 is selected.

The memory controller 45 controls the entire memory control circuit 4, and controls, for example, the control signals 11 . A control signal 10 for the address counter 42 and a control signal 12 for the RAM 5 are output respectively.

The data buffer 44 is used when the mountain W5 is used as a FIFO.

Therefore, when sequentially accessing Rm5 as a FIFO, the data buffer 44 is accessed after setting the address counter 42 to the value of the address to be accessed.

In other words, FIFO access input/output boat group 1 in Figure 1
, 1' of the memory to be accessed (for example, ``■'' for memory 1-2, or ``10'' for memory 2-2).

Since the address counter 42 performs counting and amplification after the access is completed, accesses can be made one after another by accessing the data buffer 44.

Replacing inter-memory DMA transfer with FIFO inter-memory transfer can be achieved by setting the address counter 42 and writing a DMA transfer command to the control register 43.

The memory controller 45 that received the D~ta transfer command,
A transfer request is issued to the DMAC (not shown), and when a response is received from the DMAC, the value of the address counter 42 is output as the memory address, memory data is output to the data buffer 44 when reading, and memory data is output to the data buffer 44 when writing. Write the contents of 44 to memory. Thereafter, the address counter 42 counts up.

On the other hand, random access to the RAM 5 as a memory can be achieved by writing a memory accessible command to the control register 43.

In the accessible memory lJ2, 2' of FIG.
Only the memory 1-1 and the memory 2-1 are in a state where accessible instructions are written and the memory can be accessed.

The inaccessible memory groups 3, 3' in FIG.
Since it can always be accessed as O, it would be very effective to store sequential data in each. In addition, in order to randomly access these memory groups 3 and 3', write an inaccessible command to memory IJI-1 and memory 2-1, which are currently memory accessible, and instead write, for example, memory 1- 2, and memory 2
-2, by writing a memory-accessible instruction into memory, that is, by switching between accessible memory and inaccessible memory, random access can be made freely. Therefore, the capacity of the memory space can be substantially expanded.

Effects of the Invention In short, according to the present invention, inter-memory transfer is performed using FIF
Since it can be replaced with memory-to-memory transfer, it is possible to speed up the memory-to-memory transfer, and even if a DMAC that does not have a memory-to-memory transfer mode is used, the memory-to-memory DM
In addition to being able to perform A transfer, the memory space can be substantially expanded, making it possible to process large amounts of data, and other outstanding effects.

[Brief explanation of drawings]

Figure 1 shows a memory IJ (RAM) controlled by the present invention.
FIG. 2 is a conceptual diagram showing an example of a memory space structure according to the present invention. FIG. 2 is a schematic diagram showing an embodiment of a memory control circuit according to the present invention. l, 1'... FIFO access input/output port group, 2
．． 2'...Accessible memory IJ, 3.3'...Inaccessible memory group, 4...Memory control circuit, 5.
...Memory (aAM), 6..CPU control bus, 7..CPU address bus, 8..CPU data bus. Name of agent: Patent attorney Toshio Nakao (1st person)
figure

Claims (1)

[Claims] A memory (RAM) in which a group of input/output ports for FIFO access, an accessible memory, and a plurality of inaccessible memory groups arranged in the same space as this memory are arranged in a memory space. A control circuit for controlling, comprising means for randomly accessing the accessible memory, and switching for switching between the accessible memory and the inaccessible memory and randomly accessing the inaccessible memory. means for sequentially accessing the inaccessible memory group via the FIFO access input/output port group; and a memory control unit for controlling each of the means. memory control circuit.