JPS62111240A - Production of liquid crystal display panel - Google Patents

Production of liquid crystal display panel

Info

Publication number
JPS62111240A
JPS62111240A JP25178185A JP25178185A JPS62111240A JP S62111240 A JPS62111240 A JP S62111240A JP 25178185 A JP25178185 A JP 25178185A JP 25178185 A JP25178185 A JP 25178185A JP S62111240 A JPS62111240 A JP S62111240A
Authority
JP
Japan
Prior art keywords
solder
liquid crystal
electrodes
electrode
hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25178185A
Other languages
Japanese (ja)
Inventor
Shuji Kondo
修司 近藤
Isamu Kitahiro
北廣 勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP25178185A priority Critical patent/JPS62111240A/en
Publication of JPS62111240A publication Critical patent/JPS62111240A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To connect directly the wirings of LCD panels to one another and to facilitate forming a display panel by matching the relative positions of solder electrodes to join liquid crystal panels to one another. CONSTITUTION:A foundation metallic plating layer 16 is formed selectively on the pattern group of electrode terminals 2 of the LCD panels, where a liquid crystal 15 is sealed in picture element areas 5, and through holes 12 formed in the same parts. A solder foundation metallic layer is laminated on the foundation metallic plating layer 16 as short bar patterns 13, and solder foundation metallic electrodes 17 are formed on all of the inside wall face of the through holes 12. A solder is stuck to the surface of the pattern group of electrode terminals 2 on the solder foundation metallic electrodes and is packed in the through holes 12 to constitute solder electrodes 18 in the same parts. Excess and parts 19 are cut away from a main substrate glass 10, where the solder electrodes 18 are provided in through the holes 12, along the center lines of the through holes 12 to obtain a semicircular solder electrodes 18 on end wall faces 11. In case that a multipanel is constituted, the relative positions of respective semicircular solder electrodes 18 of the 4 LCD panels 1a-1d are matched to stick them to one another.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は液晶表示パネル(以下L CDパネルと略称す
る)を用いたディスプレイ装置、特に複数枚のLCDパ
ネルを貼り合わして偶成する大型fイスプレイ装置に適
したLCDパネルの¥IJ G法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a display device using a liquid crystal display panel (hereinafter abbreviated as an LCD panel), and particularly to a large f display device constructed by bonding a plurality of LCD panels together. Regarding the IJG method of suitable LCD panels.

従来の技術 LCDパネルを用いた表示ディスプレイは薄型、軽量、
低消費電力ディスプレイとして注目されているが、製造
技術上の問題から大型のLCDパネルを骨ることが難し
い。従って、大型のディスプレイを構成するために、複
数枚のLCDパネルを平面配置して貼り合わせた、所謂
マルチパネル方式等が採用されている。
Displays using conventional technology LCD panels are thin, lightweight,
Although it is attracting attention as a low power consumption display, it is difficult to fabricate a large LCD panel due to manufacturing technology issues. Therefore, in order to construct a large display, a so-called multi-panel method, in which a plurality of LCD panels are arranged in a plane and bonded together, is employed.

この複数枚のLCDパネルを貼り合わせた方式では、個
々の中休LCDパネル内の画素を制御する画素制御配線
導体、即ち走査線及び信号線配線を、外部の制御回路と
それぞれ接続する必要がある。例えば第5図のごとく、
LCDパネル1aとLCDパネル1bの接合部では、個
々のLCDパネルla、lbの端部に形成したそれぞれ
の電極端子2にフレキシブル配線フィルム3などからな
る画素制御用配線導体4をそれぞれ結合し、該フレキシ
ブル配線フィルム3をパネル1の主面に対し垂直方向に
引き出し、画東@号制御用回路基板(図示せず)と接続
するなどの方式が用いられており、接続部の形態を含め
た電極、配線の構成が複雑となり、マルチパネル方式デ
ィスプレイの製造を難かしくする一因ともなっている。
In this method in which multiple LCD panels are bonded together, it is necessary to connect the pixel control wiring conductors, that is, the scanning lines and signal wiring, which control the pixels in each partially closed LCD panel, to external control circuits. . For example, as shown in Figure 5,
At the joint between the LCD panel 1a and the LCD panel 1b, a pixel control wiring conductor 4 made of a flexible wiring film 3 or the like is connected to each electrode terminal 2 formed at the end of each LCD panel la, lb. A method is used in which the flexible wiring film 3 is pulled out in a direction perpendicular to the main surface of the panel 1 and connected to the Gato@ control circuit board (not shown), and the electrodes, including the form of the connection part, are , the wiring structure becomes complicated, which is one of the factors that makes it difficult to manufacture multi-panel displays.

なお、第5図において、5はしCDパネルの画素表示領
域、6は液晶封止樹脂層、7は複数枚LCDパネルla
、1bを貼り合わせる際の補強用透明基板を示す。
In FIG. 5, 5 indicates a pixel display area of the CD panel, 6 indicates a liquid crystal sealing resin layer, and 7 indicates a plurality of LCD panels la.
, 1b are shown as reinforcing transparent substrates when bonding them together.

発明が解決しようとする問題点 上記のように、複数のLCDパネルを用いてマルチパネ
ルディスプレイを構成するに際し、個々のLCDパネル
に対し、それぞれのLCDパネルの画素を制御駆動させ
る画素制御配線を直接付設する煩雑さを排し、LCDパ
ネル相互間の配線をパネルの端面で直接結合することが
できるようにすれば、ディスプレイパネルの製造を容易
ならしめることができる。
Problems to be Solved by the Invention As mentioned above, when constructing a multi-panel display using a plurality of LCD panels, it is necessary to directly connect pixel control wiring for controlling and driving the pixels of each LCD panel to each LCD panel. By eliminating the complication of attaching the LCD panels and making it possible to directly connect the wiring between the LCD panels at the end faces of the panels, the manufacturing of the display panel can be facilitated.

問題点を解決するための手段 上記問題点を解決するために、液晶表示ディスプレイパ
ネルの、表示パネルを形成する主ガラス基板の外部接続
用電極端子パターン形成領域に、予め電極端子パターン
の形成ピッチと同一ピッチの貫通孔を設ける工程と、前
記主ガラス基板な用いて液晶パネルを構成する工程と、
前記液晶パネルの電極端子パターン部及び口過孔内壁面
に選択的に電極下地金属層を形成する工程と、前記下地
金属層上に半田金属をfi層する工程と、前記半田金属
の積層された貫通孔内に接続用半田金属電極を充填形成
した後、貫通孔の中心線に沿って主ガラス基板の余剰端
辺部を切断して、液晶パネルの端面部に半円状の半田電
極を構成する工程と、的記半田電極の相対位置を合わせ
て液晶パネル相互間を接合する構成にしたものである。
Means for Solving the Problems In order to solve the above problems, the forming pitch of the electrode terminal patterns is preliminarily adjusted in the external connection electrode terminal pattern forming area of the main glass substrate forming the display panel of the liquid crystal display panel. a step of providing through holes with the same pitch; a step of configuring a liquid crystal panel using the main glass substrate;
selectively forming an electrode base metal layer on the electrode terminal pattern portion and the inner wall surface of the opening hole of the liquid crystal panel; forming a fi layer of solder metal on the base metal layer; After filling and forming a connecting solder metal electrode in the through hole, cut the excess edge of the main glass substrate along the center line of the through hole to form a semicircular solder electrode on the edge of the liquid crystal panel. The liquid crystal panels are bonded together by matching the relative positions of the solder electrodes and the solder electrodes.

作用 本発明により形成したψ体LCDパネルを用い、複数枚
のLCDパネルを貼り合わせる場合、パネル相互間の画
素制御配線の走査線及d信号線の接続は直接結合できる
ため、画素制御用配線導体を個々のLCDパネルと接続
する煩わしさが解消され、同時に該配線導体を敷線する
スペースが省略されるなど、ディスプレイパネルの薄型
化が図れるとともに、大型ディスプレイパネルの製造が
簡易化できる利点を有する。
Function When using the ψ body LCD panel formed according to the present invention and bonding a plurality of LCD panels, since the scanning lines and d signal lines of the pixel control wiring between the panels can be directly connected, the pixel control wiring conductor This eliminates the trouble of connecting the wiring conductors to individual LCD panels, and at the same time eliminates the space for laying the wiring conductors, which has the advantage of making the display panel thinner and simplifying the manufacturing of large display panels. .

実施例 以下本発明の一実施例を図面に基づいて説明する。第1
図(a>は本発明の相互接続用電極端子を有するLCD
パネルの平面図、第1図(b)は第1図(a)の矢印へ
方向より見た電極端子形状の側面図、゛第2図は本発明
の製造工程を示す断面図、第3図は第2図の製造工程に
対応した平面形状の概念を示す図、第4図(a)はLC
Dパネル相互間の接続を示す平面図、第4図(b)はで
の断面図である。なおそれぞれの図面はいずれも説明の
便宜上任意の寸法に拡大表示しており、第1図と第2図
は同一寸法比ではない。
EXAMPLE An example of the present invention will be described below based on the drawings. 1st
Figure (a) shows an LCD having interconnection electrode terminals of the present invention.
1(b) is a plan view of the panel; FIG. 1(b) is a side view of the shape of the electrode terminal as seen from the direction of the arrow in FIG. 1(a); FIG. 2 is a sectional view showing the manufacturing process of the present invention; FIG. is a diagram showing the concept of the planar shape corresponding to the manufacturing process in Figure 2, and Figure 4 (a) is the LC
FIG. 4(b) is a plan view showing the connection between the D panels, and a sectional view at FIG. Note that each of the drawings is enlarged to an arbitrary size for convenience of explanation, and FIG. 1 and FIG. 2 do not have the same size ratio.

第1図、第2図において、2は走査線及び信号線配線の
電極端子、5はLCDパネルの画素領域、6は液晶封止
樹脂層、8及び9はそれぞれ走査線及び信号線配線パタ
ーン、10は主基板ガラス、11はLCDパネル完成時
の主基板ガラスの端壁面、12は貫通孔、16は接合電
極部の下地金属メッキ層、17は半田下地金#l電極、
18は接合電極となる半田電極である。
1 and 2, 2 is an electrode terminal for scanning line and signal line wiring, 5 is a pixel area of the LCD panel, 6 is a liquid crystal sealing resin layer, 8 and 9 are scanning line and signal line wiring patterns, respectively; 10 is the main substrate glass, 11 is the end wall surface of the main substrate glass when the LCD panel is completed, 12 is the through hole, 16 is the base metal plating layer of the bonding electrode part, 17 is the solder base gold #l electrode,
18 is a solder electrode serving as a bonding electrode.

次に、図面に従って製造法の詳細な説明を行う。Next, a detailed explanation of the manufacturing method will be given according to the drawings.

第2図は画素制御用の走査線配線パターン8部分の縦断
面を示している。なお、信号線配線パターン9について
も電極端子及び接合電極部の構成は同一であるため、以
下断面構造は走査線側を例にして製造工程の説明を行う
。第2図(a)及び第3図(a)に示すように、主基板
ガラス10上の画素領域5の外側に形成する電極端子2
のパターン群で、かつLCDパネルの完成時には主基板
ガラス10の端壁面11となるべき部位に、予め走査線
及び信号線配線パターン8,9の電極端子2のパターン
ピッチPに合わせたピッチpで、貫通孔12をレーザー
ビーム等により形成する。この貫通孔12の開孔径φは
、電極端子2のピッチP及び巾Wの寸法にもよるが、2
00μ1g、上とすることがIn工程上好ましい。
FIG. 2 shows a vertical section of a portion of the scanning line wiring pattern 8 for pixel control. It should be noted that since the structure of the electrode terminal and the bonding electrode part is the same for the signal line wiring pattern 9, the manufacturing process will be explained below using the scanning line side as an example of the cross-sectional structure. As shown in FIGS. 2(a) and 3(a), electrode terminals 2 formed outside the pixel area 5 on the main substrate glass 10
, and at a pitch P that matches the pattern pitch P of the electrode terminals 2 of the scanning line and signal line wiring patterns 8 and 9 in advance at a portion that will become the end wall surface 11 of the main substrate glass 10 when the LCD panel is completed. , the through hole 12 is formed using a laser beam or the like. The opening diameter φ of this through hole 12 depends on the pitch P and width W of the electrode terminals 2, but
00μ1g or more is preferable in terms of the In process.

このように、電極端子2のパターン群の形成予定位置に
、予め貫通孔12を設けた主基板ガラス10の主面に対
し、第2図(b)、第3図(b)のように走査線及び信
号線配線パターン8,9、並びにTPT素子などの画素
制御機能部(図示せず)を形成する。なお、この時走査
線及び信号線配線パターン8,9の終端である電極端子
2のパターン群の端は、後で実施する電解メッキの共通
電極に使用するため、第3図(b)のように主基板ガラ
ス10の端辺にショートバーパターン13を形成し、電
極端子相互間を電気的に結合した形態としておく。
In this way, the main surface of the main substrate glass 10, in which the through holes 12 are provided in advance at the positions where the pattern group of the electrode terminals 2 is planned to be formed, is scanned as shown in FIGS. 2(b) and 3(b). Line and signal line wiring patterns 8 and 9, and a pixel control function section (not shown) such as a TPT element are formed. At this time, the ends of the pattern group of electrode terminals 2, which are the ends of the scanning line and signal line wiring patterns 8 and 9, are used as common electrodes for electrolytic plating that will be performed later, so they are separated as shown in Figure 3(b). A short bar pattern 13 is formed on the edge of the main substrate glass 10, and the electrode terminals are electrically coupled to each other.

走査線及び信号線配線パターン8,9並びにTPT素子
などの画素制御機能部などを形成した主基板ガラス10
の主面の所定位111(画素形成領域)に、第2図(C
)のように対向電極ガラス基板14を10μm程度の間
隙で封止接着樹16により接着固定し、該間隙部に液晶
15を注入封止する。このプロセスは電極端子2のパタ
ーン群の端をショートバーパターン13で結合する以外
は、通常のアクティブマトリックス方式のしCD表示パ
ネルの製造法と同一の製造法で製造するため、詳細な説
明は省略する。
Main substrate glass 10 on which scanning line and signal line wiring patterns 8 and 9 and pixel control function parts such as TPT elements are formed.
At a predetermined position 111 (pixel formation area) on the main surface of the
), the counter electrode glass substrate 14 is adhesively fixed with a sealing adhesive 16 with a gap of about 10 μm, and the liquid crystal 15 is injected and sealed into the gap. This process is manufactured using the same manufacturing method as that of a normal active matrix type CD display panel, except for connecting the ends of the pattern group of electrode terminals 2 with the short bar pattern 13, so a detailed explanation will be omitted. do.

次に、第2図(C)、第3図< r、 >のように、画
素領域5に液晶15を封入したLCDパネルの電極端子
2のパターン群及び同部位に形成した貫通孔12に対し
て、下地金属メッキ層16を選択的に形成する。例えば
Cuの無電解スルーホールメッキにより数μlのメッキ
層を貫通孔12の内壁面に形成するとともに、該メッキ
層の一端を電極端子2のパターン群のパターン表面及び
ショートバーパターン13上に析層形成し、それぞれの
電極端子2のパターン群と電気的に結合せしめる。
Next, as shown in FIG. 2(C) and FIG. Then, a base metal plating layer 16 is selectively formed. For example, a plating layer of several μl is formed on the inner wall surface of the through hole 12 by electroless through-hole plating of Cu, and one end of the plating layer is deposited on the pattern surface of the pattern group of the electrode terminal 2 and the short bar pattern 13. The electrode terminals 2 are formed and electrically connected to the pattern groups of the respective electrode terminals 2.

しかる後、第2図(d)のように、Cu、Niなとの半
田下地金属層をショートバーパターン13を電極として
電解メッキ法により10μmの厚みで下地金属メッキ層
16上にvi!1層し、貫通孔12の内壁面全域に半田
下地金属電極17を形成する。
Thereafter, as shown in FIG. 2(d), a soldering base metal layer of Cu, Ni, etc. is deposited on the base metal plating layer 16 with a thickness of 10 μm by electrolytic plating using the short bar pattern 13 as an electrode. A solder base metal electrode 17 is formed over the entire inner wall surface of the through hole 12.

さらに、半田下地金1%電極17上に対して半田金属の
電解メッキ処理を半Ell下地金属の形成時と同様のプ
ロセスで施して、半田を電極端子2のパターン群の表面
に被着せしめるとともに、口過孔12内部にも充填形成
することにより同部位で半田電極18を構成する(第2
図(e)、第3図(e))。
Further, electrolytic plating of solder metal is applied to the 1% solder base metal electrode 17 in the same process as in the formation of the semi-Ell base metal, so that the solder adheres to the surface of the pattern group of the electrode terminal 2. By filling and forming the inside of the opening hole 12, the solder electrode 18 is formed at the same location (the second
Figure (e), Figure 3 (e)).

なお、半田金属のメッキにあたっては、本実施例のよう
に半田下地金属電極17上に形成する以外に、直接下地
金属メッキ層16上に半田電4fj18を電解メッキで
形成することもできる。
When plating the solder metal, instead of forming it on the solder base metal electrode 17 as in this embodiment, the solder metal 4fj18 can also be formed directly on the base metal plating layer 16 by electrolytic plating.

また、i通孔12内部に半田電極18を充填形成する他
の実施例として、半田下地金属電極17を貫通孔12の
内壁面全域に電解メッキ法により形成したのち、貫通孔
12を含む主基板ガラス10の周辺領域を数秒間、溶融
半田槽に浸漬するか、もしくは溶融半田噴流槽の噴流面
に接触されることにより、半田は電極端子2のパターン
群の表面に被着するとともに、貫通孔12の内壁面の半
田下地金属電極17にも選択的に半田電極18を充填形
成づるCとができる。
In addition, as another embodiment in which the solder electrode 18 is filled and formed inside the i-through hole 12, the solder base metal electrode 17 is formed on the entire inner wall surface of the through-hole 12 by electrolytic plating, and then the main board including the through-hole 12 is By immersing the peripheral area of the glass 10 in a molten solder tank for a few seconds or by contacting the jet surface of the molten solder jet tank, the solder adheres to the surface of the pattern group of the electrode terminal 2 and also forms the through holes. The solder base metal electrode 17 on the inner wall surface of No. 12 can also be selectively filled with a solder electrode 18.

なお、上記の正則では、いずれも電極端子2のパターン
部の表面上にも半田を被着ぜしめているが、同部位をソ
ルダリングレジスト等のマスキング材料で被覆して上記
の処理を施せば、貫通孔12の内壁面のみに選択的に半
田電極18が形成される。
Note that in the above rules, solder is also deposited on the surface of the pattern part of the electrode terminal 2, but if the same part is covered with a masking material such as a soldering resist and the above process is performed, A solder electrode 18 is selectively formed only on the inner wall surface of the through hole 12 .

このようにして、貫通孔12の内部に半田電極18を設
けた主基板ガラス10を、第2図(f)、第3図(f)
のように異通孔12の中心線即ちLCDパネルの完成時
に主基板ガラス10の端壁面11となる部位でその余剰
端部19を切断すると、端壁面11には同図及び第1図
のように半円状の半田電極18が得られる。
In this way, the main substrate glass 10 with the solder electrode 18 provided inside the through hole 12 is assembled as shown in FIGS. 2(f) and 3(f).
If the excess end 19 is cut at the center line of the different through hole 12, that is, at the part that will become the end wall surface 11 of the main substrate glass 10 when the LCD panel is completed, the end wall surface 11 will have a hole as shown in the same figure and FIG. A semicircular solder electrode 18 is obtained.

この端壁面11に半田金属電極18を形成したLCDパ
ネルを複数枚平面配置してマルチパネルを構成する場合
、例えば第4図(a)のように、4枚のLCDパネル1
a、1b、 1c、1d(7)それぞれの半円状の半田
電極18の相対位置を合わせてパネルを貼り合わせ、ぞ
の後、半Ffl電極18部を加熱!2!!l!I!すれ
ば、それぞれのLCDパネルの半田電極18の半u1は
溶融し、密着相対配置された半田電極18相互間が曲者
固化するため、該電橋群に接続しであるLCDパネル相
互間の走査線及び信号線配線の接続がLC[)パネルの
!@壁面においてなされる。
When configuring a multi-panel by arranging a plurality of LCD panels on which solder metal electrodes 18 are formed on the end wall surface 11, for example, as shown in FIG. 4(a), four LCD panels 1
A, 1b, 1c, 1d (7) The relative positions of the semicircular solder electrodes 18 of each panel are aligned and the panels are bonded together.After that, the 18 portions of the semi-Ffl electrodes are heated! 2! ! l! I! Then, the halves u1 of the solder electrodes 18 of each LCD panel are melted, and the solder electrodes 18 that are closely arranged relative to each other are solidified, so that the scanning between the LCD panels connected to the electric bridge group is Connect lines and signal lines on the LC [) panel! @It is done on the wall.

発明の効宋 以上本発明の製造法に基づいて、LCDパネルを製造す
ることにより、該LCDパネルの端壁面に接続用電極端
子が形成され、このLCDパネルを複数枚用いてマルチ
パネルを構成すれば、しCDパネルの制御駆動用の走査
線及び信号線ラインのLCDパネル相互間での接続が、
該LCDパネルの端壁面においてなされるため、パネル
相互間を接続するためのスペースが不用となり、隣接す
るLCDパネルを密着して配置することが可能となる。
Effects of the Invention By manufacturing an LCD panel based on the manufacturing method of the present invention, connection electrode terminals are formed on the end wall surface of the LCD panel, and a multi-panel can be constructed by using a plurality of these LCD panels. For example, the connection between the scanning lines and signal lines for control driving of the CD panel between the LCD panels is as follows.
Since this is done on the end wall surface of the LCD panel, there is no need for space for connecting the panels to each other, and it becomes possible to arrange adjacent LCD panels in close contact with each other.

これはしCDパネルの接続部にできる無画素領域(絵素
が無いため、画像表示ができない領域)の巾を狭くする
ことで有り、複数枚のしCDパネルを平面配置したマル
チパネル方式ディスプレイの品質を向上させることにな
る。
This is by narrowing the width of the no-pixel area (area where no image can be displayed because there are no picture elements) that occurs at the connection part of the CD panel, and it is possible to reduce the width of the non-pixel area (area where no image can be displayed because there are no pixels). This will improve quality.

また、個々のLCDパネルに画像制御用配線を直接接続
することが無いため、組み立て時の製造工程が簡略化さ
れるとともに、接続個所が減少するため信頼性の向上に
も寄与し、さらに、接続がパネルの端壁面相互間でなさ
れるため、個別の接続用配線スペースが省略され、ディ
スプレイパネル全体の厚さを薄くすることができる。
In addition, since image control wiring is not directly connected to each LCD panel, the manufacturing process during assembly is simplified, and the number of connection points is reduced, contributing to improved reliability. Since the connection is made between the end walls of the panel, a separate connection wiring space is omitted, and the overall thickness of the display panel can be reduced.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す相互接続用電極端子を
有するLCDパネルの平面図及び側面図、第2図は本発
明の製造工程を示す断面図、第3図は第2図に対応した
主要製造工程の平面での概念をしめす図、第4図は本発
明の製造法によるパネルのパネル相互間の接続を示す平
面図および断面図、第5図は従来例を示す断面図である
。 1a〜1d・・・LCI)パネル、2・・・走査線及び
信号線配線の電#A端子、5・・・LCDの画素領域、
6・・・液晶封止樹脂層、8・・・走査線配線パターン
、9・・・信号線配線パターン、10・・・主基板ガラ
ス、11・・・LCDパネル完成時の主基板ガラスの端
壁面、12・・貫通孔、14・・・対向電極ガラス基板
、15・・・液晶、16・・・下地金属メッキ層、17
・・・半田下地金属電極、18・・・半田電極、19・
・・主基板ガラスの余剰端部代理人     森   
 本   義   弘6−−−近晶打止rdlし曹  
S−−一下地公墨メ・ソ\層3゛走貞オ駄の乙宿iIず
ターン lツー−−4io下地僅ソし電有ν9−−−1
aMPJliJIlt<9−ン B−J+B’flkt
n−−−EMrgrrちフ tz −−−−ff進退 孔5−一儂品 tq−−−i基IIIグラスの争刺端卵13−−−シア
ートlで−lで9−〉 第3図 第4図 1dN/d−IcDバネlL
FIG. 1 is a plan view and a side view of an LCD panel having interconnecting electrode terminals showing one embodiment of the present invention, FIG. 2 is a sectional view showing the manufacturing process of the present invention, and FIG. 3 is similar to FIG. Figure 4 is a plan view and cross-sectional view showing the connection between panels according to the manufacturing method of the present invention, and Figure 5 is a cross-sectional view showing a conventional example. be. 1a to 1d...LCI) panel, 2...Electric #A terminal of scanning line and signal line wiring, 5...LCD pixel area,
6...Liquid crystal sealing resin layer, 8...Scanning line wiring pattern, 9...Signal line wiring pattern, 10...Main board glass, 11...Edge of main board glass when LCD panel is completed Wall surface, 12... Through hole, 14... Counter electrode glass substrate, 15... Liquid crystal, 16... Base metal plating layer, 17
...Solder base metal electrode, 18...Solder electrode, 19.
・Excess edge agent Mori of main substrate glass
Yoshihiro Moto 6 --- Kinsho Cessation RDL Cao
S--Ichishimoji public sumi me/so\layer 3゛Running Oda's Otsuyado IIzu turn l2--4io groundwork only sore electric v9---1
aMPJliJIlt<9-n B-J+B'flkt
n---EMrgrrchiftz---ff advance/retreat hole 5-one item tq---i group III glass rivet end egg 13---Seat l in -l in 9-> Figure 3 4 Figure 1dN/d-IcD spring lL

Claims (1)

【特許請求の範囲】 1、液晶表示ディスプレイパネルの、表示パネルを形成
する主ガラス基板の外部接続用電極端子パターン形成領
域に、予め電極端子パターンの形成ピッチと同一ピッチ
の貫通孔を設ける工程と、前記主ガラス基板を用いて液
晶パネルを構成する工程と、前記液晶パネルの電極端子
パターン部及び貫通孔内壁面に選択的に電極下地金属層
を形成する工程と、前記下地金属層上に半田金属を積層
する工程と、前記半田金属の積層された貫通孔内に接続
用半田金属電極を充填形成した後、貫通孔の中心線に沿
って主ガラス基板の余剰端辺部を切断して、液晶パネル
の端面部に半円状の半田電極を構成する工程と、前記半
田電極の相対位置を合わせて液晶パネル相互間を接合す
る液晶表示パネルの製造法。 2、貫通孔内壁面に充填する接続用半田金属電極を、前
記内壁面に形成した下地金属層を電極として電解半田メ
ッキ法により析層形成することを特徴とする特許請求の
範囲第1項記載の液晶表示パネルの製造法。 3、貫通孔内壁面に充填する接続用半田金属電極を、前
記液晶表示パネルの貫通孔形成領域を半田浴槽中に浸漬
し、前記貫通孔内壁面の下地金属層上に半田金属層を積
層形成したことを特徴とする特許請求の範囲第1項記載
の液晶表示パネルの製造法。
[Claims] 1. A step of providing in advance through holes with the same pitch as the formation pitch of the electrode terminal patterns in the external connection electrode terminal pattern formation area of the main glass substrate forming the display panel of the liquid crystal display panel. , a step of forming a liquid crystal panel using the main glass substrate, a step of selectively forming an electrode base metal layer on the electrode terminal pattern portion and the inner wall surface of the through hole of the liquid crystal panel, and a step of forming an electrode base metal layer on the base metal layer. After the step of laminating metal and filling and forming a connecting solder metal electrode in the through hole in which the solder metal is laminated, cutting the excess edge portion of the main glass substrate along the center line of the through hole, A method for manufacturing a liquid crystal display panel, which includes forming semicircular solder electrodes on end surfaces of liquid crystal panels, and joining the liquid crystal panels together by aligning the relative positions of the solder electrodes. 2. The connection solder metal electrode to be filled in the inner wall surface of the through hole is deposited by electrolytic solder plating using a base metal layer formed on the inner wall surface as an electrode. A manufacturing method for liquid crystal display panels. 3. For connection solder metal electrodes to be filled in the inner wall surface of the through hole, the through hole forming area of the liquid crystal display panel is immersed in a solder bath, and a solder metal layer is laminated on the base metal layer of the inner wall surface of the through hole. A method for manufacturing a liquid crystal display panel according to claim 1, characterized in that:
JP25178185A 1985-11-09 1985-11-09 Production of liquid crystal display panel Pending JPS62111240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25178185A JPS62111240A (en) 1985-11-09 1985-11-09 Production of liquid crystal display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25178185A JPS62111240A (en) 1985-11-09 1985-11-09 Production of liquid crystal display panel

Publications (1)

Publication Number Publication Date
JPS62111240A true JPS62111240A (en) 1987-05-22

Family

ID=17227827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25178185A Pending JPS62111240A (en) 1985-11-09 1985-11-09 Production of liquid crystal display panel

Country Status (1)

Country Link
JP (1) JPS62111240A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164853A (en) * 1989-04-06 1992-11-17 Ricoh Company, Ltd. Liquid crystal display panel with plural substrates
JP2002169483A (en) * 2000-12-04 2002-06-14 Sony Corp Display device, electronic appliance and method for manufacturing display device
JP2014145849A (en) * 2013-01-28 2014-08-14 Sharp Corp Active matrix substrate, inspection method and electric device
JP2017501453A (en) * 2013-11-28 2017-01-12 ジオ・オプトエレクトロニクス・コーポレイションGio Optoelectronics Corp. Matrix circuit board, display device, and manufacturing method of matrix circuit board

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164853A (en) * 1989-04-06 1992-11-17 Ricoh Company, Ltd. Liquid crystal display panel with plural substrates
JP2002169483A (en) * 2000-12-04 2002-06-14 Sony Corp Display device, electronic appliance and method for manufacturing display device
JP2014145849A (en) * 2013-01-28 2014-08-14 Sharp Corp Active matrix substrate, inspection method and electric device
JP2017501453A (en) * 2013-11-28 2017-01-12 ジオ・オプトエレクトロニクス・コーポレイションGio Optoelectronics Corp. Matrix circuit board, display device, and manufacturing method of matrix circuit board
US10156748B2 (en) 2013-11-28 2018-12-18 Gio Optoelectronics Corp. Matrix circuit substrate, display apparatus, and manufacturing method of matrix circuit substrate
US10545364B2 (en) 2013-11-28 2020-01-28 Gio Optoelectronics Corp. Matrix circuit substrate, display apparatus, and manufacturing method of matrix circuit substrate

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