JP3405102B2 - Manufacturing method of solder bump connection element - Google Patents

Manufacturing method of solder bump connection element

Info

Publication number
JP3405102B2
JP3405102B2 JP35458996A JP35458996A JP3405102B2 JP 3405102 B2 JP3405102 B2 JP 3405102B2 JP 35458996 A JP35458996 A JP 35458996A JP 35458996 A JP35458996 A JP 35458996A JP 3405102 B2 JP3405102 B2 JP 3405102B2
Authority
JP
Japan
Prior art keywords
insulating substrate
solder bump
base electrode
electrode film
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP35458996A
Other languages
Japanese (ja)
Other versions
JPH10189607A (en
Inventor
浩史 川合
康志 浅地
泰宏 根来
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP35458996A priority Critical patent/JP3405102B2/en
Publication of JPH10189607A publication Critical patent/JPH10189607A/en
Application granted granted Critical
Publication of JP3405102B2 publication Critical patent/JP3405102B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/28Applying non-metallic protective coatings
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明が属する技術分野】本発明は半田バンプを介して
回路基板等に接続する半田バンプ接続素子の製造方法
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a solder bump connecting element for connecting to a circuit board or the like via a solder bump.

【0002】[0002]

【従来の技術】図4には半田バンプ接続素子の半田バン
プ部分の一例が示されている。半田バンプ接続素子は、
素子形成基板1に形成したマイクロジャイロやコンデン
サ等の素子(図示せず)を半田バンプ3を介して予め定
められた接続相手側の回路基板等に導通接続させる構成
の素子であり、この半田バンプ接続素子の半田バンプ部
分は、図4に示すように、マイクロジャイロやコンデン
サ等の素子が形成される素子形成基板1と、絶縁基板2
と、半田バンプ3と、接続部4と、スルーホール5と、
接続電極6と、下地電極膜8と、リード導体10とを有
して構成されている。
2. Description of the Related Art FIG. 4 shows an example of a solder bump portion of a solder bump connecting element. The solder bump connection element is
An element (not shown) such as a microgyro or a capacitor formed on the element forming substrate 1 is electrically connected to a predetermined circuit board or the like on the other side of the connection through the solder bump 3. As shown in FIG. 4, the solder bump portion of the connection element includes an element forming substrate 1 on which elements such as a microgyro and a capacitor are formed, and an insulating substrate 2.
, The solder bumps 3, the connecting portions 4, the through holes 5,
The connection electrode 6, the base electrode film 8 and the lead conductor 10 are provided.

【0003】同図に示すように、上記素子形成基板1の
上には絶縁基板2が接合され、また、素子形成基板1に
は上記素子と接続する接続部4が形成され、この接続部
4に対応する絶縁基板2の上面には開口部が形成され該
開口部から前記接続部4に達するスルーホール5が絶縁
基板2に形成されている。このスルーホール5の底面で
ある接続部4の上には接続電極6が形成されている。
As shown in the figure, an insulating substrate 2 is bonded on the element forming substrate 1, and a connecting portion 4 for connecting the element is formed on the element forming substrate 1. The connecting portion 4 is formed. An opening is formed in the upper surface of the insulating substrate 2 corresponding to, and a through hole 5 reaching the connecting portion 4 from the opening is formed in the insulating substrate 2. A connection electrode 6 is formed on the connection portion 4, which is the bottom surface of the through hole 5.

【0004】また、前記絶縁基板2の上面における半田
バンプ3の形成領域には下地電極膜8が形成されてお
り、この下地電極膜8の上に半田バンプ3が接合形成さ
れている。上記下地電極膜8は、絶縁基板2と半田バン
プ3の両方に接合が容易な材料により形成されている。
上記半田バンプ3は絶縁基板2に接合し難いので、上記
下地電極膜8を介して絶縁基板2に固定形成することが
できる。また、前記接続電極6と下地電極膜8を接続す
るリード導体10が形成されている。
A base electrode film 8 is formed in a region where the solder bumps 3 are formed on the upper surface of the insulating substrate 2, and the solder bumps 3 are bonded and formed on the base electrode film 8. The base electrode film 8 is formed of a material that can be easily bonded to both the insulating substrate 2 and the solder bump 3.
Since the solder bumps 3 are difficult to bond to the insulating substrate 2, the solder bumps 3 can be fixedly formed on the insulating substrate 2 via the base electrode film 8. Further, a lead conductor 10 that connects the connection electrode 6 and the base electrode film 8 is formed.

【0005】上記半田バンプ3が予め定められた接続相
手側の回路基板等の接続部に接合され、前記素子は接続
部4と接続電極6とリード導体10と下地電極膜8と半
田バンプ3を介して上記回路基板等の接続部に導通接続
される。
The solder bump 3 is bonded to a predetermined connecting portion of a circuit board or the like on the other side of the connection, and the element includes the connecting portion 4, the connecting electrode 6, the lead conductor 10, the base electrode film 8 and the solder bump 3. It is conductively connected to the connecting portion of the circuit board or the like through.

【0006】上記構成の半田バンプ接続素子は次のよう
にして製造される。例えば、素子と接続部4が形成され
た素子形成基板1に、予めスルーホール5が形成された
絶縁基板2を、スルーホール5を接続部4に位置合わせ
して接合させる。次に、接続電極6と下地電極膜8を形
成する領域を規制するレジストパターンを絶縁基板2の
上面に形成し、その後、スパッタや蒸着等の成膜形成技
術により上記スルーホール5の底面の接続部4の上に接
続電極6を形成すると共に、絶縁基板2の上面に下地電
極膜8を形成する。
The solder bump connecting element having the above structure is manufactured as follows. For example, the insulating substrate 2 in which the through holes 5 are formed in advance is joined to the element forming substrate 1 in which the elements and the connecting portions 4 are formed by aligning the through holes 5 with the connecting portions 4. Next, a resist pattern is formed on the upper surface of the insulating substrate 2 to regulate the region where the connection electrode 6 and the base electrode film 8 are formed, and then the bottom surface of the through hole 5 is connected by a film forming technique such as sputtering or vapor deposition. The connection electrode 6 is formed on the portion 4, and the base electrode film 8 is formed on the upper surface of the insulating substrate 2.

【0007】然る後、上記レジストパターンを除去し、
次に、接続電極6と下地電極膜8を接続するリード導体
10を形成する領域を規制するレジストパターンを形成
し、その後、成膜形成技術によりリード導体10を形成
する。そして、上記レジストパターンを除去し、前記下
地電極膜8の上に半田材料を付着させ、この半田材料を
溶融して半田バンプを形成し、半田バンプ接続素子が完
成する。
After that, the resist pattern is removed,
Next, a resist pattern that regulates a region where the lead conductor 10 that connects the connection electrode 6 and the base electrode film 8 is formed, and then the lead conductor 10 is formed by a film forming technique. Then, the resist pattern is removed, a solder material is adhered on the base electrode film 8, and the solder material is melted to form a solder bump, thereby completing a solder bump connecting element.

【0008】[0008]

【発明が解決しようとする課題】上記構成の半田バンプ
接続素子では、前記の如く、絶縁基板2の上面に半田バ
ンプ3と、スルーホール5の開口部とが別個に形成され
ている。このように、絶縁基板2の上面に半田バンプ3
とスルーホール5の開口部を別個に設けなければならな
いので、絶縁基板2の上面には半田バンプ3の形成領域
とスルーホール5の開口部の形成領域が共に必要であ
り、上記半田バンプ3とスルーホール5の各形成領域の
大きさは予め定めた大きさよりも小さくすることができ
ないので、絶縁基板2の上面面積を狭くできず、絶縁基
板2の小型化が困難であり、このことに起因して半田バ
ンプ接続素子の小型化が困難であるという問題が生じ
る。
In the solder bump connecting element having the above structure, the solder bump 3 and the opening of the through hole 5 are separately formed on the upper surface of the insulating substrate 2 as described above. In this way, the solder bumps 3 are formed on the upper surface of the insulating substrate 2.
Since the openings of the through holes 5 and the through holes 5 must be provided separately, both the solder bump 3 forming area and the through hole 5 opening forming area are required on the upper surface of the insulating substrate 2. Since the size of each formation region of the through hole 5 cannot be made smaller than a predetermined size, the upper surface area of the insulating substrate 2 cannot be reduced, which makes it difficult to downsize the insulating substrate 2. Then, there arises a problem that it is difficult to downsize the solder bump connection element.

【0009】また、上記接続部4の上に接続電極6が形
成されると共に、絶縁基板2の上面に下地電極膜8が形
成され、上記接続電極6と下地電極膜8を導通接続させ
るためのリード導体10が設けられ、上記接続電極6と
下地電極膜8とリード導体10を形成するときには、例
えば、上記各電極の形成領域を規制するレジストパター
ンを形成した後に、スパッタや蒸着等により各電極の膜
を成膜形成し、その後、上記レジストパターンを除去す
るという面倒な工程を経なければならず、電極形成の工
程が煩雑になるという問題がある。
A connection electrode 6 is formed on the connection portion 4 and a base electrode film 8 is formed on the upper surface of the insulating substrate 2 to electrically connect the connection electrode 6 and the base electrode film 8. When the lead conductor 10 is provided and the connection electrode 6, the base electrode film 8 and the lead conductor 10 are formed, for example, after forming a resist pattern that regulates the formation region of each electrode, each electrode is formed by sputtering or vapor deposition. There is a problem that the step of forming an electrode becomes complicated because a complicated step of forming and forming the film of 1) and then removing the resist pattern is required.

【0010】この発明は上記課題を解決するためになさ
れたものであり、その目的は、小型化が容易で、しか
も、簡単な工程で製造することが可能な半田バンプ接続
子の製造方法を提供することにある。
[0010] This invention has been made to solve the above problems, is easy to miniaturize, moreover, the solder bump connection <br/> element which can be produced by a simple process It is to provide a manufacturing method of.

【0011】[0011]

【0012】[0012]

【課題を解決するための手段】 上記目的を達成するため
にこの発明は次のような構成をもって前記課題を解決す
る手段としている。すなわち、 半田バンプ接続素子の製
造方法の第1の発明は、素子が形成される素子形成基板
には上記素子に接続する接続部が形成され、上記素子形
成基板の上には絶縁基板が接合され、上記接続部に対応
する絶縁基板の上面には開口部が形成され該開口部から
上記接続部に達するスルーホールが上記絶縁基板に形成
されている半田バンプ接続素子の製造方法において、ま
ず、上記素子と接続部が形成された素子形成基板にスル
ーホールが形成された絶縁基板を上記スルーホールに接
続部を位置合わせして接合し、次に、成膜形成技術によ
り下地電極膜の材料を付着させて少なくとも絶縁基板の
上面と接続部の上面に導電膜を形成し、然る後、絶縁基
板の上面の導電膜を全て取り除くことにより接続部の上
面に下地電極膜を形成し、その後、スルーホールの内部
に半田材料を収容し、該半田材料を溶融して半田バンプ
を形成し該半田バンプを絶縁基板の上側に突き出させる
と共に、半田バンプと接続部の上面の下地電極膜を接合
する構成をもって前記課題を解決する手段としている。
[Means for Solving the Problems] To achieve the above object
The present invention has the following structure to solve the above problems.
As a means to That is, the first invention of the method for manufacturing a solder bump connection element is such that a connection portion for connecting to the element is formed on the element formation substrate on which the element is formed, and an insulating substrate is bonded on the element formation substrate. In the method of manufacturing a solder bump connecting element, an opening is formed in the upper surface of the insulating substrate corresponding to the connecting portion, and a through hole reaching the connecting portion from the opening is formed in the insulating substrate. An insulating substrate in which through holes are formed in the element formation substrate in which the element and the connection portion are formed is joined by aligning the connection portion with the above through hole, and then the material of the base electrode film is attached by the film forming technology. Then, a conductive film is formed on at least the upper surface of the insulating substrate and the upper surface of the connection portion, and thereafter, the conductive film on the upper surface of the insulating substrate is completely removed to form a base electrode film on the upper surface of the connection portion. Accommodating the soldering material inside the Horu, it causes protrude solder bumps are melted to form the solder bumps to solder material on the upper side of the insulating substrate, joining the base electrode film on the upper surface of the connection between the solder bump structure Is a means for solving the above-mentioned problems.

【0013】半田バンプ接続素子の製造方法の第2の発
明は、上記半田バンプ接続素子の製造方法の第1の発明
に示す絶縁基板の上面の導電膜は研磨技術により全て取
り除かれる構成をもって前記課題を解決する手段として
いる。
A second invention of the method for manufacturing a solder bump connection element has the above-mentioned problem in that the conductive film on the upper surface of the insulating substrate shown in the first invention of the method for manufacturing a solder bump connection element is completely removed by a polishing technique. As a means to solve.

【0014】上記構成の発明において、絶縁基板に形成
されたスルーホールの底面の接続部の上に下地電極膜が
形成され、この下地電極膜の上に半田バンプが接合形成
されており、上記半田バンプは前記絶縁基板の上側に突
き出してスルーホールに収容されている。例えば、上記
絶縁基板の上側に突き出した部分の半田バンプは予め定
められた接続相手側の回路基板の接続部に接続され、素
子形成基板に形成された素子は該素子に接続する接続部
と下地電極膜と半田バンプを介して上記回路基板の接続
部に導通接続する。
In the invention of the above structure, the base electrode film is formed on the connection portion on the bottom surface of the through hole formed in the insulating substrate, and the solder bump is bonded and formed on the base electrode film. The bump protrudes above the insulating substrate and is accommodated in the through hole. For example, the solder bumps of the portion protruding above the insulating substrate are connected to the connection portion of the circuit board of the predetermined connection partner side, and the element formed on the element forming substrate is connected to the connection portion and the base. Conductive connection is made to the connection portion of the circuit board via the electrode film and the solder bump.

【0015】上記の如く、スルーホールに半田バンプを
収容するので、絶縁基板の上面にスルーホールを形成す
る領域と、半田バンプを形成する領域とを別個に設ける
必要がなく、絶縁基板の上面に半田バンプの形成領域を
確保しなくて済み、絶縁基板の上面の面積が削減できて
絶縁基板の小型化が容易となる。このことにより、半田
バンプ接続素子の小型化が容易となる。
As described above, since the solder bumps are accommodated in the through holes, it is not necessary to separately provide a region for forming the through holes and a region for forming the solder bumps on the upper surface of the insulating substrate, and the upper surface of the insulating substrate can be formed. It is not necessary to secure the formation region of the solder bumps, the area of the upper surface of the insulating substrate can be reduced, and the insulating substrate can be easily downsized. This facilitates downsizing of the solder bump connection element.

【0016】また、スルーホールの底面の接続部の上に
下地電極膜を形成し、この下地電極膜の上に半田バンプ
を接続させるので、この発明に示す下地電極膜は、前記
従来例に示した前記接続部の上の接続電極と、半田バン
プの下の下地電極膜の機能とを兼用する構成を成してい
る。また、上記接続電極と下地電極膜を接続するための
リード導体が不要となり、半田バンプ接続素子の構成が
簡単になり、また、上記接続電極やリード導体を形成す
る工程が省略でき、半田バンプ接続素子の製造工程の簡
略化が図れる。
Further, since the base electrode film is formed on the connection portion on the bottom surface of the through hole and the solder bumps are connected on the base electrode film, the base electrode film shown in the present invention is the same as that of the conventional example. In addition, the connection electrode above the connection portion and the function of the base electrode film below the solder bump are combined. Further, the lead conductor for connecting the connection electrode and the base electrode film is not required, the structure of the solder bump connection element is simplified, and the step of forming the connection electrode and the lead conductor can be omitted, so that the solder bump connection can be achieved. The element manufacturing process can be simplified.

【0017】さらに、絶縁基板の上面に下地電極膜を形
成しないので、例えば、絶縁基板の上面および接続部の
上面に下地電極膜の材料を付着して導電膜を形成した
後、絶縁基板の上面の導電膜を全て取り除くことによっ
て接続部の上だけに下地電極膜を形成することが可能と
なり、従来例に示したようなレジストパターンを用いる
ことなく、簡単に下地電極膜を形成することができ、下
地電極膜の作製工程の簡略化および下地電極膜の作製時
間の短縮が図れ、半田バンプ接続素子の製造工程のより
簡略化および製造時間の短縮を図ることが可能である。
Further, since the base electrode film is not formed on the upper surface of the insulating substrate, for example, after the material of the base electrode film is attached to the upper surface of the insulating substrate and the upper surface of the connection portion to form the conductive film, the upper surface of the insulating substrate is formed. It becomes possible to form the base electrode film only on the connection portion by removing all the conductive films of, and it is possible to easily form the base electrode film without using the resist pattern as shown in the conventional example. The manufacturing process of the base electrode film can be simplified and the manufacturing time of the base electrode film can be shortened, and the manufacturing process of the solder bump connection element can be further simplified and the manufacturing time can be shortened.

【0018】[0018]

【発明の実施の形態】以下に、この発明に係る実施形態
例を図面に基づき説明する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

【0019】図1にはこの発明の製造方法により製造さ
れる半田バンプ接続素子において特徴的な半田バンプ部
分が示されている。この半田バンプ接続素子において特
徴的なことは、スルーホール5に半田バンプ3を収容
し、半田バンプ接続素子の小型化が容易となる構成とし
たことであり、それ以外の構成は前記従来例と同様であ
る。なお、この実施形態例の説明において、前記従来例
と同一名称部分には同一符号を付す。
FIG. 1 shows a product manufactured by the manufacturing method of the present invention .
The characteristic solder bump portion is shown in the solder bump connecting element. A characteristic of this solder bump connecting element is that the solder bump 3 is housed in the through hole 5 to facilitate the downsizing of the solder bump connecting element, and other configurations are the same as those of the conventional example. It is the same. In the description of this embodiment, the same reference numerals are given to the same names as those in the conventional example.

【0020】図1に示すように、シリコンで形成された
素子形成基板1には、該素子形成基板1に形成された素
子(図示せず)に接続する接続部4が形成されている。
上記接続部4はシリコンの素子形成基板1にボロンやリ
ンやアンチモン等の不純物を高濃度(例えば、1020cm
-3以上の濃度)に拡散して(ドープして)形成されてい
る。
As shown in FIG. 1, an element forming substrate 1 made of silicon is provided with a connecting portion 4 for connecting to an element (not shown) formed on the element forming substrate 1.
The connection portion 4 has a high concentration of impurities such as boron, phosphorus, and antimony (for example, 10 20 cm) on the silicon element formation substrate 1.
-Concentration of -3 or more) is formed by diffusion (doping).

【0021】上記素子形成基板1の上にはパイレックス
ガラス(商標)等のガラス基板で形成された絶縁基板2
(例えば、絶縁基板2の厚みが300μm)が接合され
ており、上記接続部4に対応する絶縁基板2の上面には
開口部が形成され、該開口部から前記接続部4に達する
スルーホール5が絶縁基板2に形成されている。
An insulating substrate 2 made of a glass substrate such as Pyrex glass (trademark) is provided on the element forming substrate 1.
(For example, the insulating substrate 2 has a thickness of 300 μm), and an opening is formed in the upper surface of the insulating substrate 2 corresponding to the connecting portion 4, and the through hole 5 reaching the connecting portion 4 from the opening is formed. Are formed on the insulating substrate 2.

【0022】上記スルーホール5の底面の接続部4の上
およびスルーホール5の内面には下地電極膜8が形成さ
れている。この下地電極膜8は、Crの層(例えば、層
の厚みは50nm)とNiの層(例えば、層の厚みは1μ
m)とAuの層(例えば、層の厚みは200nm)を下側
から順に積層形成した積層膜により形成されている。こ
の下地電極膜8に半田材料であるPbSn半田により形
成される半田バンプ3が接合されている。この半田バン
プ3は、図1に示すように、絶縁基板2の上面に突き出
してスルーホール5に収容されている。
A base electrode film 8 is formed on the connection portion 4 on the bottom surface of the through hole 5 and on the inner surface of the through hole 5. The base electrode film 8 includes a Cr layer (for example, the layer thickness is 50 nm) and a Ni layer (for example, the layer thickness is 1 μm).
m) and a layer of Au (for example, the thickness of the layer is 200 nm) are sequentially laminated from the bottom side. The solder bumps 3 made of PbSn solder, which is a solder material, are bonded to the base electrode film 8. As shown in FIG. 1, this solder bump 3 projects into the upper surface of the insulating substrate 2 and is accommodated in the through hole 5.

【0023】上記絶縁基板2の上側に突き出した半田バ
ンプ3は、例えば、図3に示すように、予め定められた
接続相手側の回路基板11の接続部(図示せず)に接続
される。図3に示される半田バンプ接続素子の例では、
素子形成基板1と絶縁基板2に囲まれた空間12が形成
され、この空間12にマイクロジャイロ、加速度セン
サ、コンデンサ等の素子14が収容されており、この素
子14は該素子14に接続する接続部4と下地電極膜8
と半田バンプ3を順に介して回路基板11の接続部に導
通接続され、回路基板11に形成される回路に上記素子
14を組み込むことができる。
The solder bumps 3 protruding above the insulating substrate 2 are connected to, for example, a predetermined connection portion (not shown) of the circuit board 11 on the connection partner side, as shown in FIG. In the example of the solder bump connection element shown in FIG. 3,
A space 12 surrounded by the element forming substrate 1 and the insulating substrate 2 is formed, and an element 14 such as a microgyro, an acceleration sensor, a capacitor, etc. is housed in the space 12, and the element 14 is connected to the element 14. Part 4 and base electrode film 8
The element 14 can be incorporated into a circuit formed on the circuit board 11 by being conductively connected to the connection portion of the circuit board 11 via the solder bumps 3 in order.

【0024】この半田バンプ接続素子は上記のように構
成されており、以下に、上記構成の半田バンプ接続素子
の製造方法の一例を説明する。まず、図2の(a)に示
すように、シリコンの素子形成基板1に素子(図示せ
ず)を形成すると共に、素子形成基板1の接続部4形成
領域にボロンやリンやアンチモン等の不純物を不純物拡
散技術手法を用いて拡散させて上記素子に接続する接続
部4を形成する。
[0024] Handa bump connection element of this is constituted as described above, will now be described an example of a method of manufacturing a solder bump connection element configured as described above. First, as shown in FIG. 2A, an element (not shown) is formed on a silicon element formation substrate 1, and impurities such as boron, phosphorus and antimony are formed in a connection portion 4 formation region of the element formation substrate 1. Is diffused using an impurity diffusion technique to form a connection portion 4 connected to the above element.

【0025】その後、図2の(b)に示すように、上記
素子形成基板1の上に予めスルーホール5が形成された
ガラス基板である絶縁基板2をスルーホール5を上記接
続部4に位置合わせして配置させ、素子形成基板1と絶
縁基板2の接触部分を陽極接合手法により接合する。
After that, as shown in FIG. 2B, the insulating substrate 2 which is a glass substrate in which the through holes 5 are formed in advance on the element forming substrate 1 is positioned at the through holes 5 at the connecting portions 4. They are arranged together, and the contact portion between the element forming substrate 1 and the insulating substrate 2 is joined by an anodic joining method.

【0026】次に、図2の(c)に示すように、絶縁基
板2の上側から下地電極膜8の材料を蒸着やスパッタ等
の成膜形成技術により付着させ、絶縁基板2の上面と、
スルーホール5の底面の接続部4の上と、スルーホール
5の内面とに下地電極膜8となる領域を含む導電膜8a
を形成する。この実施形態例では、前記の如く、導電膜
8aはCr,Ni,Auの各層が下から順に積層形成さ
れた積層膜で構成されているので、絶縁基板2の上側か
らCr,Ni,Auを順に蒸着やスパッタ等の成膜形成
技術により付着させて導電膜8aを形成する。
Next, as shown in FIG. 2C, the material of the base electrode film 8 is attached from the upper side of the insulating substrate 2 by a film forming technique such as vapor deposition or sputtering, and the upper surface of the insulating substrate 2 and
A conductive film 8a including a region to be the base electrode film 8 on the connection portion 4 on the bottom surface of the through hole 5 and on the inner surface of the through hole 5.
To form. In this embodiment, as described above, the conductive film 8a is composed of a laminated film in which each layer of Cr, Ni and Au is laminated in order from the bottom, so that Cr, Ni and Au are deposited from the upper side of the insulating substrate 2. The conductive film 8a is formed by sequentially adhering it by a film forming technique such as vapor deposition or sputtering.

【0027】然る後、図2の(d)に示すように、絶縁
基板2の上面の導電膜8aを研磨技術により全て取り除
くことにより、接続部4の上に下地電極膜8を形成す
る。そして、上記スルーホール5の内部にPbSn半田
材料を印刷手法等により充填し、その後、上記素子形成
基板1を炉内に収容して上記PbSn半田材料を溶融
し、該PbSn半田材料を下地電極膜8に接合させると
共に、PbSn半田材料を絶縁基板2の上側に突き出さ
せて半田バンプ3を形成して半田バンプ接続素子が完成
する。
After that, as shown in FIG. 2D, the conductive film 8a on the upper surface of the insulating substrate 2 is completely removed by a polishing technique to form the base electrode film 8 on the connection portion 4. Then, a PbSn solder material is filled in the through hole 5 by a printing method or the like, and then the element forming substrate 1 is housed in a furnace to melt the PbSn solder material, and the PbSn solder material is used as a base electrode film. 8 and the PbSn solder material is projected to the upper side of the insulating substrate 2 to form the solder bump 3 to complete the solder bump connecting element.

【0028】この実施形態例によれば、スルーホール5
に半田バンプ3を収容する構成としたので、絶縁基板2
の上面にスルーホール5を形成する領域と、半田バンプ
3を形成する領域とを別個に確保する必要がなく、絶縁
基板2の上面に半田バンプ3の形成領域を設けなくて済
むので、絶縁基板2の上面の面積を削減することがで
き、絶縁基板2の小型化を図ることができる。
According to this embodiment example, the through hole 5
Since the solder bumps 3 are housed in the insulating substrate 2,
Since it is not necessary to separately secure a region for forming the through holes 5 and a region for forming the solder bumps 3 on the upper surface of the insulating substrate 2, it is not necessary to provide a region for forming the solder bumps 3 on the upper surface of the insulating substrate 2. The area of the upper surface of 2 can be reduced, and the size of the insulating substrate 2 can be reduced.

【0029】また、スルーホール5の底面の接続部4の
上に下地電極膜8を形成し、下地電極膜8の上に半田バ
ンプ3を接合させるので、下地電極膜8は、前記図4に
示した接続電極6と下地電極膜8の機能を兼用する構成
とすることができる上に、上記接続電極6と下地電極膜
8を接続するリード導体10が不要となり、リード導体
10を省略することができる。このように、接続電極6
とリード導体10を省略できるので、半田バンプ接続素
子の半田バンプ部分の構成が簡単になるし、接続電極6
とリード導体10を作製する工程を省くことができ、半
田バンプ接続素子の製造工程の簡略化を図ることができ
る。
Further, since the base electrode film 8 is formed on the connection portion 4 on the bottom surface of the through hole 5 and the solder bump 3 is bonded onto the base electrode film 8, the base electrode film 8 is formed as shown in FIG. The lead electrode 10 for connecting the connection electrode 6 and the base electrode film 8 can be omitted, and the lead conductor 10 can be omitted. You can In this way, the connection electrode 6
Since the lead conductor 10 can be omitted, the structure of the solder bump portion of the solder bump connecting element is simplified and the connecting electrode 6
Thus, the step of manufacturing the lead conductor 10 can be omitted, and the manufacturing steps of the solder bump connection element can be simplified.

【0030】さらに、絶縁基板2の上面に半田バンプ3
を形成しないので、半田バンプ3の下地電極膜8と、前
記リード導体10とを絶縁基板2の上面に形成しなくて
済み、このことにより、絶縁基板2の上側から成膜形成
技術により下地電極膜8の材料を絶縁基板2の上面と、
接続部4と、スルーホール5の内面とに下地電極膜8と
なる領域を含む導電膜8aを形成した後、絶縁基板2の
上面の導電膜8aを全て取り除くだけで、簡単に、少な
くとも接続部4の上に選択的に下地電極膜8を形成する
ことができる。
Further, the solder bumps 3 are formed on the upper surface of the insulating substrate 2.
Therefore, it is not necessary to form the base electrode film 8 of the solder bump 3 and the lead conductor 10 on the upper surface of the insulating substrate 2, and thus the base electrode film is formed from the upper side of the insulating substrate 2 by the film forming technique. The material of the film 8 is the upper surface of the insulating substrate 2,
After forming the conductive film 8a including the region to be the base electrode film 8 on the connection part 4 and the inner surface of the through hole 5, all of the conductive film 8a on the upper surface of the insulating substrate 2 is simply removed to easily perform at least the connection part. The base electrode film 8 can be selectively formed on the substrate 4.

【0031】このように、従来の面倒なレジストパター
ンを用いた下地電極膜8の形成工程を行うことなく、簡
単に下地電極膜8を作製することができ、下地電極膜8
の形成工程の簡略化および下地電極膜8の作製時間の短
縮を図ることができる。このことから、大量の半田バン
プ接続素子を効率良く製造することが可能となり、半田
バンプ接続素子の価格を下げることができ、安価な半田
バンプ接続素子を提供することが可能である。
As described above, the base electrode film 8 can be easily manufactured without performing the conventional step of forming the base electrode film 8 using a troublesome resist pattern.
It is possible to simplify the formation process of the underlayer and shorten the production time of the base electrode film 8. From this, it is possible to efficiently manufacture a large number of solder bump connection elements, reduce the cost of the solder bump connection elements, and provide an inexpensive solder bump connection element.

【0032】なお、この発明は上記実施形態例に限定さ
れるものではなく、様々な実施の形態を採り得る。例え
ば、上記実施形態例では、素子形成基板1はシリコンで
形成されていたが、シリコン以外の半導体や、ガラス等
の絶縁体等により形成してもよい。また、絶縁基板2は
ガラス材料により形成されていたが、ガラス以外の絶縁
体により形成してもよい。
The present invention is not limited to the above-mentioned embodiment, and various embodiments can be adopted. For example, although the element formation substrate 1 is formed of silicon in the above embodiment, it may be formed of a semiconductor other than silicon, an insulator such as glass, or the like. Although the insulating substrate 2 is made of a glass material, it may be made of an insulator other than glass.

【0033】さらに、上記実施形態例では、素子形成基
板1に不純物を拡散させて接続部4を形成していたが、
素子形成基板1の接続部4形成領域にポリシリコンを設
け該ポリシリコンにより接続部4を形成してもよいし、
アルミニウムや金等の導体により接続部4を構成しても
よい。
Furthermore, in the above embodiment, the connection portion 4 was formed by diffusing impurities in the element formation substrate 1.
Polysilicon may be provided in the connection portion 4 formation region of the element forming substrate 1 to form the connection portion 4 with the polysilicon.
You may comprise the connection part 4 with conductors, such as aluminum and gold.

【0034】さらに、上記実施形態例では、下地電極膜
8はCr,Ni,Auの各層を順に積層形成した積層膜
であったが、下地電極膜8は導体材料により形成される
単層の膜により構成してもよいし、導体材料の異なる層
を2層積層した膜により構成してもよいし、導体材料の
異なる層を4層以上積層した膜により構成してもよい。
また、下地電極膜8の材料は、上記Cr,Ni,Auに
限定されるものではなく、様々な材料により構成するこ
とができる。
Further, in the above embodiment, the base electrode film 8 is a laminated film in which each layer of Cr, Ni and Au is laminated in order, but the base electrode film 8 is a single layer film made of a conductive material. Or a film in which two layers of different conductor materials are laminated, or a film in which four or more layers of different conductor materials are laminated.
The material of the base electrode film 8 is not limited to the above Cr, Ni, Au, and can be composed of various materials.

【0035】さらに、上記実施形態例では、下地電極膜
8の材料を蒸着やスパッタ等により絶縁基板2の上側か
ら付着させていたが、蒸着やスパッタ以外のフォトリソ
技術や印刷技術等の成膜形成技術により下地電極膜8の
材料を絶縁基板2の上面と接続部の上面に付着させても
よい。なお、スルーホール5の内面は、導電膜8aが形
成されなくてもよい。
Further, in the above embodiment, the material of the base electrode film 8 is adhered from the upper side of the insulating substrate 2 by vapor deposition, sputtering or the like. However, film formation by photolithography technology or printing technology other than vapor deposition or sputtering. The material of the base electrode film 8 may be attached to the upper surface of the insulating substrate 2 and the upper surface of the connection portion by a technique. The conductive film 8a may not be formed on the inner surface of the through hole 5.

【0036】さらに、上記実施形態例では、絶縁基板2
の上面の下地電極膜8を研磨技術により全て取り除いて
いたが、研磨技術以外の手法により絶縁基板2の上面の
下地電極膜8を取り除いてもよい。
Further, in the above embodiment, the insulating substrate 2 is used.
Although the base electrode film 8 on the upper surface of 1 is completely removed by the polishing technique, the base electrode film 8 on the upper surface of the insulating substrate 2 may be removed by a method other than the polishing technique.

【0037】[0037]

【発明の効果】この発明によれば、スルーホールに半田
バンプを収容するので、半田バンプの形成領域をスルー
ホールの形成領域と別個に設けなくてよく、絶縁基板の
上面に半田バンプの形成領域を確保しなくて済むので、
絶縁基板の上面の面積を削減することができる。すなわ
ち、絶縁基板の小型化を図ることができ、このことに起
因して半田バンプ接続素子の小型化が容易となる。
According to the present invention, since the solder bumps are accommodated in the through holes, it is not necessary to provide the solder bump formation region separately from the through hole formation region, and the solder bump formation region is formed on the upper surface of the insulating substrate. Since it is not necessary to secure
The area of the upper surface of the insulating substrate can be reduced. That is, the insulating substrate can be downsized, which facilitates downsizing of the solder bump connecting element.

【0038】また、スルーホールの底面の接続部の上に
下地電極膜を形成し、該下地電極膜の上に半田バンプを
接合するので、上記下地電極膜は、接続部の上の接続電
極と下地電極膜の機能を兼用する構成となり、上記接続
電極を省略することができる。しかも、上記接続電極と
下地電極膜を接続するリード導体を省略することができ
る。上記のように、接続電極とリード導体を省略できる
ので、半田バンプ接続素子の構成が簡単になるし、上記
接続電極の形成工程とリード導体の形成工程を省くこと
ができ、半田バンプ接続素子の製造工程を簡略化するこ
とができる。
Further, since the base electrode film is formed on the connection portion on the bottom surface of the through hole and the solder bump is bonded on the base electrode film, the base electrode film is connected to the connection electrode on the connection portion. Since the structure also has the function of the base electrode film, the connection electrode can be omitted. Moreover, the lead conductor connecting the connection electrode and the base electrode film can be omitted. As described above, since the connection electrode and the lead conductor can be omitted, the structure of the solder bump connection element can be simplified, and the step of forming the connection electrode and the step of forming the lead conductor can be omitted. The manufacturing process can be simplified.

【0039】さらに、絶縁基板の上面に下地電極膜やリ
ード導体を形成しないので、この発明に示した半田バン
プ接続素子の製造方法を採用することが可能である。す
なわち、下地電極膜を形成するときには、成膜形成技術
により下地電極膜の材料を付着させて少なくとも接続部
の上面と絶縁基板の上面に導電膜を形成し、その後、絶
縁基板の上面の導電膜を全て取り除くことにより下地電
極膜を形成することができる。このように、絶縁基板の
上面の導電膜を全て取り除くだけで、下地電極膜を接続
部の上面に選択的に形成することができるので、簡単に
下地電極膜を形成することができる。
Further, since the base electrode film and the lead conductor are not formed on the upper surface of the insulating substrate, it is possible to adopt the method of manufacturing the solder bump connecting element according to the present invention. That is, when forming the base electrode film, the material of the base electrode film is attached by a film forming technique to form a conductive film on at least the upper surface of the connection portion and the upper surface of the insulating substrate, and then the conductive film on the upper surface of the insulating substrate. The base electrode film can be formed by removing all of these. In this way, the base electrode film can be selectively formed on the upper surface of the connection portion by simply removing all the conductive film on the upper surface of the insulating substrate, so that the base electrode film can be easily formed.

【0040】絶縁基板の上面の下地電極膜を研磨技術に
より全て取り除く発明にあっては、従来のように下地電
極膜を形成する領域を規制するレジストパターンを用い
て下地電極膜を形成する等の面倒な工程を省略すること
ができ、下地電極膜の作製工程の簡略化および下地電極
膜の作製時間の大幅な短縮を図ることができる。
In the invention in which all the underlying electrode film on the upper surface of the insulating substrate is removed by the polishing technique, the underlying electrode film is formed by using a resist pattern that regulates the region where the underlying electrode film is formed, as in the prior art. It is possible to omit a troublesome process, simplify the manufacturing process of the base electrode film, and significantly shorten the manufacturing time of the base electrode film.

【0041】このように、半田バンプ接続素子の製造工
程の簡略化および製造時間の短縮が図れることから、半
田バンプ接続素子を効率良く製造することができ、この
ことにより、半田バンプ接続素子の価格を低減すること
ができ、安価な半田バンプ接続素子を提供することが可
能である。
As described above, since the manufacturing process of the solder bump connecting element can be simplified and the manufacturing time can be shortened, the solder bump connecting element can be efficiently manufactured, which allows the price of the solder bump connecting element to be improved. And it is possible to provide an inexpensive solder bump connection element.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明に係る半田バンプ接続素子の一例を半
田バンプ部分を抜き出して示す説明図である。
FIG. 1 is an explanatory view showing an example of a solder bump connecting element according to the present invention in which a solder bump portion is extracted.

【図2】半田バンプ接続素子の製造方法の一例を半田バ
ンプ部分を抜き出して示す説明図である。
FIG. 2 is an explanatory diagram showing an example of a method of manufacturing a solder bump connection element by extracting a solder bump portion.

【図3】この発明に係る半田バンプ接続素子の一例を示
す説明図である。
FIG. 3 is an explanatory diagram showing an example of a solder bump connection element according to the present invention.

【図4】半田バンプ接続素子の半田バンプ部分の従来例
を示す説明図である。
FIG. 4 is an explanatory diagram showing a conventional example of a solder bump portion of a solder bump connecting element.

【符号の説明】[Explanation of symbols]

1 素子形成基板 2 絶縁基板 3 半田バンプ 4 接続部 5 スルーホール 8 下地電極膜 1 element formation substrate 2 insulating substrate 3 Solder bump 4 connection 5 through holes 8 Base electrode film

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平4−94131(JP,A) 特開 平2−52436(JP,A) 特開 平6−13382(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/60 311 H01L 21/60 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-94131 (JP, A) JP-A-2-52436 (JP, A) JP-A-6-13382 (JP, A) (58) Field (Int.Cl. 7 , DB name) H01L 21/60 311 H01L 21/60

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 素子が形成される素子形成基板には上記
素子に接続する接続部が形成され、上記素子形成基板の
上には絶縁基板が接合され、上記接続部に対応する絶縁
基板の上面には開口部が形成され該開口部から上記接続
部に達するスルーホールが上記絶縁基板に形成されてい
る半田バンプ接続素子の製造方法において、まず、上記
素子と接続部が形成された素子形成基板にスルーホール
が形成された絶縁基板を上記スルーホールに接続部を位
置合わせして接合し、次に、成膜形成技術により下地電
極膜の材料を付着させて少なくとも絶縁基板の上面と接
続部の上面に導電膜を形成し、然る後、絶縁基板の上面
の導電膜を全て取り除くことにより接続部の上面に下地
電極膜を形成し、その後、スルーホールの内部に半田材
料を収容し、該半田材料を溶融して半田バンプを形成し
該半田バンプを絶縁基板の上側に突き出させると共に、
半田バンプと接続部の上面の下地電極膜を接合する半田
バンプ接続素子の製造方法。
1. An element forming substrate on which an element is formed is formed with a connecting portion for connecting to the element, and an insulating substrate is joined on the element forming substrate, and an upper surface of the insulating substrate corresponding to the connecting portion. In a method of manufacturing a solder bump connecting element, wherein an opening is formed in the insulating substrate and a through hole reaching the connecting portion from the opening is formed in the insulating substrate, first, an element forming substrate in which the element and the connecting portion are formed. An insulating substrate having a through hole formed therein is joined to the through hole by aligning the connection portion, and then a material for the base electrode film is attached by a film forming technique to form at least the upper surface of the insulating substrate and the connection portion. A conductive film is formed on the upper surface, and then the conductive film on the upper surface of the insulating substrate is completely removed to form a base electrode film on the upper surface of the connection portion. solder The material is melted to form a solder bump, and the solder bump is projected to the upper side of the insulating substrate.
A method for manufacturing a solder bump connecting element, which comprises joining a solder bump and a base electrode film on the upper surface of a connecting portion.
【請求項2】 絶縁基板の上面の導電膜は研磨技術によ
り全て取り除かれることを特徴とした請求項記載の半
田バンプ接続素子の製造方法。
2. A method for producing a solder bump connection element according to claim 1, wherein the wherein a conductive film on the upper surface of the insulating substrate is removed all the polishing technique.
JP35458996A 1996-12-19 1996-12-19 Manufacturing method of solder bump connection element Expired - Fee Related JP3405102B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP35458996A JP3405102B2 (en) 1996-12-19 1996-12-19 Manufacturing method of solder bump connection element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP35458996A JP3405102B2 (en) 1996-12-19 1996-12-19 Manufacturing method of solder bump connection element

Publications (2)

Publication Number Publication Date
JPH10189607A JPH10189607A (en) 1998-07-21
JP3405102B2 true JP3405102B2 (en) 2003-05-12

Family

ID=18438581

Family Applications (1)

Application Number Title Priority Date Filing Date
JP35458996A Expired - Fee Related JP3405102B2 (en) 1996-12-19 1996-12-19 Manufacturing method of solder bump connection element

Country Status (1)

Country Link
JP (1) JP3405102B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005241457A (en) * 2004-02-26 2005-09-08 Hamamatsu Photonics Kk Infrared sensor, and manufacturing method therefor
CN100372081C (en) * 2005-06-21 2008-02-27 友达光电股份有限公司 Picture-element electrode switch element and mfg. method
JP5558189B2 (en) * 2010-04-26 2014-07-23 浜松ホトニクス株式会社 Infrared sensor and manufacturing method thereof

Also Published As

Publication number Publication date
JPH10189607A (en) 1998-07-21

Similar Documents

Publication Publication Date Title
JP3186941B2 (en) Semiconductor chips and multi-chip semiconductor modules
EP0238089B1 (en) Three-dimensional integrated circuit and manufacturing method therefor
JP2001044357A (en) Semiconductor device and manufacture thereof
JPH07169796A (en) Semiconductor device and its manufacture
USRE48421E1 (en) Flip chip and method of making flip chip
JP2002343924A (en) Semiconductor device and manufacturing method therefor
JP2001053178A (en) Electronic component with electronic circuit device sealed and mounted on circuit board, and manufacture of the electronic component
US6998327B2 (en) Thin film transfer join process and multilevel thin film module
JP2000195861A (en) Semiconductor device and method of producing the same
JPH10178046A (en) Mounting method for semiconductor chip
JP3405102B2 (en) Manufacturing method of solder bump connection element
US6763585B2 (en) Method for producing micro bump
JP3038703B2 (en) Semiconductor device, method of manufacturing the same, and method of mounting the same
JP2001326250A (en) Flip-chip semiconductor device and method of manufacture
JP3702062B2 (en) Pressure sensor device
US20050062146A1 (en) Semiconductor device and method of fabricating semiconductor device
JPH10163411A (en) Lsi module and manufacture thereof
JPH07283334A (en) Airtightly sealed electronic parts
JP3152005B2 (en) Manufacturing method of semiconductor acceleration sensor
JPH11204519A (en) Semiconductor device and its manufacture
EP1906441A1 (en) Wafer with semiconductor devices and method of manufacturing the same
JPH0766207A (en) Surface mount device, manufacture thereof, and soldering method
US20050106785A1 (en) Method for manufacturing a housing for a chip with a micromechanical structure
JP2665914B2 (en) Semiconductor device and manufacturing method thereof
JPS646554B2 (en)

Legal Events

Date Code Title Description
FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090307

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees