JPS62109514U - - Google Patents
Info
- Publication number
- JPS62109514U JPS62109514U JP19971485U JP19971485U JPS62109514U JP S62109514 U JPS62109514 U JP S62109514U JP 19971485 U JP19971485 U JP 19971485U JP 19971485 U JP19971485 U JP 19971485U JP S62109514 U JPS62109514 U JP S62109514U
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- potential point
- emitters
- resistors
- collectors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
- Amplifiers (AREA)
Description
第１図は本考案にかかる増幅器の一実施例を示
す回路図、第２図は従来の増幅器の一例を示す回
路図である。
Ｑ１１，Ｑ１２，Ｑ１５，Ｑ１６…差動増幅ト
ランジスタ、Ｑ１３，Ｑ１４，Ｑ１７，Ｑ１８…
エミツタホロワトランジスタ、Ｉ１１，Ｉ１２…
電流源、Ｒ１１，〜Ｒ２０…抵抗。
FIG. 1 is a circuit diagram showing an embodiment of an amplifier according to the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional amplifier. Q11, Q12, Q15, Q16...Differential amplification transistor, Q13, Q14, Q17, Q18...
Emitter follower transistors, I11, I12...
Current source, R11, ~R20...resistance.
Claims (1)
点に接続され、コレクタが第１、第２の抵抗を介
して第２の電位点に接続された第１、第２のトラ
ンジスタを有し、前記第１のトランジスタのベー
スに信号が入力され、第１、第２のトランジスタ
のコレクタからリミツトされた信号が取出される
１の差動増幅手段と、 この差動増幅手段の各トランジスタからの信号
がベースに入力され、コレクタは第２の電位点に
接続され、エミツタは所定の負荷抵抗を介して第
１の電位点に接続された第３、第４トランジスタ
と、 これら第３、第４トランジスタのエミツタに現
れる電圧をそれぞれ前記第１、第２のトランジス
タのベースに帰還する第３、第４の抵抗と、 前記第３、第４トランジスタのエミツタからの
信号がそれぞれベースに供給される第５、第６ト
ランジスタを差動接続し、そのエミツタを電流源
を介して第１の電位点に接続し、コレクタと第２
電位点間に接続された負荷抵抗を介して差動出力
信号を出力する第２の差動増幅手段とを具備し、 前記第１、第２の抵抗および第３、第４の抵抗
の値をそれぞれ等しくすることで前記第１の差動
増幅手段でのオフセツトを解消する増幅装置。[Claims for Utility Model Registration] The emitters are connected to the first potential point via current sources, and the collectors are connected to the second potential point via the first and second resistors. 1 differential amplification means having 2 transistors, a signal is input to the base of the first transistor, and a limited signal is taken out from the collectors of the first and second transistors; a signal from each transistor of the means is input to the base, the collector is connected to the second potential point, and the emitter is connected to the first potential point via a predetermined load resistance, third and fourth transistors; third and fourth resistors that feed back voltages appearing at the emitters of the third and fourth transistors to the bases of the first and second transistors, respectively; and signals from the emitters of the third and fourth transistors, respectively. The fifth and sixth transistors supplied to the base are differentially connected, their emitters are connected to the first potential point via a current source, and the collectors and the second
and second differential amplification means for outputting a differential output signal via a load resistor connected between potential points, and the values of the first and second resistors and the third and fourth resistors are An amplifier device that eliminates offset in the first differential amplification means by making them equal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19971485U JPS62109514U (en) | 1985-12-27 | 1985-12-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19971485U JPS62109514U (en) | 1985-12-27 | 1985-12-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62109514U true JPS62109514U (en) | 1987-07-13 |
Family
ID=31161595
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19971485U Pending JPS62109514U (en) | 1985-12-27 | 1985-12-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62109514U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03232308A (en) * | 1989-11-22 | 1991-10-16 | Canon Inc | Direct-coupled grounded-base amplifier, semiconductor device and information processor equipped with same amplifier |
-
1985
- 1985-12-27 JP JP19971485U patent/JPS62109514U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03232308A (en) * | 1989-11-22 | 1991-10-16 | Canon Inc | Direct-coupled grounded-base amplifier, semiconductor device and information processor equipped with same amplifier |
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